CN108108564A - The apparatus and method that a kind of raising system starts speed - Google Patents
The apparatus and method that a kind of raising system starts speed Download PDFInfo
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- CN108108564A CN108108564A CN201711472887.4A CN201711472887A CN108108564A CN 108108564 A CN108108564 A CN 108108564A CN 201711472887 A CN201711472887 A CN 201711472887A CN 108108564 A CN108108564 A CN 108108564A
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- nandflash
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Abstract
The apparatus and method that a kind of raising system starts speed can optimize circuit structure, shorten the signal delay between CPU to NANDFLASH, improve NANDFLASH access frequencys, so as to improve the startup speed of whole system, promote user experience.Including CPU, low delay level translator, NANDFLASH, memory bar/memory grain；Wherein, by being connected after low delay level translator progress level conversion with NANDFLASH, memory bar/memory grain is directly connected the NANDFLASH signals of the CPU with central processing unit.CPLD is used into line level phase inversion ratio with common, and the present invention uses low delay two-way level converting device realization central processing unit（CPU）NANDFLASH interfaces are to the level translation between NANDFLASH so that central processing unit（CPU）Signal between NANDFLASH is delayed is reduced to below 10ns, central processing unit by 20ns（CPU）Can NANDFLASH be accessed with higher frequency, improve the startup speed of whole system.
Description
Technical field
The present invention relates to circuit design fields, and in particular to the apparatus and method that a kind of raising system starts speed.
Background technology
In communication apparatus, a kind of common CPU mini systems circuit block diagram is as shown in Figure 1, the mini system includes processor
(CPU), memory bar/memory grain, programmable logic chip (CPLD), NANDFLASH.Wherein CPU is the core of entire mini system
The heart, the other circuits of mini system are that it is serviced；Memory bar/memory grain is the space that program performs；CPLD is used to implement periphery
The functions such as Interface Expanding and level conversion, NANDFLASH are used to store BOOT and system version.After the completion of system electrification, CPU is visited
It asks NANDFLASH, obtains wherein information, system is enable smoothly to start.CPU directly determines the access speed of NANDFLASH
The startup speed of whole equipment.
Communication apparatus, if the NANDFLASH interfaces of majority CPU in router, interchanger are 1.8V level standards, and it is normal
NANDFLASH is 3.3V level standards, it will usually the level conversion of 1.8V to 3.3V is realized using piece of CPLD.Signal
After CPLD, the delay of 20ns or so can be brought, the settling time that CPU reads NANDFLASH data-signals is influenced, in CPU
NAND FLASH controller, which must increase, to be read enable signal effective time and could meet the requirement of itself sampled data settling time.
This undoubtedly increases the cycle that CPU reads NANDFLASH, limits access frequencys of the CPU to NANDFLASH, causes opening for equipment
The dynamic time increases.While the conversion of NANDFLASH interface levels is realized, delay caused by reducing level conversion improves CPU and visits
The frequency of NANDFLASH is asked, by the startup speed for the system that improves.
The content of the invention
The method that a kind of raising system proposed by the present invention starts speed can optimize circuit structure, shorten CPU and arrive
Signal delay between NANDFLASH, improves NANDFLASH access frequencys, so as to improve the startup speed of whole system, is promoted
User experience.
To achieve the above object, present invention employs following technical schemes：
A kind of raising system starts the device of speed, including central processing unit (CPU), low delay level translator,
NANDFLASH, memory bar/memory grain.The NANDFLASH signals of wherein described central processing unit (CPU) pass through low delay electricity
Flat turn parallel operation carry out level conversion after be connected with NANDFLASH, memory bar/memory grain directly with central processing unit (CPU) phase
Even.
When central processing unit (CPU) carries out write operation to NANDFLASH30, central processing unit (CPU) will be prolonged by low
When level translator send control signal, order, address and data to NANDFLASH30.At this point, the direction of all signals is all
NANDFLASH30 is sent to by central processing unit (CPU).Assuming that the signal that central processing unit (CPU) is sent is in low delay level
Delay in converter is T2, and each chip chamber PCB trace delay is ignored.When writing NANDFLASH30 operations, central processing
The delay that all signals that device (CPU) is sent can all undergo T2 reaches NANDFLASH, without considering level conversion device difference end
In the case of mouthful delay difference, order that NANDFLASH30 is received, address, data phase relation are with central processing unit (CPU)
The signal sequence relation issued is essentially identical.T2 delays size has no effect on central processing unit (CPU) to NANDFLASH30's
Write operation sequential.The frequency that central processing unit (CPU) writes NANDFLASH can reach NANDFLASH/ central processing units (CPU)
The middle supported upper limiting frequency of NAND FLASH controller.
But for read operation, central processing unit (CPU) sends after control signal first passes around T2 delays and reaches
The data-signal of reading is sent to low delay level translator by NANDFLASH, NANFLASH, in being reached using the delay of T2
Central processor (CPU).Central processing unit (CPU) receives the time of data-signal than direct plug-in NANDFLASH30 at this time
Read operation is carried out to be delayed 2 T2 times.This delay will make central processing unit (CPU) sampled data signal window shorten 2*
T2, the effective pulsewidth of reading enable signal that designer must export NAND FLASH controller in big central processing unit (CPU) increase
The big 2*T2 times read NANDFLASH30 timing requirements to meet central processing unit (CPU).Read the increasing of enable signal effective time
Add, entire tead cycle time is caused to increase, NANDFALSH read operations speed reduces.The low delay level translator for selecting T2 small
Carrying out level conversion will be effectively improved this case.
As shown from the above technical solution, the present invention using low delay level translator replace CPLD carry out 1.8V and 3.3V it
Between level conversion, such as TXB0304RUTR self-inductions direction low delay two-way level converting device, the chip be input to output
Delay is less than or equal to 4.5ns, and energy automatic sensing input and output direction can realize level conversion between 1.8V and 3.3V, highest letter
Number rate reaches 140Mbps.After the program, 2*T2 delays shorten to 9ns by 20ns, and NANDFLASH30 reads useful signal
Low duration can shorten 11ns, and the read operation cycle can shorten 11ns, improve NANDFLASH30 and read behaviour's rate.
The technical effects of the invention are that：CPLD is used into line level phase inversion ratio with common, it is of the invention to use low delay
Two-way level converting device realizes central processing unit (CPU) NANDFLASH interfaces to the level translation between NANDFLASH so that
Signal of the central processing unit (CPU) between NANDFLASH is delayed is reduced to below 10ns, central processing unit (CPU) by 20ns
Can NANDFLASH be accessed with higher frequency, improve the startup speed of whole system.
Description of the drawings
Fig. 1 is common CPU mini system circuit structure block diagrams；
Fig. 2 is present system circuit block diagram；
Fig. 3 is CPU write NANDFLASH sequence diagrams；
Fig. 4 is that CPU reads NANDFLASH sequence diagrams.
Specific embodiment
The present invention will be further described below in conjunction with the accompanying drawings：
As shown in Fig. 2, a kind of raising system described in the present embodiment starts the device of speed, including central processing unit
(CPU) 10, low delay two-way level converting device 20, NANDFLASH30, memory bar/memory grain 40.
The NANDFLASH interfaces of the central processing unit (CPU) 10 realize 1.8V by low delay electrical level transferring chip 20
It is connected after turning 3.3V with NANDFLASH30.The BOOT and software version needed when system starts is stored in NANDFLASH30.
After system electrification, central processing unit (CPU) 10 selects to start from NANDFLASH30, central processing unit according to configuration
(CPU) 10 the sequential for accessing NANDFLASH30 is generated, obtains BOOT and software version.
When 10 couples of NANDFLASH30 of central processing unit (CPU) carry out write operation, central processing unit (CPU) 10 is sent to
The sequential of NANDFLASH30, such as Fig. 3, it is necessary to meet NANDFLASH write operation timing requirements.These signal sequences can pass through
Central processing unit (CPU) 10 register is configured to realize.When carrying out write operation, all signals are all by central processing unit (CPU)
10 send, and NANDFLASH30 is reached after low delay electrical level transferring chip 20.20 each passage of low delay electrical level transferring chip it
Between delay difference it is minimum, entire NANDFLASH30 is write timing requirements influence can be ignored.Before timing requirements are met
It puts, the write enable signal cycle is shorter, and the speed for writing NANDFLASH30 is faster.What low delay electrical level transferring chip 20 was brought
4.5ns is delayed, and does not influence 10 pairs of NANDFLASH30 accessing time sequences of central processing unit (CPU).
When 10 couples of NANDFLASH30 of central processing unit (CPU) carry out read operation, central processing unit (CPU) 10 will first be sent out
Piece choosing (CE_B), order is sent to latch enabled (CLE), address latch enable (ALE), write enabled (WE_B), read enabled (RE_B) this
A little control signals are to low delay electrical level transferring chip 20, and after 4.5ns is delayed, these signals reach NANDFLASH30.
TREA times of the NANDFLASH30 after RE_B signal trailing edges sends out data-signal to low delay level conversion device 20
(DATA), data-signal (DATA) is sent to central processing unit in low delay level conversion device 20 after 4.5ns is delayed
(CPU)10.The sampled signal window of 10 pairs of data-signals of central processing unit (CPU) is that TRP-TREA+TRHOH. wherein TRP are
RE_B effective pulse widths, TREA are the time of output data after NANDFLASH30 receives RE_B effectively, and TRHOH is RE_B letters
Number draw high the time that rear NANDFLASH30 output datas are kept, such as Fig. 4.After low delay electrical level transferring chip 20, reach
The RE_B useful signals of NANDFLASH30 have been delayed 4.5ns in fact, this causes the time of NANDFLASH30 output datas
Also can be delayed 4.5ns.The data of NANDFLASH30 outputs will also just reach central processing by low delay level conversion device 20
Device (CPU) 10, this so that data are more late 9ns than the directly plug-in NANDFLASH30 of central processing unit (CPU) 10.By adjusting center
The register configuration of NAND FLASH controller in processor (CPU), enables RB_B useful signals to shift to an earlier date 9ns to ensure data
There are enough foundation, retention time correctly to be sampled.
In the present embodiment, the low delay two-way level converting device of use, delay is only 4.5ns, with carrying out electricity using CPLD
Flat turn commutation ratio, read-write cycle can shorten 11ns.By carrying out reasonable disposition to central processing unit (CPU) 10, can improve
NANDFALSH access speeds, and then improve the startup speed of whole system.
Embodiment described above is only that the preferred embodiment of the present invention is described, not to the model of the present invention
It encloses and is defined, on the premise of design spirit of the present invention is not departed from, those of ordinary skill in the art are to the technical side of the present invention
The various modifications and improvement that case is made, should all fall within the scope of protection of the present invention.
Claims (7)
1. a kind of raising system starts the device of speed, it is characterised in that：Including CPU (10), low delay level translator (20),
NANDFLASH (30), memory bar/memory grain (40)；Wherein, the NANDFLASH signals of the CPU (10) pass through low delay electricity
Flat turn parallel operation (20) is connected after carrying out level conversion with NANDFLASH (30), and memory bar/memory grain (40) is directly and centre
Device (10) is managed to be connected.
2. a kind of method that raising system starts speed, it is characterised in that：Include the following steps：
Step 1：When CPU (10) carries out write operation to NANDFLASH (30), CPU (10) will pass through low delay level translator
(20) control signal, order, address and data are sent to NANDFLASH (30), the direction of all signals is all by central processing
Device CPU (10) is sent to NANDFLASH (30)；
Step 2：Assuming that delay of the signal that sends of central processor CPU (10) in low delay level translator (20) is T2,
Each chip chamber PCB trace delay is ignored；When writing NANDFLASH (30) operations, all signals that CPU (10) is sent all can be through
The delay for going through T2 reaches NANDFLASH (30), in the case of without considering level conversion device different port delay difference,
Order that NANDFLASH (30) is received, address, data phase relation are basic with the signal sequence relation that CPU (10) is issued
It is identical；
Step 3：When CPU (10) carries out read operation to NANDFLASH (30), CPU (10) sends control signal and first passes around T2
NANDFLASH (30) is reached after delay, the data-signal of reading is sent to low delay level translator by NANDFLASH (30)
(20), central processing unit (CPU) 10 is reached using the delay of T2；CPU (10) receives time of data-signal and has compared at this time
Directly plug-in NANDFLASH (30) carries out read operation and has been delayed 2 T2 times；This delay will make CPU (10) sampled data
Signal window shortens 2*T2.
3. the method that raising system according to claim 2 starts speed, it is characterised in that：T2 is delayed in the step 2
Size has no effect on write operation sequential of the CPU (10) to NANDFLASH (30).
4. the method that raising system according to claim 3 starts speed, it is characterised in that：CPU (10) in the step 2
Write the frequency of NANDFLASH (30) can reach NAND FLASH controller in NANDFLASH (30)/CPU (10) it is supported on
Limit frequency.
5. the method that raising system according to claim 4 starts speed, it is characterised in that：It must be in the step 3
Reading enable signal effective pulsewidth increase 2*T2 times that NANDFLASH (30) is exported in CPU (10), to meet CPU (10) readings
NANDFLASH (30) timing requirements.
6. the method that the raising system according to claim 2-5 any one starts speed, it is characterised in that：It is described low to prolong
When level translator (20) be low delay two-way level converting device, delay be less than or equal to 4.5ns.
7. the method that raising system according to claim 6 starts speed, it is characterised in that：The low delay level conversion
Device (20) uses TXB0304RUTR chips.
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| CN201711472887.4A CN108108564B (en) | 2017-12-29 | 2017-12-29 | Device and method for improving system starting speed |
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| CN201711472887.4A CN108108564B (en) | 2017-12-29 | 2017-12-29 | Device and method for improving system starting speed |
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| CN108108564B CN108108564B (en) | 2021-06-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110399319A (en) * | 2019-07-25 | 2019-11-01 | 尧云科技(西安)有限公司 | A kind of NAND Flash PHY |
| CN113626352A (en) * | 2021-07-01 | 2021-11-09 | 珠海全志科技股份有限公司 | Reading calibration method of memory controller, computer device and readable storage medium |
| CN113626352B (en) * | 2021-07-01 | 2024-04-30 | 珠海全志科技股份有限公司 | Memory controller reading calibration method, computer device and readable storage medium |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1100089A1 (en) * | 1999-11-09 | 2001-05-16 | Fujitsu Limited | Semiconductor memory device, and method of controlling the same |
| CN2444345Y (en) * | 2000-10-17 | 2001-08-22 | 东方通信股份有限公司 | Anti-theft device with radio monitoring |
| CN1473725A (en) * | 2003-07-23 | 2004-02-11 | 长春一汽启明信息技术有限公司 | Vehicle running recorder |
| CN101701869A (en) * | 2009-12-04 | 2010-05-05 | 北京工业大学 | Portable transmission noise meter for controlling engaging quality of bevel gear |
| CN201674552U (en) * | 2009-11-20 | 2010-12-15 | 北京五岳鑫信息技术股份有限公司 | Multimedia voice communication apparatus |
| CN102122271A (en) * | 2011-03-01 | 2011-07-13 | 株洲南车时代电气股份有限公司 | NAND flash memory controller and control method thereof |
| US20120020146A1 (en) * | 2010-07-23 | 2012-01-26 | Jonghoon Jung | Static Random Access Memory Device Including Negative Voltage Level Shifter |
| US20150143037A1 (en) * | 2011-04-06 | 2015-05-21 | P4tents1, LLC | System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class |
| CN105159200A (en) * | 2015-09-21 | 2015-12-16 | 郑州精益达汽车零部件有限公司 | Overall vehicle controller based on function safety |
| CN205563259U (en) * | 2016-04-28 | 2016-09-07 | 扬州宏诚智能科技有限公司 | Be applied to servo server of thing networking |
| CN106445859A (en) * | 2016-07-26 | 2017-02-22 | 安徽皖通邮电股份有限公司 | Switching method and device of multiplexing of multiple processor debugging ports on single board |
-
2017
- 2017-12-29 CN CN201711472887.4A patent/CN108108564B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1100089A1 (en) * | 1999-11-09 | 2001-05-16 | Fujitsu Limited | Semiconductor memory device, and method of controlling the same |
| CN2444345Y (en) * | 2000-10-17 | 2001-08-22 | 东方通信股份有限公司 | Anti-theft device with radio monitoring |
| CN1473725A (en) * | 2003-07-23 | 2004-02-11 | 长春一汽启明信息技术有限公司 | Vehicle running recorder |
| CN201674552U (en) * | 2009-11-20 | 2010-12-15 | 北京五岳鑫信息技术股份有限公司 | Multimedia voice communication apparatus |
| CN101701869A (en) * | 2009-12-04 | 2010-05-05 | 北京工业大学 | Portable transmission noise meter for controlling engaging quality of bevel gear |
| US20120020146A1 (en) * | 2010-07-23 | 2012-01-26 | Jonghoon Jung | Static Random Access Memory Device Including Negative Voltage Level Shifter |
| CN102122271A (en) * | 2011-03-01 | 2011-07-13 | 株洲南车时代电气股份有限公司 | NAND flash memory controller and control method thereof |
| US20150143037A1 (en) * | 2011-04-06 | 2015-05-21 | P4tents1, LLC | System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class |
| CN105159200A (en) * | 2015-09-21 | 2015-12-16 | 郑州精益达汽车零部件有限公司 | Overall vehicle controller based on function safety |
| CN205563259U (en) * | 2016-04-28 | 2016-09-07 | 扬州宏诚智能科技有限公司 | Be applied to servo server of thing networking |
| CN106445859A (en) * | 2016-07-26 | 2017-02-22 | 安徽皖通邮电股份有限公司 | Switching method and device of multiplexing of multiple processor debugging ports on single board |
Non-Patent Citations (4)
| Title |
|---|
| CHANIK PARK等: ""Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems"", 《PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN》 * |
| NOBUAKI OTSUKA等: ""Circuit Techniques for 1.5-V Power Supply Flash Memory"", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
| 庄文斌等: ""基于C51和FLASH存储器卡的无纸记录仪"", 《单片机与嵌入式系统应用》 * |
| 魏志静: ""基于 Android 的无线便携式现场招聘会信息采集终端的设计与实现"", 《电子技术与软件工程》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110399319A (en) * | 2019-07-25 | 2019-11-01 | 尧云科技(西安)有限公司 | A kind of NAND Flash PHY |
| CN113626352A (en) * | 2021-07-01 | 2021-11-09 | 珠海全志科技股份有限公司 | Reading calibration method of memory controller, computer device and readable storage medium |
| CN113626352B (en) * | 2021-07-01 | 2024-04-30 | 珠海全志科技股份有限公司 | Memory controller reading calibration method, computer device and readable storage medium |
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