CN202331441U

CN202331441U - FPGA-based expanded serial port

Info

Publication number: CN202331441U
Application number: CN2011204571155U
Authority: CN
Inventors: 王泽宽; 陈果
Original assignee: CHENGDU COVE TECHNOLOGY Co Ltd
Current assignee: Chengdu for Polytron Technologies Inc
Priority date: 2011-11-17
Filing date: 2011-11-17
Publication date: 2012-07-11
Anticipated expiration: 2021-11-17

Abstract

The utility model discloses an FPGA (Field Programmable Gate Array)-based expanded serial port. A reset signal port rst, a read-write signal port wr, an enable signal port enable, a fifo clock signal port fifo_clk, a fifo reset signal port fifo_rst and a 3-bit address port add of an RAM are respectively connected with an FPGA in a matched manner respectively; a bidirectional 8-bit data port data is connected between the register RAM and the FPGA; 8 interruption ports int provided for transmission of the register by the FPGA are connected with the register RAM in a matched manner; and the FPGA is connected with 8 full-duplex serial signal ports txd and rxd and a clock signal port clk. The FPGA-based expanded serial port replaces a traditional parallel port to serial port conversion chip, the parallel port mode can be user-defined, and a host with a corresponding parallel port mode is not required to be selected.

Description

A kind of expansion serial ports based on FPGA

Technical field

The utility model relates to the interface of the communications field, specifically is meant a kind of expansion serial ports based on FPGA.

Background technology

FPGA has adopted the such notion of logical cell array LCA (Logic Cell Array), and inside comprises configurable logic blocks CLB (Configurable Logic Block), output load module IOB (Input Output Block) and three parts of interconnector (Interconnect).Field programmable gate array (FPGA) is a programming device.With traditional logic circuit and gate array (like PAL; GAL and CPLD device) compare; FPGA has various structure; FPGA utilizes small-sized look-up table, and (16 * 1RAM) realize combinational logic, and each look-up table is connected to the input end of a d type flip flop, and trigger drives other logical circuits again or drives I/O; Constituted the basic logic unit module that not only can realize combination logic function but also can realize the sequential logic function thus, these intermodules utilize metal connecting line to connect mutually or are connected to the I/O module.The logic of FPGA realizes through loading programming data to inner static storage cell; Being stored in value in the memory cell has determined between logic function and each module of logical block or the connecting mode between module and I/O; And final decision the FPGA function that can realize, FPGA allows unlimited programming.RAM (RAS) RAM-random access memory random access memory, the content of storage unit can arbitrarily take out or deposit in as required, and the storer of the location independent of the speed of access and storage unit.Sort memory will be lost its memory contents when outage, so be mainly used in the program of storage short time use.In the industries such as industry, electronics, electrical equipment, serial communication is a kind of communication mode that is widely used in modern times.But it is not abundant that general main frame carries serial ports; Maximum as single-chip microcomputer have a two-way serial ports, and the RAM chip generally also has only four road serial ports, many times need insert the multichannel slave through serial ports; At this moment just need expand serial ports through other modes; There is the parallel port of specialty to change serial port chip, but general parallel port communication mode underaction, the serial ports way is abundant inadequately.

The utility model content

The purpose of the utility model is to provide a kind of expansion serial ports based on FPGA, utilizes on-site programmable gate array FPGA and buffer RAM to solve main frame and carries the not abundant problem of serial ports, for main frame provides more available serial ports.

The purpose of the utility model realizes through following technical proposals:

A kind of expansion serial ports based on FPGA; Comprise on-site programmable gate array FPGA; Also comprise buffer RAM; The reset signal port rst of RAM, read-write port wr, enable signal port enable, fifo clock signal port fifo_clk, fifo reset signal port fifo_rst, 3 bit address port add are connected with the on-site programmable gate array FPGA coupling respectively; Two-way 8 bit data mouth data are connected between buffer RAM and the on-site programmable gate array FPGA; On-site programmable gate array FPGA is connected with 8 tunnel full duplex rs 232 serial interface signal port txd and rxd at the scene for 8 interruptive port int that buffer RAM transmission provides are connected with buffer RAM coupling on the programmable gate array FPGA, be connected with clock signal port clk at the scene on the programmable gate array FPGA.

The clock signal frequency of the clock signal port clk input that connects on the programmable gate array FPGA at the scene is 10MHz.

Principle of work: the reception of serial ports and send by the inner asynchronous fifo of FPGA buffer memory is provided respectively, can accomplish the full duplex transmitting-receiving like this, for example, when receiving serial ports 0 when data are arranged; FPGA deposits data and receives among the fifo, and the interruption int0 of serial ports 0 is put 1, tells RAM serial ports 0 to receive data, can read; At this moment RAM puts 0 with the address, selects serial ports 0, and enable puts 1, and wr puts 1; The expression read data, fifo_clk provides the clock that receives fifo, and data have read the data that receive among the fifo by the data parallel read-out; Int0 puts 0, as RAM during to serial ports 0 write data, only needs the address is put 0, selects serial ports 0; Enable puts 1, and wr puts 0, the expression write data, and fifo_clk provides the clock that sends fifo; Data are written in parallel to by data and send fifo, and FPGA detects and sends when among the fifo data being arranged, and data are sent by setting the baud rate serial by txd0.

The utility model compared with prior art has the following advantages:

A kind of expansion serial ports based on FPGA of 1 the utility model has replaced traditional parallel port to change serial port chip, and the parallel port mode can be self-defined, need not select the main frame of corresponding parallel port mode;

A kind of expansion serial ports of 2 the utility model based on FPGA, the serial ports of expansion is horn of plenty more, needs to expand how many road serial ports and just can expand how many roads, and mode is flexible;

A kind of expansion serial ports based on FPGA of 3 the utility model adopts the FPGA design, and code cutting property and transplantability are strong, and range of application is wider.

Description of drawings

Fig. 1 is the utility model circuit diagram.

Embodiment

Below in conjunction with embodiment the utility model is done further to specify, but the embodiment of the utility model is not limited thereto.

Embodiment

As shown in Figure 1; A kind of expansion serial ports of the utility model based on FPGA; Comprise on-site programmable gate array FPGA; Also comprise buffer RAM; The reset signal port rst of RAM, read-write port wr, enable signal port enable, fifo clock signal port fifo_clk, fifo reset signal port fifo_rst, 3 bit address port add are connected with the on-site programmable gate array FPGA coupling respectively; Two-way 8 bit data mouth data are connected between buffer RAM and the on-site programmable gate array FPGA, and on-site programmable gate array FPGA is connected with 8 tunnel full duplex rs 232 serial interface signal port txd and rxd at the scene for 8 interruptive port int that buffer RAM transmission provides are connected with buffer RAM coupling on the programmable gate array FPGA; Be connected with clock signal port clk at the scene on the programmable gate array FPGA, the frequency of clock signal is 10MHz.

As stated, just can realize the utility model well.

Claims

1. expansion serial ports based on FPGA; Comprise on-site programmable gate array FPGA; It is characterized in that: also comprise buffer RAM; The reset signal port rst of RAM, read-write port wr, enable signal port enable, fifo clock signal port fifo_clk, fifo reset signal port fifo_rst, 3 bit address port add are connected with the on-site programmable gate array FPGA coupling respectively; Two-way 8 bit data mouth data are connected between buffer RAM and the on-site programmable gate array FPGA; On-site programmable gate array FPGA is connected with 8 tunnel full duplex rs 232 serial interface signal port txd and rxd at the scene for 8 interruptive port int that buffer RAM transmission provides are connected with buffer RAM coupling on the programmable gate array FPGA, be connected with clock signal port clk at the scene on the programmable gate array FPGA.

2. a kind of expansion serial ports based on FPGA according to claim 1 is characterized in that: the clock signal frequency of the clock signal port clk input that connects on the programmable gate array FPGA at the scene is 10MHz.