CN104461967A - Parallel data interface supporting synchronous and asynchronous transmission modes - Google Patents
Parallel data interface supporting synchronous and asynchronous transmission modes Download PDFInfo
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- CN104461967A CN104461967A CN201410826415.4A CN201410826415A CN104461967A CN 104461967 A CN104461967 A CN 104461967A CN 201410826415 A CN201410826415 A CN 201410826415A CN 104461967 A CN104461967 A CN 104461967A
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- asynchronous
- parallel data
- write
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
Abstract
The invention discloses a parallel data interface supporting synchronous and asynchronous transmission modes. The parallel data interface is in communication with a processor through an AHB. The parallel data interface comprises a transmission module, a parameter configuration module, an asynchronous writing first-in first-out module, an asynchronous reading first-in first-out module, a flash memory control module and an asynchronous memory control module. The transmission module achieves direct communication between the parallel data interface and the AHB and transmits all commands to the parallel data interface and read-write data. The parameter configuration module configures all parameters of the parallel data interface. The asynchronous write first-in first-out module buffers all writing commands and writing data transmitted from the AHB. The asynchronous read first-in first-out module buffers data read from an external storage device. The flash memory control module reads the commands from the AHB from the asynchronous write first-in first-out module, so that conversion from the commands from the AHB to flash memory port signals of the processor is achieved. The asynchronous memory control module reads the commands from the AHB from the asynchronous write first-in first-out module, so that conversion from the commands from the AHB to the memory port signals of the processor is achieved.
Description
Technical field
The present invention relates to a kind of parallel data grabbing card being applied to digital signal processor, belong to digital signal processor techniques field, particularly relate to a kind of parallel data grabbing card supporting synchronous and asynchronous transmission mode.
Background technology
Parallel data grabbing card is mainly used between DSP kernel and outside flash or sram carries out data communication.Its Main Function has: 1 for DSP boot. because DSP boot code is generally stored in above flash, system start at the beginning of, by parallel data grabbing card by boot code load come in, only hang flash outside this situation; 2 for the storage of the data of the centre of DSP calculating process, hangs flash or synchronous sram can outside this situation.
The speed of synchronous sram is very fast, and interface sequence is simple, but finite capacity, cost is higher simultaneously.NORflash speed is comparatively slow, and capacity is comparatively large, but the operation of read-write is complicated a little, generally all needs to add special character before and after writing data.The data length that NOR flash writes at every turn is subject to the restriction of flash granule interior buffer size.The NOR flash of the GL-S series that such as spansion company produces, inner buffer size is 512byte.The maximum data length of so each write flash is 512byte, and after buffer data being write flash, needs to wait for that data could be write flash by about 750 microseconds completely.At this moment the data write of second time flash could be initiated.This working method reduces the efficiency of DSP kernel.So need a kind of mechanism energy write-once considerably beyond the data volume of the inner buffer size restriction of flash.
Summary of the invention
In view of this, the present invention proposes a kind of parallel data grabbing card supporting synchronous and asynchronous transmission mode, it supports the synchronous and asynchronous transmission mode between ahb bus and processor.
The present invention realizes like this, a kind of parallel data grabbing card supporting synchronous and asynchronous transmission mode, it is communicated with processor by ahb bus, and this parallel data grabbing card comprises transport module, parameter configuration module, asynchronous write first in first out module, asynchronously reads first in first out module, flash memory control module, asynchronous memory control module; This transport module, for realizing the direct communication between this parallel data grabbing card and this ahb bus, is all completed by this module all orders of this parallel data grabbing card and the transmission that reads and writes data; This parameter configuration module realizes all parameter configuration of this parallel data grabbing card; This asynchronous write first in first out module is used for all write orders of coming from ahb bus of buffer memory and write data; This is asynchronous reads first in first out module and is used for cushioning from the data come of reading back during exterior storage; This flash memory control module reads the order from ahb bus from this asynchronous write first in first out module, realizes the conversion of ahb bus order to the flash memory port signal of this processor; Asynchronous memory control module reads from ahb bus order from this asynchronous write first in first out module, realizes the conversion of ahb bus order to the internal memory port signal of this processor.
As the further improvement of such scheme, this parameter configuration comprises the configuration of time sequence parameter, the selection of data bit width, the selection of type of device.
The present invention possesses following beneficial effect:
1 makes this parallel data grabbing card support different flash devices by register configuration;
2 these parallel data grabbing card support that DSP kernel initiates the dma data transmission of flash, and after namely configuring correlation parameter, DSP kernel can operate the write of large batch of data by initiation dma;
3 these parallel data grabbing card support that dma operation is cancelled in DSP kernel midway;
The function that the flash sector that any amount is once carried out in 4 these parallel data grabbing card supports wipes.
Accompanying drawing explanation
Fig. 1 is the frame diagram of the parallel data grabbing card of support synchronous and asynchronous transmission mode of the present invention;
Fig. 2 is 5 multiplexing figure of passage FDM of the present invention;
Fig. 3 is horizontal polarization of the present invention and vertical polarization schematic diagram;
Fig. 4 is polarization multiplexing schematic diagram of the present invention;
Fig. 5 is the expander graphs of the frame diagram of the parallel data grabbing card of support synchronous and asynchronous transmission mode of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Refer to Fig. 1, the parallel data grabbing card of support synchronous and asynchronous transmission mode of the present invention, be called for short parallel interface (Parallel port), parallel data grabbing card is communicated with processor by ahb bus.This parallel data grabbing card comprises transport module 1, parameter configuration module 2, asynchronous write first in first out module 3, asynchronously reads first in first out module 4, flash memory control module 5, asynchronous memory control module 6.
Transport module 1 is this module of parap_ahb_intf, realizes the direct communication between parallel data grabbing card and ahb bus, is all completed by this module all orders of parallel data grabbing card and the transmission that reads and writes data.
Parameter configuration module 2 is this module of parap_config, realizes all parameter configuration of parallel data grabbing card, comprises the configuration of time sequence parameter, the selection of data bit width, selection of type of device etc.
Asynchronous write first in first out module 3 is this module of async_wfifo, the fifo for asynchronous: first in first out (first in first out).This asynchronous fifo is used for all write order of coming from ahb bus of buffer memory and write data.
The asynchronous first in first out module 4 read for this module of async_rfifo, for this asynchronous fifo of asynchronous fifo. is used for cushioning from the data come of reading back during exterior storage.
Flash memory control module 5 is this module of flash controller, reads ahb bus order, realize the conversion of ahb bus order to flash port signal from async_wfifo.
Asynchronous memory control module 6 is this module of sync_sram controller, reads ahb bus order, realize the conversion of ahb bus order to sram port signal from async_wfifo.
Flash dma function describes in detail.In the market main flow NOR flash to write data mode all substantially similar, namely first several special characters (prefix) are sent to flash, and then the data address of write will be needed the buffer of corresponding write flash, and then send some special characters (suffix) confirmation this time write to flash.The write buffer command format of Spansion and Micron is as shown in table 1.
The write buffer command format of table 1 Spansion and Micron
Because the size of flash write buffer is limited, such as the buffer of spansion inside only has 512byte, namely the maximum amount of data of write-once is 512byte, if mass data (such as 1M bits) need be write, then need these data sectionals to write, also need to wait for a large amount of time between every section of write.Superimpose data segmentation gives DSP with the work of inserting special prefix suffix, then can increase the weight of the burden of DSP, reduces the efficiency of system.The function of Flash dma is exactly segmentation when large data transmission is moved on to parallel data grabbing card inside with the work of inserting prefix suffix complete.It is good that DSP only needs the parameter configuration of dma needs, as the content of concrete prefix suffix, and the length of prefix suffix, write the start address of data, total data length etc., as long as initiate a dma initiation command after having configured, remaining work is just complete to be completed by parallel data grabbing card.
Flash dma cancels function and describes in detail.If DSP will cancel this dma and transmits in dma transmitting procedure, then can initiate dma mandatum cassatorium, stop sending data by ahb bus to parallel data grabbing card simultaneously.After parallel data grabbing card receives dma mandatum cassatorium, then start dma and cancel handling procedure.Before Flashwrite buffer operates in and sends real data to flash, need flash to send several special character combination (prefix), inside prefix, contain the data amount check this time needing to send.If carry out stopping in process sending data to flash at write buffer, then flash device will rest on certain state and cannot get back to original state.If the flash device not being in original state in the later time sends order, unpredictable results can be produced.So parallel data grabbing card can produce data voluntarily, this remaining address of write buffer is write full F (original state due to NOR flash is full F, and in fact data are constant).Like this after current write buffer terminates, flash device will get back to original state, can initiate dma operation next time.
Flash continuous erase function describes in detail.NOR flash internal data before not write reads as must to be wiped free of full F. address is written into once after and could write for the second time.The GL-S series of Spansion.Erase command is as shown in table 2.
The erase command of table 2 Spansion series
Each sector erase order can only wipe a sector content, after distributing sector erase order, needs to wait until that the current erase of about 1100ms could initiate second time sector erase order after completing.This parallel data grabbing card can realize allowing after DSP configures related register, initiates related command, realizes the sector erase feature of continuous quantity and do not need to wait for that sector erase each time completes.Be exactly concrete implementation method configures initial No. sector that needs erasing, total need the number of the sector of erasing, then initiate erase command.The some sector of continuous print from initial No. sector will wipe by this parallel data grabbing card, can return an end signal after erasure completion to DSP.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. support the parallel data grabbing card of synchronous and asynchronous transmission mode for one kind, it is communicated with processor by ahb bus, it is characterized in that: this parallel data grabbing card comprises transport module, parameter configuration module, asynchronous write first in first out module, asynchronously reads first in first out module, flash memory control module, asynchronous memory control module; This transport module, for realizing the direct communication between this parallel data grabbing card and this ahb bus, is all completed by this module all orders of this parallel data grabbing card and the transmission that reads and writes data; This parameter configuration module realizes all parameter configuration of this parallel data grabbing card; This asynchronous write first in first out module is used for all write orders of coming from ahb bus of buffer memory and write data; This is asynchronous reads first in first out module and is used for cushioning from the data come of reading back during exterior storage; This flash memory control module reads the order from ahb bus from this asynchronous write first in first out module, realizes the conversion of ahb bus order to the flash memory port signal of this processor; This asynchronous memory control module reads from ahb bus order from this asynchronous write first in first out module, realizes the conversion of ahb bus order to the internal memory port signal of this processor.
2. the as claimed in claim 1 parallel data grabbing card supporting synchronous and asynchronous transmission mode, is characterized in that: this parameter configuration comprises the configuration of time sequence parameter, the selection of data bit width, the selection of type of device.
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| CN104461967B CN104461967B (en) | 2018-03-06 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105320637A (en) * | 2015-10-23 | 2016-02-10 | 西安中科晶像光电科技有限公司 | FLASH data read circuit |
| CN107959694A (en) * | 2016-10-14 | 2018-04-24 | 中兴通讯股份有限公司 | The method and apparatus of data synchronization caching |
| CN111274171A (en) * | 2018-12-04 | 2020-06-12 | 珠海格力电器股份有限公司 | Data transmission device and method |
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| JP2009237790A (en) * | 2008-03-26 | 2009-10-15 | Yamaha Corp | Dma controller |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105320637A (en) * | 2015-10-23 | 2016-02-10 | 西安中科晶像光电科技有限公司 | FLASH data read circuit |
| CN107959694A (en) * | 2016-10-14 | 2018-04-24 | 中兴通讯股份有限公司 | The method and apparatus of data synchronization caching |
| CN107959694B (en) * | 2016-10-14 | 2021-04-06 | 中兴通讯股份有限公司 | Data synchronization caching method and device |
| CN111274171A (en) * | 2018-12-04 | 2020-06-12 | 珠海格力电器股份有限公司 | Data transmission device and method |
| CN111274171B (en) * | 2018-12-04 | 2022-02-11 | 珠海格力电器股份有限公司 | Data transmission device and method |
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| CN104461967B (en) | 2018-03-06 |
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