CN112925641B - Satellite power supply lower computer system with 1553B interface chip replacing data storage - Google Patents
Satellite power supply lower computer system with 1553B interface chip replacing data storage Download PDFInfo
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- CN112925641B CN112925641B CN202110194519.8A CN202110194519A CN112925641B CN 112925641 B CN112925641 B CN 112925641B CN 202110194519 A CN202110194519 A CN 202110194519A CN 112925641 B CN112925641 B CN 112925641B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0608—Saving storage space on storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
Abstract
A1553B interface chip replaces a satellite power supply lower computer system of a data memory and comprises a CPU minimum system module, a communication module, a telemetering acquisition module and an instruction execution module; the CPU minimum system module comprises a CPU and a peripheral circuit, wherein the CPU is used for executing a stored program, sending generated data to the communication module and reading required data from the communication module; the communication module comprises a 1553B interface chip and a peripheral circuit, the 1553B interface chip completes 1553B communication with the integrated electronic subsystem and simultaneously stores data sent by the CPU minimum system module; the telemetering acquisition module acquires various telemetering measurements and converts the telemetering measurements into digital quantity; the instruction execution module performs level instruction control on the power controller control mechanism through the latch and performs OC instruction control on the power controller control mechanism through the decoder and the OC instruction chip. The invention removes the data memory, and uses the memory space of 1553B interface chip to access the data cache; the resource waste is avoided, the cost is saved, and the reliability is improved.
Description
Technical Field
The invention belongs to the field of satellite lower computers, and relates to a satellite power supply lower computer system with a 1553B interface chip replacing a data memory.
Background
In the application process of the lower computer of the satellite power supply controller, when the 1553B interface chip is used, the communication protocol cannot always use all 1553B memory spaces for data transmission. Meanwhile, the space utilization rate of the data memory by the CPU is often low.
Due to the limitation of information transmission quantity of a satellite measurement and control system, telemetering data transmitted by the power controller to the integrated electronics through 1553B one-time communication is generally in the order of tens of bytes to hundreds of bytes, the memory capacity of a commonly used 1553B interface chip is 8192 bytes, most of memory space is redundant space, and the part of memory cannot be used in the whole satellite process.
The data caching capacity required in the whole power controller lower computer program is about hundreds to two kilobytes, which depends on the program coding mode, the memory capacity of a data memory commonly used by the power controller lower computer system is 8192 bytes, and most of the memory space is not used.
The 1553B interface chip and the data storage are aerospace-level chips with the smallest available memory space in the same type, and a small-capacity memory chip cannot be replaced, so that the memory space waste is caused to a certain extent on the premise of meeting the memory space derating.
Disclosure of Invention
The technical problem solved by the invention is as follows: the satellite power supply lower computer system overcomes the defects of the prior art and provides a 1553B interface chip for replacing a data memory.
The technical scheme of the invention is as follows:
A1553B interface chip replaces a satellite power supply lower computer system of a data memory and comprises a CPU minimum system module, a communication module, a telemetering acquisition module and an instruction execution module;
CPU minimum system module: the CPU is used for executing a stored program, sending data generated in the execution process to the communication module, and reading data required by the subsequent execution of the program from the communication module; acquiring digital quantity data converted by the telemetering acquisition module, and sending the data to the communication module; carrying out communication protocol analysis and decoding on the ground instruction transmitted by the communication module to obtain data and a control signal, and sending the data and the control signal to the instruction execution module;
a communication module: the system comprises a 1553B interface chip and a peripheral circuit thereof, and is used for receiving a ground instruction forwarded by an on-satellite integrated electronic subsystem and transmitting the ground instruction to a CPU minimum system module; simultaneously storing data sent by the minimum system module of the CPU;
a telemetry acquisition module: various remote measurements in the power controller are acquired through a multi-channel gate and an analog-to-digital converter, converted into digital quantity and sent to a CPU minimum system module;
the instruction execution module: the power controller control mechanism is subjected to level instruction control through the latch, and is subjected to OC instruction control through the decoder and the OC instruction chip.
A subaddress which is not used in the 1553B communication protocol is selected as a memory space of the 1553B interface chip, and the memory space is ensured not to be accessed in the normal communication process
The communication module stores the data sent by the CPU minimum system module as follows:
step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;
and 2, step: the CPU selects a 1553B interface chip through bus writing operation, and writes low-byte data of data to be written into the memory into an address;
and step 3: and (3) shifting the address in the step (2) by 1 binary bit to the left, selecting a 1553B interface chip through bus writing operation, and writing the high byte data of the data to be written into the memory into the address after the left shift.
The way for the CPU minimum system module to read the data required by the subsequent execution of the program from the communication module is as follows:
step 1: selecting the memory/register pin of the 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;
step 2: the CPU selects a 1553B interface chip through bus reading operation, reads low-byte data of data to be read out of the memory of the 1553B interface chip into the CPU from a corresponding address, discards the data and regards the data as a sub-reading operation;
and step 3: the CPU selects the 1553B interface chip through bus reading operation, reads low byte data of data stored in the 1553B interface chip to be read out into the CPU from a corresponding address again, and stores the data;
and 4, step 4: and (3) leftwards shifting the address in the step (3) by 1 binary bit, selecting a 1553B interface chip through bus reading operation, reading high-byte data of the data to be read out of the memory of the 1553B interface chip into a CPU from a corresponding address, and storing the data.
The program stored in the CPU comprises an application layer, a system layer and an interface layer; wherein:
the application layer completes each specific function of the on-satellite software;
the system layer completes CPU initialization, OC instruction chip initialization, level instruction chip initialization, 1553B interface chip interrupt control, timing interrupt control, on-track code injection verification and injection;
the interface layer completes the input and output management of all software external interface data, and the management comprises interface initialization of a 1553B interface chip, data input and output management of the 1553B interface chip, reset drive management of the 1553B interface chip, data cache storage of the 1553B interface chip, drive management of an analog-to-digital converter, OC instruction drive management and level instruction drive management.
In the instruction execution module, the latch converts data in the data bus into a level instruction and outputs the level instruction to the power controller control mechanism.
In the instruction execution module, the decoder converts the control signal into a channel chip selection for selecting the OC instruction chip; and the OC instruction chip converts the channel chip selection into an OC instruction of a corresponding output port and outputs the OC instruction to the power controller control mechanism.
The capacity of the 1553B interface chip can simultaneously meet all data caching requirements of an appointed program and 1553B data communication caching requirements.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the unused memory space of the 1553B interface chip is utilized, so that the data memory chip is saved, and the cost is saved; 1553B interface chip resources are fully utilized, and resource waste is avoided; meanwhile, the use of components is reduced, and the reliability of the lower computer module of the satellite power supply controller is improved.
Drawings
FIG. 1 is a schematic diagram of a lower computer system of a power supply controller of the present invention;
FIG. 2 is a diagram of the software platform architecture of the CPU minimal system of the present invention;
FIG. 3 is a flow chart of the data caching function write of the present invention;
FIG. 4 is a flow chart of the data caching function read-out according to the present invention.
Detailed Description
The invention is further elucidated with reference to the drawing.
According to the invention, a data storage is removed from a lower computer system of the power controller, and the memory space of a 1553B interface chip is used for accessing the data cache; under the condition of certain quality grade, the number of components is reduced, and the reliability of the module is improved.
The specific design is as follows.
As shown in fig. 1, the invention provides a system for replacing a data memory by a 1553B interface chip based on a satellite power controller. The system comprises a CPU minimum system module, a communication module, a telemetry acquisition module and an instruction execution module. The minimum system module of the CPU is a CPU and a peripheral circuit, and completes the execution of programs and the realization of functions; the communication module is mainly used for executing the stored program, sending data generated in the executing process to the communication module, and reading data required by the subsequent execution of the program from the communication module; acquiring digital quantity data converted by the telemetering acquisition module, and sending the data to the communication module; and analyzing and decoding the communication protocol of the ground instruction transmitted by the communication module to obtain a level instruction and an OC instruction, and sending the level instruction and the OC instruction to the instruction execution module.
The communication module completes 1553B communication with the integrated electronic subsystem (or the measurement and control subsystem or the data transmission subsystem). The system comprises a CPU minimum system module, a ground command receiving module, a ground command transmitting module and a ground command transmitting module, wherein the ground command is used for receiving a ground command transmitted by an on-satellite integrated electronic subsystem and transmitting the ground command to the CPU minimum system module; and simultaneously storing the data sent by the minimum system module of the CPU.
The telemetering acquisition module finishes acquisition of telemetering data and converts the telemetering data into digital quantity through a multi-channel gate, a telemetering voltage filter circuit and an analog-to-digital (AD) converter, and the multi-channel gate selects one of a plurality of channels of input analog quantity to output through a control signal; the voltage filter circuit filters high-frequency noise of the telemetering signal and improves driving capability. The instruction execution module executes the level instruction through the latch, and executes the OC instruction through the decoder and the OC driving chip (the instruction execution module can also execute the OC instruction through the latch and the triode). Wherein the CPU minimum system module does not contain a data memory.
The CPU minimum system module comprises a CPU, a crystal oscillator, a bus buffer, an address latch, a program memory, a hardware watchdog, a chip selection decoder and no data memory; CPU executes corresponding program function, and does not contain large capacity on-chip data memory; the crystal oscillator generates a square wave with fixed frequency to provide a clock input signal for the CPU; the bus buffer enhances the driving current capability of the CPU to a data bus or an address bus; the address latch latches a data bus of the data low byte and enhances the driving current capability from the CPU to the address bus; the program memory stores the burned binary program codes and the CPU reads the internal program; the hardware watchdog resets the CPU when the CPU is affected by single event upset and the like to cause the program to run away; the chip selection decoder converts the address signal in the address bus into a chip selection signal to carry out the gating of the device.
The CPU communicates with the bus by writing or reading corresponding data of the 1553B interface chip; the capacity of the 1553B interface chip can meet all data caching requirements of appointed program functions and 1553B data communication caching requirements at the same time.
And the instruction execution unit comprises a latch, a decoder and an OC instruction chip. The latch converts the data in the data bus into level instructions to be output; the decoder converts the control signal into channel chip selection for selecting the OC instruction chip; the OC instruction chip converts the channel chip selection into an OC instruction of a corresponding output port.
Fig. 2 is a block diagram showing a software implementation stored in the CPU of the present invention. The software platform stored in the CPU of the invention comprises an application layer, a system layer and an interface layer. Wherein:
the application layer mainly completes various specific functions of satellite software, such as receiving, analyzing and executing of remote control instructions of comprehensive electronic forwarding, framing and packaging of telemetering acquired data, balancing management of the storage battery, ampere-hour meter estimation of the storage battery, overcharge/overdischarge protection of the storage battery and the like.
The system layer comprises control on a minimum system layer and mainly completes CPU initialization, OC instruction chip initialization, level instruction initialization, 1553B interrupt control, timing interrupt control, on-track code injection verification and injection and the like.
The interface layer comprises all software external interface data input and output management and mainly completes interface initialization of a 1553B interface chip, data input and output management of the 1553B interface chip, reset drive management of the 1553B interface chip, data cache storage of the 1553B interface chip, drive management of an analog-to-digital converter, OC instruction drive management, level instruction drive management and the like.
As shown in fig. 3, the data caching function performs a data storage process, and the CPU puts the data to be stored into the 1553B interface chip through the following steps.
Step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin through IO port operation;
and 2, step: selecting a 1553B interface chip through bus writing operation, and writing low-byte data of data to be written into the memory into an address;
and step 3: and (3) leftwards shifting the address in the step (2) by 1 binary bit, selecting a 1553B interface chip through bus writing operation, and writing high byte data of the data to be written into the memory into the address after left shifting.
As shown in fig. 4, a flow of data reading by the data cache storage function exists, because there is a sub-read operation on the read sequence of the 1553B interface chip, that is, an address needs to be written into the interface chip when the first chip selection is enabled, the same address needs to be written and data needs to be read when the second chip selection is enabled, and the CPU reads the data cache to be stored from the 1553B interface chip to the CPU by the following steps.
Step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;
step 2: selecting a 1553B interface chip through bus reading operation, reading low-byte data of data to be read out of a 1553B memory into a CPU (Central processing Unit) from a corresponding address, discarding the data, and regarding the data as a sub-reading operation;
and step 3: selecting a 1553B interface chip through bus reading operation, reading low-byte data of data to be read out of a 1553B memory into a CPU (central processing unit) from a corresponding address again, and storing the data;
and 4, step 4: and (3) leftwards shifting the address in the step (2) or the step (3) by 1 binary bit, selecting a 1553B interface chip through bus reading operation, reading high-byte data of the data to be read out of the 1553B memory into a CPU from a corresponding address, and storing the data.
In addition, before program coding, a 1553B memory space corresponding to each variable needs to be allocated in advance, and a sub-address which is not used in a communication protocol is selected to ensure that the memory space is not accessed in a normal communication process; the read-write drive function is divided into two versions called by a main program and an interrupt program respectively, otherwise if the read-write drive function is interrupted when executed in the main program, local variables in the read-write drive function are rewritten, so that read-write data after the interruption is skipped are incorrect; and configuring a fixed sub-address for a 1553B memory space corresponding to the variable, and configuring the sub-address into illegal transmission, reception and broadcasting, thereby avoiding misoperation of the sub-address by comprehensive electrons.
According to the invention, a 1553B interface chip is used for replacing a data memory, and under the condition that 1553B bus communication is used in a lower computer system of a satellite power supply controller, a lower computer CPU minimum system does not comprise the data memory; when the program reads and writes the data cache, the corresponding variables are stored in the memory of the 1553B interface chip, and the driver is programmed to read and write the data in the memory of the 1553B interface chip.
In the hardware composition of the invention, a 1553B interface chip is used for replacing a data memory, and when software codes are realized, the data is cached and stored in the 1553B interface chip.
According to the invention, the unused memory space of the 1553B interface chip is utilized, the cost is saved, and the reliability of the lower computer module of the satellite power supply controller is improved. Its advantage and beneficial effect are:
1) The lower computer system of the satellite power supply controller saves a data memory chip and saves cost;
2) 1553B interface chip resources are fully utilized, and resource waste is avoided;
3) The use of components is reduced, and the reliability of model products is improved.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (7)
1. A1553B interface chip replaces a satellite power supply lower computer system of a data storage, which is characterized in that: the system comprises a CPU minimum system module, a communication module, a telemetering acquisition module and an instruction execution module;
CPU minimum system module: the CPU is used for executing a stored program, sending data generated in the execution process to the communication module, and reading data required by the subsequent execution of the program from the communication module; acquiring digital quantity data converted by the telemetering acquisition module, and sending the data to the communication module; carrying out communication protocol analysis and decoding on the ground instruction transmitted by the communication module to obtain data and a control signal, and sending the data and the control signal to the instruction execution module;
a communication module: the system comprises a 1553B interface chip and a peripheral circuit thereof, and is used for receiving a ground instruction forwarded by an on-satellite integrated electronic subsystem and transmitting the ground instruction to a CPU minimum system module; simultaneously storing data sent by the minimum system module of the CPU;
a telemetry acquisition module: various remote measurements in the power controller are acquired through a multi-channel gate and an analog-to-digital converter, converted into digital quantity and sent to a CPU minimum system module;
the instruction execution module: according to the data and the control signal, level instruction control is carried out on the power controller control mechanism through the latch, and OC instruction control is carried out on the power controller control mechanism through the decoder and the OC instruction chip;
and selecting a sub-address which is not used in the 1553B communication protocol as a memory space of a 1553B interface chip to ensure that the memory space is not accessed in a normal communication process.
2. The satellite power supply lower computer system with the 1553B interface chip replacing the data storage device as claimed in claim 1, wherein the communication module stores the data sent by the CPU minimum system module in the following manner:
step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;
and 2, step: the CPU selects a 1553B interface chip through bus writing operation, and writes low-byte data of data to be written into the memory into an address;
and step 3: and (3) shifting the address in the step (2) by 1 binary bit to the left, selecting a 1553B interface chip through bus writing operation, and writing the high byte data of the data to be written into the memory into the address after the left shift.
3. The satellite power supply lower computer system with a 1553B interface chip replacing a data storage device as claimed in claim 1, wherein the way that the CPU minimum system module reads data required for subsequent execution of a program from the communication module is as follows:
step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;
and 2, step: the CPU selects the 1553B interface chip through bus reading operation, reads low-byte data of data stored in the 1553B interface chip to be read out into the CPU from a corresponding address, discards the data and regards the data as sub-reading operation;
and step 3: the CPU selects the 1553B interface chip through bus reading operation, reads low-byte data of the data stored in the 1553B interface chip to be read out into the CPU from a corresponding address again, and stores the data;
and 4, step 4: and (3) leftwards shifting the address in the step (3) by 1 binary bit, selecting a 1553B interface chip through bus reading operation, reading high-byte data of the data to be read out of the memory of the 1553B interface chip into a CPU from a corresponding address, and storing the data.
4. The satellite power supply lower computer system with a 1553B interface chip replacing a data storage device according to claim 1, wherein the program stored in the CPU comprises an application layer, a system layer and an interface layer; wherein:
the application layer completes each specific function of the on-satellite software;
the system layer completes CPU initialization, OC instruction chip initialization, level instruction chip initialization, 1553B interface chip interrupt control, timing interrupt control, on-track code injection verification and injection;
the interface layer completes the input and output management of all software external interface data, and the management comprises interface initialization of a 1553B interface chip, data input and output management of the 1553B interface chip, reset drive management of the 1553B interface chip, data cache storage of the 1553B interface chip, drive management of an analog-to-digital converter, OC instruction drive management and level instruction drive management.
5. The satellite power supply lower computer system with the 1553B interface chip replacing the data storage device as claimed in claim 1, wherein in the instruction execution module, the latch converts data in a data bus into a level instruction and outputs the level instruction to the power supply controller control mechanism.
6. The satellite power supply lower computer system with the 1553B interface chip replacing the data storage device as claimed in claim 1, wherein in the instruction execution module, the decoder converts the control signal into a channel chip selection for selecting the OC instruction chip; and the OC instruction chip converts the channel chip selection into an OC instruction of a corresponding output port and outputs the OC instruction to the power supply controller control mechanism.
7. The satellite power supply lower computer system with the 1553B interface chip replacing the data storage device as claimed in claim 1, wherein the capacity of the 1553B interface chip meets all data caching requirements of an appointed program and 1553B data communication caching requirements at the same time.
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| CN103944629A (en) * | 2014-04-28 | 2014-07-23 | 航天东方红卫星有限公司 | Satellite integrated electronic system |
| CN109542063A (en) * | 2018-11-21 | 2019-03-29 | 上海航天计算机技术研究所 | A kind of Complex interface control equipment and spaceborne Integrated Electronic System |
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| DE102004038591A1 (en) * | 2004-08-06 | 2006-02-23 | Robert Bosch Gmbh | Interface module |
| TWI298834B (en) * | 2006-02-14 | 2008-07-11 | Neotec Semiconductor Ltd | Battery management system |
| CN102495565B (en) * | 2011-11-25 | 2013-08-14 | 中国电子科技集团公司第三十八研究所 | Phased array radar antenna beam control device |
| CN104460427B (en) * | 2014-10-31 | 2017-01-25 | 上海卫星工程研究所 | Integrated electronic system for modular microsatellite platform |
| CN108988931B (en) * | 2018-06-26 | 2020-10-09 | 上海卫星工程研究所 | Satellite measurement and control coprocessor |
| CN109613865B (en) * | 2018-12-13 | 2021-09-03 | 上海航天计算机技术研究所 | Control device of satellite-borne power system |
| CN111679995B (en) * | 2020-06-19 | 2021-09-28 | 西安微电子技术研究所 | Embedded management execution unit of space computer based on 1553B bus |
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| CN101354829A (en) * | 2008-09-12 | 2009-01-28 | 航天东方红卫星有限公司 | Satellite telemetering data transmission method |
| CN103944629A (en) * | 2014-04-28 | 2014-07-23 | 航天东方红卫星有限公司 | Satellite integrated electronic system |
| CN109542063A (en) * | 2018-11-21 | 2019-03-29 | 上海航天计算机技术研究所 | A kind of Complex interface control equipment and spaceborne Integrated Electronic System |
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