CN115080471A

CN115080471A - Nand flash interface controller based on FPGA and read-write method

Info

Publication number: CN115080471A
Application number: CN202210762743.7A
Authority: CN
Inventors: 杨永进; 徐克兴; 王维
Original assignee: Dfine Technology Co Ltd
Current assignee: Dfine Technology Co Ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-09-20

Abstract

The invention discloses a nand flash interface controller based on an FPGA (field programmable gate array). A data cache module is connected with the FPGA through an off-chip bus, a time sequence control module is connected with the nand flash through the off-chip bus, the data cache module, a command control module and the time sequence control module are sequentially connected through an on-chip bus, a read-write counting module is respectively connected with the data cache module, the command control module and the time sequence control module, and the ECC module is connected with the command control module. The interface controller generates an address, data and a command which need to be sent to the nand flash in the FPGA according to the time sequence requirement of the interface of the nand flash chip, responds to the operation of an upper application program, and the data cache module designs two dual-port RAMs to perform ping-pong operation processing, thereby ensuring that the data is not lost in different clock domains, ensuring the integrity of data transmission and facilitating the read-write operation of the nand flash.

Description

Nand flash interface controller based on FPGA and read-write method

Technical Field

The invention relates to the field of electronic storage, in particular to a nand flash interface controller based on an FPGA and a read-write method.

Background

The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit. The FPGA has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and forms a typical integrated circuit in a semi-custom circuit from the viewpoint of a chip device, wherein the FPGA comprises a digital management module, an embedded unit, an output unit, an input unit and the like.

The FPGA adopts the concept of a logic cell array LCA, and comprises a configurable logic module CLB, an input-output module IOB and an internal connecting line. A Field Programmable Gate Array (FPGA) is a programmable device that has a different structure than traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices). The FPGA utilizes small lookup tables (16 × 1RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming. FPGA design is not simple chip research, and is mainly used for designing products in other industries by utilizing an FPGA mode.

The nand flash memory is one of flash memories, is a nonvolatile storage medium, is generally used for storing an operating system, an application program, user data and the like which are necessary for the running of an embedded system, and adopts a nonlinear macro-unit mode inside, thereby providing a cheap and effective solution for realizing a solid-state large-capacity memory. The nand structure can provide very high cell density, can achieve high storage density, has the advantages of large capacity, high rewriting speed and the like, is suitable for storage of a large amount of data, and is widely applied in the industry, for example, embedded products comprise a digital camera, an MP3 walkman memory card, a small-sized U disk and the like.

Usually the nand flash controller is located between the host and the nand flash device and controls the access to the device, and the characteristic of the nand flash is that the normal use must be equipped with corresponding management mechanisms, such as ECC, bad block management mechanism, read-write mechanism, etc. The operation of the nand flash memory chip can be completed only by a special register of the nand flash controller. Therefore, a bus operation cannot be performed for the nand flash. And the write operation of the nand flash also needs to be carried out in a block mode. A read operation on a nand flash can be read in bytes.

The nand flash has the characteristics of large capacity, low cost and long service life, and is widely used as a solution for data storage. However, most of the interface controllers on the nand flash in the market are developed based on a PC or an ARM processor as an architecture, and the problem of inconvenient operation exists.

Disclosure of Invention

In order to solve the technical problem, the invention provides the nand flash interface controller based on the FPGA, which can enable the operation of reading and writing the nand flash to be more convenient without the participation of a PC (personal computer) or an ARM (advanced RISC machine) processor.

The invention provides a nand flash interface controller based on FPGA, comprising:

the data cache module is used for caching data between the FPGA and the controller;

the command control module is used for receiving command data and performing corresponding operation;

the time sequence control module is matched with the command control module to generate a time sequence signal;

the read-write counting module is used for generating a read-write starting address and an end address;

the ECC module is used for data validation;

the data cache module is connected with the FPGA through an off-chip bus, the time sequence control module is connected with the nand flash through the off-chip bus, the data cache module, the command control module and the time sequence control module are sequentially connected through the on-chip bus, the read-write counting module is respectively connected with the data cache module, the command control module and the time sequence control module, and the ECC module is connected with the command control module.

Furthermore, the data cache module adopts a dual-port RAM formed by a first RAM and a second RAM to realize ping-pong operation, so that stable data communication across clock domains is ensured;

further, the commands executable by the command control module include block erase, page program, page read, read ID, read status;

the invention also provides a read-write method of the nand flash interface controller based on the FPGA, which comprises the following steps:

double-port RAM ping-pong reading and writing;

and (5) executing the nand flash operation command.

Further, ping-pong reading and writing of the dual-port RAM comprises the following steps:

the first RAM starts to store data;

the first RAM is full of data, the second RAM starts to store the data, and the first RAM starts to read the data and stores the data in a nand flash;

the data in the second RAM is fully stored, after the data in the first RAM is completely read, new data are stored, and the second RAM starts to read the data and stores the data in the nand flash;

the first RAM and the second RAM alternately store and read data until all data are stored in the nand flash.

Further, the nand flash operation command execution includes the following sequence:

executing a command sending period to indicate which type the current operation is;

sending a nand flash address needing to be operated;

and sending a data writing period.

Further, the operation types of nand flash include block erase, page program, and page read.

Further, the block erase operation includes the following timing:

the FPGA sends an instruction 60h, and then 4 address cycles are sent to specify the block address to be erased;

the FPGA sends an erasing confirmation instruction;

and after the erasing operation is executed, the FPGA judges whether the erasing is successful, and if the erasing is failed, the block is added into the bad block table.

Further, the page programming operation includes the following timing:

the FPGA sends a command 80h, then sends 6 address cycles, and specifies the written position;

the FPGA executes a data writing period, writes page data into a page register of nand flash, and takes a 10h command as a data ending mark;

and writing the page data into the internal storage array by the nand flash, and judging whether the page writing is finished by the FPGA.

Further, the page read operation includes the following timing:

the FPGA sends a 00h command, then sends 6 address cycles to tell the nand flash addressing position, and finishes with a 30h command;

after receiving a page reading command, the nand flash moves the addressed page data in the storage matrix to a page register;

the FPGA judges whether data movement is finished or not;

the FPGA executes a data reading period to read the data of the page from the DQ bus.

The invention has the advantages that the controller generates the address, the data and the command which need to be sent to the nand flash in the FPGA according to the time sequence requirement of the interface of the nand flash chip, responds to the operation of an upper application program, and the data cache module designs two double-port RAMs for ping-pong operation processing, thereby ensuring the integrity of data transmission and facilitating the read-write operation of the nand flash.

The foregoing description is only an overview of the technical solutions of the embodiments of the present invention, and the present invention can be implemented according to the content of the description in order to clearly understand the technical means of the embodiments of the present invention, and the content of the present invention will be further described in detail by the embodiments below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present invention more obvious.

Drawings

FIG. 1 is a structural diagram of a nand flash controller;

FIG. 2 is a schematic diagram of the dual port RAM operation of the data cache module;

FIG. 3 is a nand flash command control state machine diagram;

FIG. 4 is a block erase operation flow;

FIG. 5 is a page program operation flow;

FIG. 6 is a page read operation flow;

FIG. 7 is a timing diagram of command latch in SDR mode;

FIG. 8 is a timing diagram of address latching in SDR mode;

FIG. 9 is a timing diagram of data writing in SDR mode;

fig. 10 is a timing diagram for data reading in SDR mode.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, the nand flash interface controller of the present invention includes:

the ECC module is used for data validation;

The modules cooperate to implement the read/write function, and the data transmission and processing flow of each module will be described in detail below.

And the data cache module is responsible for finishing data caching between the FPGA and the controller, and adopts a double-port RAM design to ensure that data is not lost during communication between clock-crossing domains. As shown in fig. 2, two RAMs of the data cache module read data in turn to implement a ping-pong operation process, which can greatly improve the throughput of data and ensure that data is not lost. The ping-pong operation read-write process of the dual-port RAM comprises the following steps:

the first RAM starts to store data;

The command control module responds to a control command of an external module, is responsible for scheduling work of the whole module, is a central brain of the nand flash, and completes corresponding operation by analyzing the received control command (reset, ID reading, erasing, writing, reading and the like). The types of operation commands that the nand flash can complete include operations such as block erasing, ID reading, reading state, page programming, data page reading and the like, and command sending is completed under the coordination of the timing control module. The execution of a nand flash command requires three timings to complete. First, a command transmission cycle indicating what kind of operation is currently performed needs to be executed; secondly, transmitting a nand flash address to be operated, wherein the step usually needs 1-6 address cycles to be completed, and the specific number of the address cycles is shown in table 1; and finally, sending a data writing period, and if the command is a reading operation, omitting the step.

TABLE 1nand flash chip instruction set

Instruction description	Instruction	1	Number of address cycles	Instruction 2
					Reduction of position	FFh
Reading ID	90h
			1
Reading status	70h
		Page read operation	00h				6	30h
Page programming operation	80h					6			10h
		Block erase operation	60h	4			D0h

The command control module of the nand flash interface device of the invention is configured with a state machine for jumping each operation, as shown in fig. 3. After the nand flash is powered on, at least 100us of waiting is needed in the idle state, the R/B _ n signal of the nand flash is pulled high, and no instruction is sent in the state. Then, a reset state machine is entered, which needs to reset all logical unit blocks (LUNs), and the command is received by all logical unit blocks of the same CE _ n at the same time. After the reset is completed, the FPGA sends a read state instruction (70h) and waits until the state register SR [6] is set to 1, and at the moment, the nand flash can be operated by commands of erasing, reading, writing, reading ID and the like. And the Nand flash responds to the operation of an upper application program through the wait _ cmd state machine and jumps to a corresponding sub-state to act.

In the block erasing command, if the current block is erased, the block address generator adds 1, and the FPGA erases the next block until all blocks of the nand flash are erased.

Similarly, if the current page is completely written and read, adding 1 to the page address generator, and the FPGA performs page writing and reading operations on the next page until all the page pages of the nand flash are completely read and written.

The specific flow of each command jump of the state machine is as follows:

(1) reset (FFh)

The reset instruction can set the nand flash chip to be in a default state after being powered on, the FPGA can execute reset only by sending an instruction (FFh) to the nand flash, the nand flash can pull down the R/B _ n signal after receiving the reset instruction, the R/B _ n signal is set to be in a high level after tRST time, and the reset operation is indicated to be finished.

(2) Read ID (90h)

The read ID command is used to read the ID number of the chip. When a write read ID command (90h) is written to the command register, which causes the chip to enter the read ID mode, the chip will continue in this mode waiting for the next available command to execute.

(3) Read status (70h)

The FPGA can judge the equipment state by inquiring the state register and whether the erasing, reading and writing operations are successful or not. The read state time sequence comprises a command period and a data output period, the FPGA writes a 70h command into the nand flash to request for obtaining the state, and the nand flash outputs the value of the state register SR to the DQ bus after receiving the command.

(4) Page read (00h-30h) operation is shown in FIG. 6

The page read instruction (page read) is used for reading data of one page (16k +2048bytes) from the storage array, the FPGA sends a 00h command to the nand flash, then sends 6 address cycles to tell the nand flash the addressing position, then the nand flash finishes with the 30h command, the nand flash transfers the addressed page data in the storage array to the page register after receiving the page read command, the FPGA can judge whether data transfer is completed or not by judging whether an R/B _ n signal is 1 or not, the FPGA executes a data read cycle after transfer is completed, and the data of the page is read from a DQ bus.

(5) Page program (80h-10h) operation is shown in FIG. 5

A page program operation (page program) is a process of writing page or partial page data to a page buffer and then programming the data into a flash memory array. The FPGA writes data of one page into a page register through a page programming instruction, and then writes the data into a memory array of nand flash. The FPGA sends a command 80h firstly, then sends 6 address cycles, specifies the writing position, executes a data writing cycle after tADL time, writes page data into a page register of nand flash, and takes a 10h command as a data ending mark. After data is written into the page register, the nand flash starts to execute the operation of writing the page data into the internal storage array, and the FPGA can judge whether the page writing is finished by judging whether the R/B _ n signal is 1 or not.

(6) Block erase (60h-D0h) operation is shown in FIG. 4

A Block Erase operation (Block Erase) is used to Erase a single Block (Block). The FPGA sends an erase setup command (60h) followed by 4 address cycles to specify the block address to be erased, and then sends an erase confirm command (d0h) to perform the block erase. The FPGA can judge whether the block erasure is finished by judging whether the R/B _ n signal is 1, and after the erasure operation is finished, the FPGA judges whether the erasure is successful by inquiring a status register (SR [0 ]). If the erasure fails, the block needs to be added into the bad block table for management.

The sequential state machine of the sequential control module needs to carry out command skip under the coordination of the command control state machine, when the command control state machine sends out an instruction, the sequential state machine skips to corresponding sequential logic to generate a control sequential diagram, and the main responding operations comprise address latching, command latching, input and output. The scheme adopts an SDR mode to design a time sequence interface, and the time sequence relation is shown in figure 7, figure 8, figure 9 and figure 10. SDR is a single data transfer mode that is characterized by a single operation (read or write) on the rising edge of a waveform during a memory clock cycle. The command latch timing diagram in SDR mode is shown in FIG. 7, where the command on the DQ bus is latched on the rising edge of the WE _ n signal when CLE is high and CE _ n is low. FIG. 8 is a timing diagram for address latching in SDR mode, as shown with the ALE high and CE _ n low, for latching addresses on the DQ bus on the rising edge of the WE _ n signal. Fig. 9 is a timing chart of data writing in the SDR mode, where data on the DQ bus is sampled at the rising edge of the WE _ n signal and input to the chip when both ALE and CLE are low and CE _ n is low. FIG. 10 is a timing diagram for data reading in SDR mode, where RE _ n should be high when R/B _ n is low, and the FPGA reads data from the chip on the rising edge of RE _ n when R/B _ n transitions to high.

The nand flash has the physical characteristics that errors with certain probability can occur in the data reading and writing process, so that a corresponding error detection and correction mechanism is needed, and an ECC error check code is used for detecting and correcting data errors. Common algorithms of the ECC of nand flash include hamming code and BCH, and the implementation of such algorithms can be software or hardware. Different systems adopt corresponding software or hardware according to own requirements.

The embodiment uses verilog language to develop the driver of nand flash. Verilog HDL, a language that describes the structure and behavior of digital system hardware in textual form, describes a circuit (system) from five levels, including a system level, an algorithm level, a register transfer level (i.e., RTL level), a gate level, and a switch level. Part of the code of the nand flash driver developed by using verilog language in the embodiment is as follows:

as shown in the code, after entering the wait for command operation state machine, the command (command) plus enable (op _ start _ pos) signal from the upper layer software triggers the state machine to enter the corresponding sub-state to respond, and the example code lists the response operations of reset, read ID, read state, bad block detection, block erasure, page write and page read.

As shown in the code, after entering the bad block detection state machine, the initial number of bad blocks is 0, when the block erasure is successful, the block is marked as a good block, and when the block erasure is failed, the block is marked as a bad block until all 1006 block detections of the LUN are completed.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A nand flash interface controller based on FPGA is characterized by comprising:

the ECC module is used for data validation;

2. The nand flash interface controller based on FPGA of claim 1, wherein the data cache module adopts a dual-port RAM formed by a first RAM and a second RAM to realize ping-pong operation, thereby ensuring stable data communication across clock domains.

3. The FPGA-based nand flash interface controller of claim 1, wherein the commands executable by said command control module comprise block erase, page program, page read, read ID, read status.

4. The method for reading and writing nand flash data of the nand flash interface controller based on the FPGA according to any one of claims 1 to 3, characterized by comprising the following steps:

double-port RAM ping-pong reading and writing;

and (5) executing the nand flash operation command.

5. The method for reading and writing nand flash data by the nand flash interface controller based on the FPGA as claimed in claim 4, wherein the ping-pong reading and writing of the dual-port RAM comprises the following steps:

the first RAM starts to store data;

6. The method for the nand flash interface controller to read and write the nand flash data based on the FPGA of claim 4, wherein the execution of the nand flash operation command comprises the following sequence:

executing a command sending cycle to indicate which type the current operation is;

sending a nand flash address needing to be operated;

and sending a data writing period.

7. The method for reading and writing nand flash data of the FPGA-based nand flash interface controller as recited in claim 6, wherein the operation types of the nand flash comprise block erasing, page programming and page reading.

8. The method for reading and writing nand flash data of the FPGA-based nand flash interface controller as recited in claim 7, wherein the block erase operation comprises the following sequence:

the FPGA sends an erasing confirmation instruction;

9. The method for reading and writing nand flash data of the FPGA-based nand flash interface controller as recited in claim 7, wherein the page programming operation comprises the following sequence:

10. The method for the nand flash interface controller to read and write the nand flash data based on the FPGA of claim 7, wherein the page reading operation comprises the following sequence:

the FPGA judges whether data movement is finished or not;