CN105955899B - Radar digital signal processing device based on all solid state semicondctor storage array - Google Patents
Radar digital signal processing device based on all solid state semicondctor storage array Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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Abstract
The invention discloses a kind of radar digital signal processing devices based on all solid state semicondctor storage array, comprising: SoC chip, AXI bus, PCIe controller, all solid state semicondctor storage array controller, SRIO controller and main control computer (PC)；PC obtains control instruction and radar return；PCIe controller receives control instruction and is parsed；SoC chip receives and executes the control instruction after parsing, then gives PC feedback operation state；All solid state semicondctor storage array controller encoded after radar return, and the radar return after coding is decoded, obtains radar return；All solid state semicondctor storage array controller obtains itself and the array control unit respectively working condition, and SoC chip is made to feed back the memory and the memory array controller respectively working condition to PC；SRIO controller obtains the radar return after control instruction and coding, and SoC chip is made to be parsed and be executed, and then feeds back current SRIO controller working condition to PCIe controller.
Description
Technical field
The invention belongs to all solid state memory technology fields, in particular to a kind of to be based on all solid state semicondctor storage array
Radar digital signal processing device, the broadcasting, importing or export of digital signal suitable for all solid state memory.
Background technique
High-speed data recording and controllable play-back technology are one of the key technologies in lot of domestic and foreign field, for detecting,
Investigation, monitoring, equipment Test, outfield debugging etc..In engineering, it usually needs record high speed raw digital signal data flow
So that the later period carries out the work such as fault diagnosis, scene check and archives data；And practical engineering application environment often has big temperature
Poor, more dust, macroseism such as swing at the mal-conditions.Therefore, hard real time, large capacity, high density, highly reliable digital collection broadcasting are set
It is standby to become research and development focus.
Current commercial high-speed processing apparatus mainly has automatic magnetic-tape filing cabinet and hard disk array (Redundant Arrays of
Independent Disks, RAID), such as current state-of-the-art European Nuclear Research Center computer center is large-scale hadron pair
(LHC) is collided using the magnetic-tape filing cabinet storage for being fully automated processing, when magnetic-tape filing cabinet is stored in vault, robot
Mechanical arm can be such that tape moves between memory layer and tape drive；Magnetic-tape filing cabinet storage has high capacity price ratio,
And there are numerous advantages such as ultrahigh speed, large capacity and low price, it is the ideal chose of Fixed Base high-speed high capacity storage；Certainly it lacks
Point also clearly, the framework of magnetic-tape filing cabinet storage is complicated, loosely organized, temperature applicable range is narrow, shock resistance is poor, intolerant to dust and
It takes up a large area.
Compared to this, solid-state memory has the advantages that compact-sized, strong environmental adaptability, and market is commercial at present consolidates
State hard disk (SSD) belongs to solid-state memory product；But current commercial solid state hard disk (SSD) product capacity is small, speed is low, collection
Become second nature difference, is not able to satisfy the storage of High speed real-time signal processing device and plays demand, and what exploitation was stored based on semiconductor solid-state
There are five technological difficulties for private memory tool: the semicondctor storage array controller of (one) design high density large capacity；(2)
In order to extend the failure free time of memory, to all storing semiconductors on the private memory stored based on semiconductor solid-state
Load balancing control is most important and difficult；(3) in the private memory stored based on semiconductor solid-state, to data
Storage and reading speed and data accuracy requirement it is particularly important, it is therefore desirable to pass through multinomial technology guarantee zero defect
Ground high speed operation；(4) the PCIe control between the private memory host based on semiconductor solid-state storage and high-speed data are logical
Letter；(5) (such as AD analog input card, Signal transacting board analysis, these equipment plate cards are total by VPX with the other equipment board in cabinet
Line backboard formed electrical connection) between high speed interface as Data entries and data outlet.
Summary of the invention
For above the shortcomings of the prior art, it is an object of the invention to propose that one kind is deposited based on all solid state semiconductor
The radar digital signal processing device of memory array, at radar digital signal of this kind based on all solid state semicondctor storage array
Reason device can overcome high bandwidth existing for existing memory technology record with play, high density storage, insertion VPX ruggedized equipment and
Carried out in particular surroundings using problem, while be also it is a kind of based on all solid state semiconductor storage, highly reliable, high density, height
The specific store of speed plays integrated apparatus.
To reach above-mentioned technical purpose, the present invention is realised by adopting the following technical scheme.
A kind of radar digital signal processing device based on all solid state semicondctor storage array, comprising: high density is entirely solid
State semicondctor storage array memory plane and main control computer；The all solid state semicondctor storage array memory plane packet of high density
Include FPGA and all solid state semicondctor storage array；The FPGA includes: embedded software core processor, AXI bus, PCIe control
Device, all solid state semicondctor storage array controller and SRIO controller；The main control computer includes a bidirectional port, institute
Stating embedded software core processor includes a bidirectional port, and the AXI bus includes four bidirectional ports, the PCIe controller
Comprising two bidirectional ports, all solid state semicondctor storage array controller includes four bidirectional ports, the SRIO control
Device processed includes two bidirectional ports, and all solid state semicondctor storage array includes a bidirectional port；
Main control computer is by a bidirectional port of the two-way electrical connection PCIe controller of PCIe bus, and the four of AXI bus
A bidirectional port is electrically connected another bidirectional port, complete of the bidirectional port of embedded software core processor, PCIe controller
One bidirectional port of one bidirectional port of solid state semiconductor memory array control unit, SRIO controller；It is all solid state partly to lead
The other three bidirectional port of body memory array control unit is electrically connected one bidirectional port of residue, complete of PCIe controller
Another bidirectional port of the bidirectional port of solid state semiconductor memory array, SRIO controller；
The main control computer passes through PCIe bus for the control instruction for obtaining control instruction and radar return
PCIe controller is sent to radar return；The control instruction includes store instruction, reads instruction, erasing instruction, initialization
Instruction and functional configuration operational order；
The PCIe controller solves the control instruction received for receiving control instruction and radar return
Analysis, is then sent to embedded software core processor for the control instruction after parsing by AXI bus；Embedded software core processor is used
Control instruction after receiving and executing parsing, then gives main control computer feedback operation state by PCIe controller；It will solution
Control instruction after analysis is sent to all solid state semicondctor storage array controller；The PCIe controller is by radar return simultaneously
It is packaged, and is communicated according to PCIe protocol with main control computer；The working condition is that the control instruction after parsing is opened
Begin to execute, be carrying out or be finished；
The all solid state semicondctor storage array controller is used to obtain control instruction and radar return after parsing, and
Radar return is encoded, the radar return after being encoded, and is sent out the radar return after coding by Nand I/O interface
It send to all solid state semicondctor storage array and is stored；All solid state semicondctor storage array is by the radar after the coding of storage
Echo is sent to all solid state semicondctor storage array controller and is decoded, and obtains radar return, and radar return is sent
To main control computer；All solid state semicondctor storage array controller obtains all solid state semiconductor according to the control instruction after parsing
The respective working condition of memory array and all solid state semicondctor storage array controller, and by all solid state semiconductor memory battle array
Respectively working condition is sent to embedded software core processor, Embedded Soft Core to column with all solid state semicondctor storage array controller
Processor is for receiving and being packaged all solid state semicondctor storage array and all solid state semicondctor storage array controller respectively
Then working condition is fed back all solid state semicondctor storage array to main control computer by PCIe controller and all solid state is partly led
The respective working condition of body memory array control unit；The radar return after coding is sent to SRIO controller simultaneously；
The SRIO controller is used to obtain the radar return after control instruction and coding, and the control instruction of acquisition is sent out
It send to embedded software core processor and is parsed and executed, current SRIO is then fed back to PCIe controller by AXI bus and is controlled
The working condition of device processed；The radar return after coding is sent to external equipment by SRIO link simultaneously and carries out HWIL simulation
Or Radar Signal Processing.
Beneficial effects of the present invention: the present invention uses field programmable gate array (Field Programmable Gate
Array, FPGA) as main realization platform of the invention, it is communicated, is used with main control computer using PCIe bus control unit
SRIO high speed data link and peripheral communications are realized under system administration control, are deposited to the highdensity solid-state of large capacity
Memory array carries out high-speed record, controllable broadcasting, data management and maintenance management function.
Detailed description of the invention
Invention is further described in detail with reference to the accompanying drawings and detailed description.
Fig. 1 is the structural schematic diagram of apparatus of the present invention；
Fig. 2 is the function structure chart of all solid state semicondctor storage array controller；
Fig. 3 is the structural schematic diagram of PCIe bus control unit；
Fig. 4 is the structural schematic diagram of SRIO controller module；
Fig. 5 is memory plane host computer interface figure；
Fig. 6 is that memory plane records sub-interface figure；
Fig. 7 is that memory plane plays back sub-interface figure；
Fig. 8 is that memory plane exports sub-interface figure；
Fig. 9 is that memory plane imports sub-interface figure.
Specific embodiment
It referring to Fig.1, is the structural schematic diagram of apparatus of the present invention；One kind of the invention is based on all solid state semiconductor memory battle array
The repertoire for including in the radar digital signal processing device of column is realized in main control computer and FPGA respectively, described to be based on
The digital signal dedicated unit of all solid state semicondctor storage array, comprising: all solid state semicondctor storage array of high density is deposited
Store up plate and main control computer；The all solid state semicondctor storage array memory plane of high density includes FPGA and all solid state semiconductor
Memory array；The FPGA includes: embedded software core processor, AXI bus, PCIe controller, all solid state semiconductor storage
Device array control unit and SRIO controller；The main control computer includes a bidirectional port, the embedded software core processor
Comprising a bidirectional port, the AXI bus includes four bidirectional ports, and the PCIe controller includes two bidirectional ports,
The all solid state semicondctor storage array controller includes four bidirectional ports, and the SRIO controller includes two bidirectional ends
Mouthful, all solid state semicondctor storage array includes a bidirectional port.
Main control computer passes through a bidirectional port of the two-way electrical connection PCIe controller of main control computer PCIe bus,
Four bidirectional ports of AXI bus be electrically connected the bidirectional port of embedded software core processor, PCIe controller another
Bidirectional port, a bidirectional port of all solid state semicondctor storage array controller, SRIO controller a bidirectional port；
The other three bidirectional port of all solid state semicondctor storage array controller is electrically connected residue one of PCIe controller
Bidirectional port, the bidirectional port of all solid state semicondctor storage array, SRIO controller another bidirectional port.
The main control computer passes through PCIe bus for the control instruction for obtaining control instruction and radar return
PCIe controller is sent to radar return；The control instruction includes store instruction, reads instruction, erasing instruction, initialization
Instruction and functional configuration operational order.
The PCIe controller solves the control instruction received for receiving control instruction and radar return
Analysis, is then sent to embedded software core processor for the control instruction after parsing by AXI bus；Embedded software core processor is used
Control instruction after receiving and executing parsing, then gives main control computer feedback operation state by PCIe controller；It will solution
Control instruction after analysis is sent to all solid state semicondctor storage array controller；The PCIe controller is by radar return simultaneously
It is packaged, and is communicated according to PCIe protocol with main control computer；The working condition is that the control instruction after parsing is opened
Begin to execute, be carrying out or be finished.
The all solid state semicondctor storage array controller is used to obtain control instruction and radar return after parsing, and
Radar return is encoded, the radar return after being encoded, and (Nand IO connects by semiconductor memory access interface
Mouthful) radar return after coding is sent to all solid state semicondctor storage array stores；All solid state semiconductor memory
Radar return after the coding of storage is sent to all solid state semicondctor storage array controller and is decoded by array, obtains thunder
Main control computer is sent to up to echo, and by radar return；After all solid state semicondctor storage array controller is according to parsing
Control instruction obtains all solid state semicondctor storage array and all solid state semicondctor storage array controller respectively working condition,
And by all solid state semicondctor storage array and all solid state semicondctor storage array controller respectively working condition be sent to it is embedding
Enter formula soft-core processor, embedded software core processor is for receiving and being packaged all solid state semicondctor storage array and all solid state half
Then the respective working condition of conductor memory array control unit is fed back to main control computer by PCIe controller and all solid state is partly led
The respective working condition of body memory array and all solid state semicondctor storage array controller；Simultaneously by the radar return after coding
It is sent to SRIO controller；Wherein, all solid state semicondctor storage array includes 96 Flash chips.
The SRIO controller is used to obtain the radar return after control instruction and coding, and the control instruction of acquisition is sent out
It send to embedded software core processor and is parsed and executed, current SRIO is then fed back to PCIe controller by AXI bus and is controlled
The working condition of device processed；The radar return after coding is sent to external equipment by SRIO link simultaneously and carries out HWIL simulation
Or Radar Signal Processing.
Specifically, apparatus of the present invention emphasis is to realize that all solid state semicondctor storage array of high density stores plate array control
System, embedded software core processor intarconnected cotrol and embedded software core processor are integrated, and wherein embedded software core processor is this hair
Bright control core is responsible for state-maintenance and the operation distribution of whole device, the FPGA internal frame diagram of institutional framework as shown in figure 1
It is shown, the purposes of each sub-function module is illustrated in detail below:
It (one) is the function structure chart of all solid state semicondctor storage array controller referring to Fig. 2；All solid state semiconductor is deposited
The modular structure of memory array controller include all solid state semicondctor storage array memory, user logic, infrastructure and
State acquisition unit: all solid state semicondctor storage array memory includes: storage control, user logic layer, basis
Facility, state acquisition unit；The storage control includes: physical layer, Media Interface Connector layer, memory command layer, storage link
Layer, memory maintenance and configuration unit；The physical layer is connect with the Media Interface Connector layer, and the Media Interface Connector layer is deposited with described
The connection of reservoir layer order, the memory command layer are connect with the storage link layer, the storage link layer and the user
It is connected using logical layer；The user logic includes four ports, is separately connected the user using logical layer, the memory
Maintenance and configuration unit, the infrastructure and the state acquisition unit.
The physical layer be used for receives parse after control instruction and radar return, the control instruction after the parsing include
Store instruction reads instruction, erasing instruction, initialization directive and functional configuration operational order, and obtains and meet Nand Flash
Double Data Rate synchronous sequence interface model physical layer data stream that technical manual defines, single times of rate synchronous timing interface model object
Recombination data stream after managing layer data stream or parsing, and, delay adjustment synchronous by data edge to radar return, timing adjust
Or be fanned out to, it obtains meeting the operation timing that Nand Flash technology handbook defines, is then forwarded to all solid state semiconductor memory
In array；Physical layer is also used to meet what Nand Flash technology handbook defined from Nand flash storage array received simultaneously
Sequential data stream, then in turn through cache synchronization, timing adjustment, delay adjustment, timing reconstruction, data resampling or data pair
Neat operation, obtain meeting Double Data Rate synchronous sequence interface model physical layer data stream that Nand Flash technology handbook defines or
Single times of rate synchronous timing interface model physical layer data stream, and it is sent to Media Interface Connector layer.
It is described to meet Nand Flash technology hand for what is sended over by local timing interface (NIF) reception physical layer
The Double Data Rate synchronous sequence interface model physical layer data stream or single times of rate synchronous timing interface model physical layer of volume definition
Nand Flash manipulation of data stream after the decomposition that data flow and store command layer send over, and according to Nand Flash
The Double Data Rate synchronous sequence interface model physical layer data stream or single times of rate synchronous timing interface model that technical manual defines
Successively carry out parsing operation and recombination data stream, the recombination data stream after being parsed, then by the recombination number after the parsing
Physical layer is sent to by physical link interface (PIF) according to stream；Media Interface Connector layer is used to pass through PIF interface physical layer simultaneously
The Double Data Rate synchronous sequence interface model physical layer data stream, the list that meet Nand Flash technology handbook and define sended over
Recombination data stream after times rate synchronous timing interface model physical layer data stream or parsing, and successively parsed and reconstructed,
Nand Flash manipulation of data stream is obtained, then passes through local timing interface (NIF) interface for the Nand Flash operand
Memory command layer is sent to according to stream.
The memory command layer is connect for receiving the Nand Flash manipulation of data stream, and respectively by ordering to control
Mouth (CIF) obtains the respective operations instruction of Nand Flash manipulation of data stream from storage link layer, and is connect by ordering to control
Mouth (CIF) obtains the data frame for meeting command interface timing from storage link layer, is then successively parsed and is decomposed, is divided
Nand Flash manipulation of data stream after solution, then grasped the Nand Flash after the decomposition by local timing interface (NIF)
Media Interface Connector layer is sent to as data flow；Simultaneous memory layer order is sended over by NIF interface Media Interface Connector layer
Nand Flash manipulation of data stream after decomposition obtains command interface timing after being packaged, and passes through order control interface
(CIF) it is sent to storage link layer.
The storage link layer is obtained for receiving the command interface timing, and by memory control interface (MIF)
The operational order and respective operations data that user applies logical layer to send over, and successively by tissue frame format, addition mistake
After control coding, data traffic control, the data frame for meeting command interface timing is obtained, then according to depositing order control interface
(CIF) data frame for meeting command interface timing is sent to memory command layer by timing requirements；Link layer is stored simultaneously
To the command interface timing successively by parsing frame format, decoding extract after, obtain decoded command interface timing, and lead to
It crosses memory control interface (MIF) and the decoded command interface timing is sent to user using logical layer.
The user logic is respectively used to obtain required system clock and use when register configuration order, user logic work
The operational order of data format needed for family logic global reset signal, operational order data flow, user logic and current time
Physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration unit, infrastructure and use
Apply logical layer respectively working condition in family；The operational order data stream packets containing store instruction, read instruction, erasing instruction, first
Beginningization instruction and the respective corresponding data stream of functional configuration operational order.
The memory maintenance and configuration unit belong to independent functional unit in Memory Controller, for by auxiliary
Adjuvant grafting mouth obtains the register configuration order that user logic sends over, and then parses the register configuration order, is solved
Register configuration order after analysis, and the register configuration order after parsing is respectively sent to physical layer, Media Interface Connector layer, is deposited
Reservoir layer order and storage link layer；Simultaneous memory maintenance and configuration unit for respectively read physical layer, Media Interface Connector layer,
Memory command layer and the storage corresponding register configuration order of link layer, and user is sent to by satellite interface and is patrolled
Volume.
The infrastructure obtains required system clock and the user logic overall situation when user logic works by system interface
Reset signal, required system clock and user logic global reset signal are successively locked when then working the user logic
Xiang Huan, clock are fanned out to and reset simultaneously operating, obtain multiple work clocks and with the synchronous work respectively of multiple work clocks
Reset signal, and synchronous power on reset signal is respectively sent to physics respectively by multiple work clocks and with multiple work clocks
Layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration unit；Meanwhile when by multiple work
Clock and synchronous power on reset signal is exported to user logic respectively with multiple work clocks.
The state acquisition unit is for obtaining current time physical layer, Media Interface Connector layer, memory command layer, storage chains
Road floor, memory maintenance and configuration unit, infrastructure and user apply logical layer respectively working condition, and are connect by state
Mouthful by current time physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration unit, base
Respectively working condition is sent to user logic using logical layer by Infrastructure and user.
It is the layering of user logic custom feature that the user, which applies logical layer, for obtaining user by user interface
The operational order of data format needed for operational order data flow and user logic that logic sends over, and it is organized into memory control
Then data format and operational format needed for interface (MIF) processed are sent to storage link by memory control interface (MIF)
Layer；The storage link layer obtains the operational order that Nand flash storage array can identify, institute from user logic simultaneously
The operational order that Nand flash storage array can identify is stated to visit including storage, reading, functional configuration operation, direct store
Ask (Direct Menory Access, DMA) write-in, DMA read, programmable input and output (Program Input Output,
PIO) write-in, PIO reading, bulk erasure, simple erasing or initialization operation order, and to the Nand flash storage battle array
The operational order that arranging can identify successively is parsed and is reconstructed, and the operational order of data format needed for user logic is obtained, then
The operational order of data format needed for the user logic is sent to user logic by state interface.
It (two) is the structural schematic diagram of PCIe bus control unit referring to Fig. 3；PCIe controller includes physical layer, link layer
And transport layer, the transport layer include register file, direct memory access (Direct Memory Access, DMA) control
Device, power management；Physical layer and link layer complete respective function by the IP that Xilinx is provided respectively；Transport layer provides two pairs
To port, respectively user register port (User Register Port) and direct memory access (Direct Memory
Access, DMA) port, when wherein program input/output is transmitted, user accesses register file by user register port
When, respectively correspond the up arrow and down arrow of this port), register file passes through PCIe protocol transparent mapped to master control
Storage region in computer is read out, and the access includes reading and writing；The port DMA high-volume is completed by dma controller
Data transmit-receive work；User data enters PCIe bus control unit by the port DMA, successively passes through dma controller, link layer and object
Reason layer is packaged according to PCIe protocol, obtains communication data, and be sent to main control computer by PCIe bus；Master control simultaneously
Computer issues communication data by PCIe bus, is successively decapsulated, is used by physical layer, link layer and transport layer
User data, and user data is sent out by the port DMA；The power management is power management module, for being PCIe bus
Controller power supply.
(3) SRIO controller uses full mesh interconnection architecture, can be realized the high speed interconnection of arbitrary node, i.e. realization plate
Between pass through at a high speed, as shown in figure 4, SRIO controller include user logic, direct memory access (Direct Memory
Access, DMA) controller, transport layer, link layer, physical layer, infrastructure；User logic transmits data to DMA control
Device successively passes through transport layer, link layer and physical layer by SRIO agreement again after dma controller encapsulation and is packaged, obtains
The data completed to final encapsulation, and the data that final encapsulation is completed are sent according to SRIO agreement by SRIO link；Simultaneously
The data of SRIO chain road are received, and are successively exported after the decapsulation of physical layer, link layer and transport layer to user logic.
(4) embedded software core processor is control core of the invention, is responsible for state-maintenance and the operation point of whole system
Match, major function is to receive and parse through the operational order from main control computer and detection lug internal controller state and pass through PCIe
Bus is reported to host computer, instruction explanation function be responsible for for the operational order of host computer being construed to memory array controller,
The register instruction of SRIO controller is responsible for configuration feature register and fill state register.
Above-mentioned four big functional module is connected, at Embedded Soft Core using embedded software core processor as core by AXI bus
It manages device and PCIe controller, SRIO controller and all solid state semicondctor storage array controller is completed respectively by AXI bus
Function setting and state are read, as shown in the FPGA internal frame diagram of Fig. 1；Secondly, PCIe controller, SRIO controller and all solid state half
There is dedicated high speed interface between conductor memory array control unit respectively, meet AXI_Stream standard, can pass through
The control of embedded software core processor carries out the data transmission of high speed.
Wherein, above-mentioned embedded software core processor, PCIe bus control unit, all solid state semicondctor storage array controller
It realizes inside onboard FPGA with SRIO controller, all solid state is partly led by the way that the I/O interface bus marco of Nand Flash is onboard
Body memory array realizes the storage of high-speed high capacity data；In apparatus of the present invention, all solid state semiconductor memory battle array of high density
Column memory plane is attached by PCIe bus with main control computer, and completing order control and data transmission, (envelope is imported and led
Out), the data connection between other equipment is respectively completed by SRIO controller, and completes record and the playback of data；
The other equipment such as AD analog input card, Signal transacting board analysis, and connected by VPX bus backplane.
In the global structure of the present invention that Fig. 1 is shown, main control computer as host computer play center control, data storage and
Restore function.Fig. 5 is memory plane control interface figure；In Fig. 5, the signified part of label 1 is the file information list, for showing simultaneously
The class file information of record storage equipment, including filename, file type, record time, file size, initial address, end
Address and data source, the class file information are stored in main control computer by XML file, and main control computer is by being defined in
Host interface protocol in PCIe bus completes the communication between memory plane, realizes state self-test, record, playback, imports, leads
Out, it deletes, format and forces to stop function, illustrate the effect of each single item function in detail below.
The signified part of label 2 is self-test in Fig. 5, i.e., sends the self-test order in Host Interface Commands to memory plane, successively
The detection of memory plane working condition and feedback testing result are completed, wherein the detection includes all solid state semicondctor storage array
Controller working condition, the operating mode of all solid state semicondctor storage array and current state, PCIe controller working condition,
The link connection state and embedded software core processor operating status of SRIO controller.
The signified part of label 3 is record in Fig. 5, i.e., sends the record order in Host Interface Commands to memory plane, described
Record order includes record start address and record length, and Fig. 6 display record work sub-interface, in the interface, user can match
Recording parameters are set, the recording parameters are record filename, record time, record start address, record length；Memory plane receives
After order, embedded software core processor carries out resolve command, record length and record start address is obtained, to all solid state semiconductor
Memory array controller sends batch write operation, and transmits and receives and operate to SRIO controller, and control SRIO controller
Record length and record start address are sent into all solid state semicondctor storage array controller, complete record length and recorded
Beginning address is received and recorded in all solid state semicondctor storage array.
The signified part of label 4 is playback in Fig. 5, i.e., sends the playback command in Host Interface Commands to memory plane, described
Playback command includes playback initial address, playback length and flow control option, Fig. 7 display playback work sub-interface, on the boundary
In face, user can configure playback parameter, and the playback parameter is playback file name, playback duration, playback initial address, playback length
Degree, enabled, the playback flow control word of playback flow control etc.；After memory plane receives order, Embedded Soft Core processor scheduling
SRIO controller and all solid state semicondctor storage array controller read data simultaneously from all solid state semicondctor storage array
It is sent by SRIO interface toward other equipment, the other equipment are AD analog input card, Signal transacting board analysis, and total by VPX
The connection of line backboard；Wherein, the flow control option belongs to source flow control, sends data speed for controlling.
The signified part of label 5 is export in Fig. 5, i.e., sends the export (swf) command in Host Interface Commands to memory plane, described
Export (swf) command includes export initial address and derived length, and Fig. 8 display export work sub-interface, in the interface, user can match
Derived parameter is set, the derived parameter is export name, export time, export initial address, derived length etc.；Memory plane is received
To after order, embedded software core processor resolve command obtains export initial address and derived length, passes through AXI bus marco
All solid state semicondctor storage array controller is read, while being sent directly by AXI bus to PCIe controller
Internal storage access order, PCIe controller receive direct memory access order and are sent to main control computer, and main control computer receives
Dma controller after direct memory access order in PCI allocation e controller；Wherein, the configuration includes the packet of dma controller
Length, the packet number of dma controller and the address of dma controller；Finally, all solid state semicondctor storage array controller is read
Export initial address and derived length will be sent with dma mode to main control computer by the dma controller of PCIe controller.
In Fig. 5 the signified part of label 6 sends the importing order in Host Interface Commands to memory plane to import, described
Importing order includes importing initial address and importing length, and Fig. 9 display imports work sub-interface, and in the interface, user can match
Importing parameter is set, the importing parameter is to import filename, import the time, import initial address, import length etc..Board receives
It imports after order and embedded software core processor is sent to by AXI bus, embedded software core processor is received to import to order and be gone forward side by side
Row parsing obtains and imports initial address and import length, then the dma controller in PCI allocation e controller and notifies master control meter
Calculation machine, main control computer receives the dma controller imported after command response in PCI allocation e controller, then from main control computer
It receives and imports initial address and import length and be written in all solid state semicondctor storage array；Wherein, the configuration includes DMA
Packet length, the packet number of dma controller and the address of dma controller of controller.
In Fig. 5 the signified part of label 7 sends the delete command in Host Interface Commands to memory plane to delete, described
Delete command includes deleting initial address and deleting length, while main control computer removes the respective file in the file information list
Record, after memory plane receives delete command, all solid state semicondctor storage array controller of Embedded Soft Core processor scheduling is simultaneously
Start erasing operation, the respective file is recorded and carries out physics erasing operation.
In Fig. 5 the signified part of label 8 sends the formatting command in Host Interface Commands to memory plane to format,
Main control computer empties the record of the All Files in the file information list, after board receives formatting command, embedded software simultaneously
Core processor dispatches all solid state semicondctor storage array controller and starts full array erasing operation, and then partly leads to all solid state
Body memory array carries out physics erasing operation.
In Fig. 5 the signified part of label 9 is stopped to force to stop for sending the pressure in Host Interface Commands to memory plane
It only orders, while main control computer waits the state feedback between memory plane；Board receives after pressure ceases and desist order, embedded software
Core processor is controlled according to current working status to SRIO controller, PCIe controller and all solid state semicondctor storage array
Device sends corresponding emergent stopping control respectively, and then memory plane enters Auto-Sensing Mode, detects memory plane current state and feeds back
To main control computer.
In addition, dedicated unit of the present invention has following function:
(1) all solid state semiconductor array reinforces storage equipment: under conditions of outfield experiments and real system are run, receiving
The original data stream of collection high speed facilitates the analysis of phenomenon, technology adjustment and system mode monitoring, under most conditions, needs to add
Solid special equipment could cope with the mal-condition including high temperature difference, high humility, strong motion, more dust etc. of real system operation
Weather and climate condition.The present invention uses all solid state semiconductor storage, belongs to reinforcement embedded device, has technical grade environment item
Part index, intrinsic mechanical stability ensure that the reliable and stable operation of this equipment under severe conditions from design.
(2) record of high sDeed real-time digital signal and broadcasting: former in the embedded system for real-time signal processing of high speed
The high bandwidth of beginning data is proposed high requirement to acquisition, storage and broadcasting；And initial data acquisition and playback for
System Performance Analysis, system running state monitoring will be it is indispensable, the present invention is realized by multinomial technological means embedding
The acquisition and playback of high speed raw digital signal are realized in embedded system.
(3) be used for the random waveform signal digital signal broadcast source of HWIL simulation: the joint debugging work of large scale system is often
It is related to the more common joint debuggings of unit, the extension set in the subsystem debugging of research and development early period, use process is examined, the performance of algorithm is commented
Estimate and requires digital signal playback equipment and provide stable, controllable, the true front end of simulation number to signal processing subsystem
Signal, the present invention provide complete solution for such HWIL simulation demand.The certain wave of initial data, emulation construction
Graphic data or other any data for meeting particular demands can first pass through main control computer in advance and import this equipment, and embedding
The data are played in embedded system, realize the function of HWIL simulation validation test.
The present invention realizes the dedicated high density high speed storing of integration and broadcasting by following technological means:
(1) memory control problem is solved using the high density large-capacity semiconductor memory array controller of customization: this
Invention is using separate semiconductor storage particle as basic storage medium；For large-scale storage array still without dedicated control
Device IP processed provides use, and therefore, the present invention uses the memory array controller of customized development, completes the height to high density arrays
The read and write access of fast zero defect controls.
(2) control and data exchange with main control computer are realized using PCIe bus: the present invention as computer outside
Peripheral equipment accesses computer system by PCIe bus, and carry passes through main control computer in the PCIe bus of computer-internal
It realizes to order control of the invention and data access operation, there is biggish control flexibility and data interface bandwidth.
(3) acquisition and broadcasting of high speed original data stream are realized using SRIO data/address bus: in embedded device,
The present invention and other embedded boards are realized using SRIO controller to be interconnected, and is carried out the acquisition of high speed original data stream and broadcast
It puts, belongs to isomery full mesh interconnection architecture, provide the controllable system interconnection of high speed.
(4) realize controlled speed broadcasting using source flow control technique and storage dedicated frame design: the present invention uses
The dedicated dedicated frame structure of storage is packaged the initial data of storage, improves memory reliability, and cooperate the present invention
Source flow control technique, can be realized the output effective data rate of controllable variable, meet rear end receive system to difference
The requirement of data transfer rate improves system adaptation performance.
(5) system remote upgrade and demand change: this hair are realized as master controller using embedded software core processor
It is bright to use the connection of AXI bus as onboard master controller, between embedded software core processor and onboard peripheral hardware using system on chip,
It ensure that the high bandwidth of connection, the flexibility of control and convenient and fast expansion, embedded software core processor external interface abundant
Characteristic with software programmable is that the present invention provides the characteristics of remote system upgrade.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range；In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (8)
1. a kind of radar digital signal processing device based on all solid state semicondctor storage array characterized by comprising high
The all solid state semicondctor storage array memory plane of density and main control computer；The all solid state semicondctor storage array of high density
Memory plane includes FPGA and all solid state semicondctor storage array；The FPGA include: embedded software core processor, AXI bus,
PCIe controller, all solid state semicondctor storage array controller and SRIO controller；The main control computer includes one double
To port, the embedded software core processor includes a bidirectional port, and the AXI bus includes four bidirectional ports, described
PCIe controller includes two bidirectional ports, and all solid state semicondctor storage array controller includes four bidirectional ports,
The SRIO controller includes two bidirectional ports, and all solid state semicondctor storage array includes a bidirectional port；
Main control computer passes through a bidirectional port of the two-way electrical connection PCIe controller of PCIe bus, and four of AXI bus are double
The bidirectional port of embedded software core processor, another bidirectional port of PCIe controller, all solid state is electrically connected to port
One bidirectional port of one bidirectional port of semicondctor storage array controller, SRIO controller；All solid state semiconductor is deposited
The other three bidirectional port of memory array controller is electrically connected one bidirectional port of residue, all solid state of PCIe controller
Another bidirectional port of the bidirectional port of semicondctor storage array, SRIO controller；
The main control computer passes through PCIe bus for the control instruction and thunder for obtaining control instruction and radar return
PCIe controller is sent to up to echo；The control instruction includes store instruction, reads instruction, erasing instruction, initialization directive
With functional configuration operational order；
The PCIe controller parses the control instruction received for receiving control instruction and radar return, so
The control instruction after parsing is sent to by embedded software core processor by AXI bus afterwards；Embedded software core processor is for connecing
It receives and executes the control instruction after parsing, then give main control computer feedback operation state by PCIe controller；After parsing
Control instruction be sent to all solid state semicondctor storage array controller；The PCIe controller carries out radar return simultaneously
It is packaged, and is communicated according to PCIe protocol with main control computer；The working condition is that the control instruction after parsing starts to hold
Row is carrying out or is finished；
The all solid state semicondctor storage array controller is used to obtain control instruction and radar return after parsing, and to thunder
It is encoded up to echo, the radar return after being encoded, and the radar return after coding is sent to all solid state semiconductor and is deposited
Memory array is stored；Radar return after the coding of storage is sent to all solid state half by all solid state semicondctor storage array
Conductor memory array control unit is decoded, and obtains radar return, and radar return is sent to main control computer；It is all solid state
Semicondctor storage array controller obtains all solid state semicondctor storage array and all solid state according to the control instruction after parsing
The respective working condition of semicondctor storage array controller, and all solid state semicondctor storage array and all solid state semiconductor are deposited
Respectively working condition is sent to embedded software core processor to memory array controller, and embedded software core processor is for receiving and beating
All solid state semicondctor storage array and all solid state semicondctor storage array controller respectively working condition are wrapped, is then passed through
PCIe controller feeds back all solid state semicondctor storage array to main control computer and all solid state semicondctor storage array controls
The respective working condition of device；The radar return after coding is sent to SRIO controller simultaneously；
The SRIO controller is used to obtain the radar return after control instruction and coding, and the control instruction of acquisition is sent to
Embedded software core processor is parsed and is executed, and then feeds back current SRIO controller to PCIe controller by AXI bus
Working condition；The radar return after coding is sent to external equipment by SRIO link simultaneously and carries out HWIL simulation or thunder
Up to signal processing.
2. a kind of radar digital signal processing device based on all solid state semicondctor storage array as described in claim 1,
It is characterized in that, the modular structure of all solid state semicondctor storage array controller includes all solid state semiconductor memory battle array
Column memory, user logic, infrastructure and state acquisition unit: all solid state semicondctor storage array memory packet
It includes: storage control, user logic layer, infrastructure, state acquisition unit；The storage control includes: physical layer, medium
Interface layer, memory command layer, storage link layer, memory maintenance and configuration unit；The physical layer and the Media Interface Connector
Layer connection, the Media Interface Connector layer are connect with the memory command layer, the memory command layer and the storage link layer
Connection, the storage link layer are connect with the user logic layer；User logic includes four ports, is separately connected the user
Logical layer, the memory maintenance and configuration unit, the infrastructure and the state acquisition unit.
3. a kind of radar digital signal processing device based on all solid state semicondctor storage array as claimed in claim 2,
It is characterized in that, the physical layer is used to receive control instruction and radar return after parsing, the control instruction after the parsing
Including store instruction, instruction, erasing instruction, initialization directive and functional configuration operational order are read, and it is same to obtain Double Data Rate
Recombination after walking timing interface model physical layer data stream, single times of rate synchronous timing interface model physical layer data stream or parsing
Data flow, and synchronous data edge, delay adjustment, timing adjustment are carried out to radar return or are fanned out to, the operation timing is obtained, then
It is sent in Nand flash storage array；Ordinal number when physical layer is also used to from Nand flash storage array received simultaneously
According to stream, grasped then in turn through cache synchronization, timing adjustment, delay adjustment, timing reconstruction, data resampling or alignment of data
Make, obtains Double Data Rate synchronous sequence interface model physical layer data stream or the single times of rate synchronous timing interface model physics number of plies
According to stream, and it is sent to Media Interface Connector layer；
The Media Interface Connector layer is for receiving the Double Data Rate synchronous sequence interface model physical layer data that physical layer sends over
Stream or single times of rate synchronous timing interface model physical layer data stream, and after obtaining the decomposition that sends over of store command layer
Nand Flash manipulation of data stream, and according to Double Data Rate synchronous sequence interface model physical layer data stream or single times of rate synchronous
Timing interface model successively carries out parsing operation and recombination data stream, the recombination data stream after being parsed, then by the solution
Recombination data stream after analysis is sent to physical layer；Media Interface Connector layer is same for receiving the Double Data Rate that physical layer sends over simultaneously
Recombination after walking timing interface model physical layer data stream, single times of rate synchronous timing interface model physical layer data stream or parsing
Data flow, and successively parsed and reconstructed, Nand Flash manipulation of data stream is obtained, then operates the Nand Flash
Data flow is sent to memory command layer.
4. a kind of radar digital signal processing device based on all solid state semicondctor storage array as claimed in claim 2,
It is characterized in that, the memory command layer is used to receive the Nand Flash manipulation of data stream, and respectively from storage link
Layer obtains the corresponding instruction of Nand Flash manipulation of data stream, and the number for meeting command interface timing is obtained from storage link layer
According to frame, is then successively parsed and decomposed, the Nand Flash manipulation of data stream after being decomposed, then will be after the decomposition
Nand Flash manipulation of data stream is sent to Media Interface Connector layer；Simultaneous memory layer order is transmitted across for receiving Media Interface Connector layer
Nand Flash manipulation of data stream after the decomposition come obtains command interface timing after being packaged, and by the command interface
Timing is sent to storage link layer；
The storage link layer obtains the operational order that user logic layer sends over for receiving the command interface timing
With respective operations data, and successively by tissue frame format, addition error control coding, data traffic control after, met
The data frame of command interface timing, then according to depositing command interface timing requirements for the data frame for meeting command interface timing
It is sent to memory command layer；Link layer is stored simultaneously, and the command interface timing is successively mentioned by parsing frame format, decoding
After taking, decoded command interface timing is obtained, and the decoded command interface timing is sent to user logic layer.
5. a kind of radar digital signal processing device based on all solid state semicondctor storage array as claimed in claim 2,
It is characterized in that, the user logic is respectively used to obtain required system clock when register configuration order, user logic work
With the operational order of data format needed for user logic global reset signal, operational order and data flow, user logic, and work as
Preceding moment physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration unit, infrastructure
And the respective working condition of user logic layer；The operational order includes store instruction, reads instruction, erasing instruction, initialization
Instruction and functional configuration operational order；
Then the memory maintenance and configuration unit are parsed for obtaining the register configuration order that user logic sends over
The register configuration order, the register configuration order after being parsed, and the register configuration order after parsing is distinguished
It is sent to physical layer, Media Interface Connector layer, memory command layer and storage link layer；Simultaneous memory maintenance and configuration unit are used for
Physical layer, Media Interface Connector layer, memory command layer and the storage corresponding register configuration order of link layer are read respectively, and
It is sent to user logic；
The infrastructure obtains required system clock and user logic global reset signal when user logic work, then to institute
When stating user logic work required system clock and user logic global reset signal successively carries out phaselocked loop, clock is fanned out to and
Reset simultaneously operating, obtain multiple work clocks and with multiple work clocks synchronous power on reset signal respectively, and will be multiple
Work clock and synchronous power on reset signal is respectively sent to physical layer, Media Interface Connector layer, deposits respectively with multiple work clocks
Reservoir layer order, storage link layer, memory maintenance and configuration unit；Meanwhile by multiple work clocks and when with multiple work
The power on reset signal that clock synchronizes respectively is exported to user logic.
6. a kind of radar digital signal processing device based on all solid state semicondctor storage array as claimed in claim 2,
It is characterized in that, the state acquisition unit is for obtaining current time physical layer, Media Interface Connector layer, memory command layer, depositing
It stores up link layer, memory maintenance and configuration unit, infrastructure and user and applies logical layer respectively working condition, and pass through shape
State interface is single by current time physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration
Respectively working condition is sent to user logic for member, infrastructure and user logic layer；
The user logic layer is organized into memory control for obtaining the operational order and data flow that user logic sends over
Data format needed for interface processed and operational format are then forwarded to storage link layer；The storage link layer is patrolled from user simultaneously
It collects and obtains the operational order that Nand flash storage array can identify, the Nand flash storage array can identify
Operational order include storage, read, functional configuration operation, direct memory access write-in, direct memory access read, are programmable
Input and output write-in, programmable input and output reading, bulk erasure, simple erasing or initialization operation order, and to described
The operational order that Nand flash storage array can identify successively is parsed and is reconstructed, and data needed for user logic are obtained
The operational order of format, then the operational order of data format needed for the user logic is sent to user logic.
7. a kind of radar digital signal processing device based on all solid state semicondctor storage array as described in claim 1,
It is characterized in that, the PCIe controller include physical layer, link layer and transport layer, the transport layer include register file,
Direct memory access controller, power management；Physical layer and link layer complete respective function by the IP that Xilinx is provided respectively；
Transport layer provides two bidirectional ports, respectively user register port and direct memory access port, wherein program output/defeated
When entering to transmit, when user accesses register file by user register port, register file is reflected by the way that PCIe protocol is transparent
The storage region being mapped in main control computer is read out；Direct memory access port high-volume number is completed by dma controller
According to transmitting-receiving work；User data enters PCIe bus control unit by direct memory access port, successively passes through dma controller, chain
Road floor and physical layer are packaged according to PCIe protocol, obtain communication data, and be sent to main control computer by PCIe bus；
Main control computer issues communication data by PCIe bus simultaneously, is successively unsealed by physical layer, link layer and transport layer
Dress, obtains user data, and user data is sent out by direct memory access port；The power management is power management mould
Block, for powering for PCIe bus control unit.
8. a kind of radar digital signal processing device based on all solid state semicondctor storage array as described in claim 1,
It is characterized in that, the SRIO controller includes user logic, direct memory access controller, transport layer, link layer, physics
Layer, infrastructure；User logic transmits data to dma controller, presses again after direct memory access controller encapsulation
SRIO agreement is successively passed through transport layer, link layer and physical layer and is packaged, and obtains the data of final encapsulation completion, and will be final
The data that encapsulation is completed are sent according to SRIO agreement by SRIO link；The data of SRIO chain road are received simultaneously, and are successively passed through
It exports after crossing physical layer, link layer and transport layer decapsulation to user logic.
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| CN107885693A (en) * | 2017-11-28 | 2018-04-06 | 南京理工大学 | High-capacity and high-speed data transfer and storage system and method based on PCIE3.0 |
| CN108345555B (en) * | 2018-03-13 | 2021-10-08 | 算丰科技（北京）有限公司 | Interface bridge circuit based on high-speed serial communication and method thereof |
| CN111258504B (en) * | 2020-01-15 | 2023-05-30 | 西安电子科技大学 | Storage control system based on SATA interface solid state disk |
| CN112100817B (en) * | 2020-08-20 | 2022-07-12 | 上海机电工程研究所 | Intelligent heterogeneous IO data conversion method and system based on distributed simulation system |
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