CN105955899A - Radar digital signal processing device based on all-solid-state semiconductor memory array - Google Patents
Radar digital signal processing device based on all-solid-state semiconductor memory array Download PDFInfo
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- CN105955899A CN105955899A CN201610256793.2A CN201610256793A CN105955899A CN 105955899 A CN105955899 A CN 105955899A CN 201610256793 A CN201610256793 A CN 201610256793A CN 105955899 A CN105955899 A CN 105955899A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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Abstract
The invention discloses a radar digital signal processing device based on an all-solid-state semiconductor memory array. The radar digital signal processing device comprises a SoC chip, an AXI bus, a PCIe controller, an all-solid-state semiconductor memory array controller, a SRIO controller, and a main control computer (PC). The PC obtains a control instruction and radar echo. The PCIe controller receives the control instruction and analyzes the control instruction. The SoC chip receives and executes the analyzed control instruction, and then feeds back operation states to the PC. The all-solid-state semiconductor memory array controller obtains encoded radar echo, and decodes the encoded radar echo to obtain radar echo. The all-solid-state semiconductor memory array controller obtains respective operating state of the all-solid-state semiconductor memory array controller and the array controller, and makes the SoC chip feed the respective operating state of a storage and the storage array controller back to the PC. The SRIO controller obtains the control instruction and the encoded radar echo, and makes the SoC chip analyze and execute the control instruction, and feeds the current SRIO controller operating state back to the PCIe controller.
Description
Technical field
The invention belongs to all solid state memory technology field, particularly to a kind of thunder based on all solid state semicondctor storage array
Reach digital signal processing device, it is adaptable to the broadcasting of digital signal in all solid state memorizer, import or derive.
Background technology
High-speed data recording and controlled play-back technology are one of key technologies in lot of domestic and foreign field, be used for detecting, investigate,
Supervision, equipment Test, outfield debugging etc..In engineering, it usually needs high speed raw digital signal traffic logging is got off with
Phase carries out the work such as fault diagnosis, scene check and archives data after an action of the bowels；And practical engineering application environment often have the big temperature difference,
Many dust, macroseism such as swing at the mal-condition.Therefore, hard real time, Large Copacity, high density, highly reliable digital collection are play
Equipment becomes research and development focus.
Current commercial high-speed processing apparatus mainly has automatic magnetic-tape filing cabinet and hard disk array (Redundant Arrays of
Independent Disks, RAID), if computer center of current state-of-the-art CERN is large-scale hadron pair
Collide the magnetic-tape filing cabinet storage that (LHC) use full automation to process, when magnetic-tape filing cabinet is stored in vault, machine
The mechanical arm of people can make tape move between memory layer and tape drive；Magnetic-tape filing cabinet storage has high capacity price
Ratio, and there are numerous advantages such as ultrahigh speed, Large Copacity and low price, it is the ideal chose of Fixed Base high-speed high capacity storage；
Certainly shortcoming is the most clearly, the framework of magnetic-tape filing cabinet storage is complicated, loosely organized, temperature applicable range is narrow, shock resistance is poor,
It is weak to dust and floor space is big.
Compared to this, the advantage that solid-state memory has compact conformation, adaptive capacity to environment is strong, the solid-state that current market is commercial
Hard disk (SSD) belongs to solid-state memory product；But current commercial solid state hard disc (SSD) product capacity is little, speed is low,
Integration is poor, it is impossible to meets storage and the broadcasting demand of High speed real-time signal processing device, and develops and store based on semiconductor solid-state
Private memory there are five technological difficulties: (one) designs high density jumbo semicondctor storage array controller；
(2) in order to extend the failure free time of memorizer, to storages all on the private memory stored based on semiconductor solid-state half
It is most important and difficult that the load balancing of conductor controls；(3) in the private memory stored based on semiconductor solid-state,
Storage and reading speed to data, and the requirement of data accuracy is particularly important, it is therefore desirable to ensured by multinomial technology
Free of errors high speed operation；(4) PCIe and between private memory main frame based on semiconductor solid-state storage controls and high
Speed data communication；(5) with other equipment plate cards in cabinet (such as AD analog input card, signal processing board, these equipment
Board by VPX bus backplane formed electrical connection) between high speed interface as Data entries and data outlet.
Summary of the invention
The deficiency existed for above prior art, it is an object of the invention to propose one based on all solid state semiconductor memory
The radar digital signal processing device of array, this kind radar digital signal processing based on all solid state semicondctor storage array fills
Put the high bandwidth record and broadcasting, high density storage, embedding VPX ruggedized equipment and spy that existing memory technology can be overcome to exist
Different environment carries out the difficult problem used, be also simultaneously a kind of based on all solid state semiconductor storage, highly reliable, high density, height
The specific store of speed plays integrated apparatus.
For reaching above-mentioned technical purpose, the present invention adopts the following technical scheme that and is achieved.
A kind of radar digital signal processing device based on all solid state semicondctor storage array, including: high density all solid state half
Conductor memory array stores plate and main control computer；Described high density all solid state semicondctor storage array memory plane includes
FPGA and all solid state semicondctor storage array；Described FPGA includes: embedded software core processor, AXI bus, PCIe
Controller, all solid state semicondctor storage array controller and SRIO controller；Described main control computer comprise one two-way
Port, described embedded software core processor comprises a bidirectional port, and described AXI bus packet contains four bidirectional ports, described
PCIe controller comprises two bidirectional ports, and described all solid state semicondctor storage array controller comprises four bidirectional ports,
Described SRIO controller comprises two bidirectional ports, and described all solid state semicondctor storage array comprises a bidirectional port；
A main control computer bidirectional port by PCIe bus two-way electrical connection PCIe controller, four of AXI bus
Bidirectional port is electrically connected the bidirectional port of embedded software core processor, another bidirectional port of PCIe controller, Quan Gu
One bidirectional port of state semicondctor storage array controller, a bidirectional port of SRIO controller；All solid state quasiconductor
The other three bidirectional port of memory array controller is electrically connected one bidirectional port of residue of PCIe controller, complete
The bidirectional port of solid state semiconductor memory array, another bidirectional port of SRIO controller；
Described main control computer is used for obtaining control instruction and radar return, and by PCIe bus by described control instruction and
Radar return sends to PCIe controller；Described control instruction includes storage instruction, reads instruction, erasing instruction, initially
Change instruction and functional configuration operational order；
Described PCIe controller is used for receiving control instruction and radar return, and resolves the control instruction received,
Then the control instruction after being resolved by AXI bus is sent to embedded software core processor；Embedded software core processor is used for
Receive and perform the control instruction after resolving, then by PCIe controller to main control computer feedback operation state；To solve
Control instruction after analysis sends to all solid state semicondctor storage array controller；Radar is returned by the most described PCIe controller
Ripple is packed, and communicates with main control computer according to PCIe protocol；Described duty is that the control after resolving refers to
Order starts to perform, be carrying out or be finished；
Described all solid state semicondctor storage array controller is used for the control instruction after obtaining parsing and radar return, and to thunder
Reach echo to encode, it is thus achieved that the radar return after coding, and by Nand I/O interface, the radar return after coding is sent
Store to all solid state semicondctor storage array；Radar after the coding of storage is returned by all solid state semicondctor storage array
Ripple sends and is decoded to all solid state semicondctor storage array controller, obtains radar return, and is sent extremely by radar return
Main control computer；All solid state semicondctor storage array controller obtains all solid state quasiconductor according to the control instruction after resolving and deposits
Memory array and all solid state semicondctor storage array controller each duty, and by all solid state semicondctor storage array
Send to embedded software core processor with all solid state semicondctor storage array controller each duty, at Embedded Soft Core
Reason device is used for receive and pack all solid state semicondctor storage array and all solid state semicondctor storage array controller each work
Make state, then feed back all solid state semicondctor storage array by PCIe controller to main control computer and all solid state partly lead
Body memory array control unit each duty；Radar return after coding is sent to SRIO controller simultaneously；
Described SRIO controller radar return after obtaining control instruction and coding, and the control instruction obtained is sent
Resolve to embedded software core processor and perform, then feeding back current SRIO by AXI bus to PCIe controller and control
The duty of device processed；Radar return after coding is carried out half by SRIO link transmission to external equipment in kind imitative simultaneously
True or Radar Signal Processing.
Beneficial effects of the present invention: the present invention use field programmable gate array (Field Programmable Gate Array,
FPGA) as the main platform that realizes of the present invention, use PCIe bus control unit and main control computer communication, use SRIO
High speed data link and peripheral communications, it is achieved that under system administration control, solid-state memory highdensity to Large Copacity
Array carries out high-speed record, controlled broadcasting, data management and maintenance management function.
Accompanying drawing explanation
With detailed description of the invention, the present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 is the structural representation of apparatus of the present invention；
Fig. 2 is the function structure chart of all solid state semicondctor storage array controller；
Fig. 3 is the structural representation of PCIe bus control unit；
Fig. 4 is the structural representation of SRIO controller module；
Fig. 5 is memory plane host computer interface figure；
Fig. 6 is the sub-surface chart of memory plane record；
Fig. 7 is that memory plane plays back sub-surface chart；
Fig. 8 is that sub-surface chart derived by memory plane；
Fig. 9 is that memory plane imports sub-surface chart.
Detailed description of the invention
With reference to Fig. 1, for the structural representation of apparatus of the present invention；The one of the present invention is based on all solid state semicondctor storage array
Radar digital signal processing device in the repertoire that comprises realize in main control computer and FPGA respectively, described based on
The digital signal special purpose device of all solid state semicondctor storage array, including: all solid state semicondctor storage array of high density is deposited
Storage plate and main control computer；Described high density all solid state semicondctor storage array memory plane includes FPGA and all solid state partly leads
Body memory array；Described FPGA includes: embedded software core processor, AXI bus, PCIe controller, all solid state half
Conductor memory array control unit and SRIO controller；Described main control computer comprises a bidirectional port, described embedded
Soft-core processor comprises a bidirectional port, and described AXI bus packet contains four bidirectional ports, and described PCIe controller comprises
Two bidirectional ports, described all solid state semicondctor storage array controller comprises four bidirectional ports, and described SRIO controls
Device comprises two bidirectional ports, and described all solid state semicondctor storage array comprises a bidirectional port.
A main control computer bidirectional port by main control computer PCIe bus two-way electrical connection PCIe controller, AXI
Four bidirectional ports of bus be electrically connected the bidirectional port of embedded software core processor, PCIe controller another is two-way
Port, a bidirectional port of all solid state semicondctor storage array controller, a bidirectional port of SRIO controller；Entirely
The residue one that the other three bidirectional port of solid state semiconductor memory array control unit is electrically connected PCIe controller is double
To port, the bidirectional port of all solid state semicondctor storage array, another bidirectional port of SRIO controller.
Described main control computer is used for obtaining control instruction and radar return, and by PCIe bus by described control instruction and
Radar return sends to PCIe controller；Described control instruction includes storage instruction, reads instruction, erasing instruction, initially
Change instruction and functional configuration operational order.
Described PCIe controller is used for receiving control instruction and radar return, and resolves the control instruction received,
Then the control instruction after being resolved by AXI bus is sent to embedded software core processor；Embedded software core processor is used for
Receive and perform the control instruction after resolving, then by PCIe controller to main control computer feedback operation state；To solve
Control instruction after analysis sends to all solid state semicondctor storage array controller；Radar is returned by the most described PCIe controller
Ripple is packed, and communicates with main control computer according to PCIe protocol；Described duty is that the control after resolving refers to
Order starts to perform, be carrying out or be finished.
Described all solid state semicondctor storage array controller is used for the control instruction after obtaining parsing and radar return, and to thunder
Reach echo to encode, it is thus achieved that the radar return after coding, and by semiconductor memory access interface (Nand I/O interface)
Radar return after coding is sent extremely all solid state semicondctor storage array store；All solid state semicondctor storage array
Radar return after the coding of storage is sent and is decoded to all solid state semicondctor storage array controller, obtain radar and return
Ripple, and radar return is sent to main control computer；All solid state semicondctor storage array controller is according to the control after resolving
Instruction obtains all solid state semicondctor storage array and all solid state semicondctor storage array controller each duty, and will
All solid state semicondctor storage array and all solid state semicondctor storage array controller each duty send to embedded
Soft-core processor, embedded software core processor is used for receive and pack all solid state semicondctor storage array and all solid state quasiconductor
Memory array controller each duty, then feeds back all solid state quasiconductor by PCIe controller to main control computer
Memory array and all solid state semicondctor storage array controller each duty；Radar return after coding is sent out simultaneously
Deliver to SRIO controller；Wherein, all solid state semicondctor storage array comprises 96 Flash chip.
Described SRIO controller radar return after obtaining control instruction and coding, and the control instruction obtained is sent
Resolve to embedded software core processor and perform, then feeding back current SRIO by AXI bus to PCIe controller and control
The duty of device processed；Radar return after coding is carried out half by SRIO link transmission to external equipment in kind imitative simultaneously
True or Radar Signal Processing.
Specifically, apparatus of the present invention emphasis is for realizing high density all solid state semicondctor storage array memory plane antenna array control, embedding
Entering formula soft-core processor intarconnected cotrol and embedded software core processor is integrated, wherein embedded software core processor is the control of the present invention
Core processed, is responsible for state-maintenance and operation distribution, its organizational structure such as the FPGA internal frame diagram institute in Fig. 1 of whole device
Show, illustrate the purposes of each sub-function module in detail below:
(1) with reference to Fig. 2, for the function structure chart of all solid state semicondctor storage array controller；All solid state quasiconductor is deposited
The modular structure of memory array controller include all solid state semicondctor storage array memorizer, user logic, infrastructure and
State acquisition unit: described all solid state semicondctor storage array memorizer includes: storage control, user logic layer, base
Infrastructure, state acquisition unit；Described storage control includes: physical layer, Media Interface Connector layer, memory command layer, deposit
Storage link layer, memory maintenance and dispensing unit；Described physical layer is connected with described Media Interface Connector layer, described Media Interface Connector layer
Being connected with described memory command layer, described memory command layer is connected with described storage link layer, described storage link layer with
Described user applies logical layer to connect；Described user logic comprises four ports, connect respectively described user apply logical layer,
Described memory maintenance and dispensing unit, described infrastructure and described state acquisition unit.
Described physical layer is used for the control instruction after receiving parsing and radar return, and the control instruction after described parsing includes storage
Instruct, read instruction, erasing instruction, initialization directive and functional configuration operational order, and acquisition meets Nand Flash
The Double Data Rate synchronous sequence interface model physical layer data stream of technical manual definition, single times of rate synchronous sequential interface model thing
Recombination data stream after reason layer data stream or parsing, and radar return is adjusted through data edge synchronization, delay adjustment, sequential
Whole or fan-out, obtains meeting the time sequential routine of Nand Flash technology handbook definition, is then forwarded to all solid state quasiconductor and deposits
In memory array；Physical layer is additionally operable to meet Nand Flash technology handbook from Nand flash storage array received simultaneously
The sequential data stream of definition, heavily adopts then in turn through cache synchronization, sequential adjustment, delay adjustment, timing reconstruction, data
Sample or alignment of data operation, obtain meeting the Double Data Rate synchronous sequence interface model thing of Nand Flash technology handbook definition
Reason layer data stream or single times of rate synchronous sequential interface model physical layer data stream, and send to Media Interface Connector layer.
Described meet Nand Flash technology handbook for receive that physical layer sends over by local sequential interface (NIF)
The Double Data Rate synchronous sequence interface model physical layer data stream of definition or the single times of rate synchronous sequential interface model physics number of plies
According to stream, and store the Nand Flash manipulation of data stream after the decomposition that layer order sends over, and according to Nand Flash
The Double Data Rate synchronous sequence interface model physical layer data stream of technical manual definition or single times of rate synchronous sequential interface model
Carrying out successively resolving operation and recombination data stream, the recombination data stream after being resolved, then by the restructuring number after described parsing
Sent to physical layer by physical link interface (PIF) according to stream；Media Interface Connector layer is for by PIF interface thing simultaneously
The Double Data Rate synchronous sequence interface model physical layer data meeting the definition of Nand Flash technology handbook that reason layer sends over
Stream, single times of rate synchronous sequential interface model physical layer data stream or resolve after recombination data stream, and successively carry out resolve and
Reconstruct, obtains Nand Flash manipulation of data stream, then by local sequential interface (NIF) interface by described Nand Flash
Manipulation of data stream sends to memory command layer.
Described memory command layer is used for receiving described Nand Flash manipulation of data stream, and controls interface by order respectively
(CIF) obtain the respective operations instruction of Nand Flash manipulation of data stream from storage link layer, and connect by order control
Mouth (CIF) obtains the Frame meeting command interface sequential from storage link layer, resolves the most successively and decomposes,
Nand Flash manipulation of data stream after decomposition, then by local sequential interface (NIF) by the Nand Flash after described decomposition
Manipulation of data stream sends to Media Interface Connector layer；Simultaneous memory layer order is sended over by NIF interface Media Interface Connector layer
Decomposition after Nand Flash manipulation of data stream, after packing, obtain command interface sequential, and connect by order control
Mouth (CIF) sends to storing link layer.
Described storage link layer is used for receiving described command interface sequential, and controls interface (MIF) acquisition use by memorizer
The family application operational order that sends over of logical layer and respective operations data, and sequentially pass through tissue frame format, interpolation mistake control
After system coding, data traffic control, obtain meeting the Frame of command interface sequential, then according to deposit order to control interface
(CIF) the described Frame meeting command interface sequential is sent to memory command layer by timing requirements；Store link simultaneously
After layer sequentially passes through parsing frame format, decoding extraction to described command interface sequential, obtain decoded command interface sequential,
And by memorizer control interface (MIF), the transmission of described decoded command interface sequential is applied logical layer to user.
When described user logic is respectively used to obtain register configuration order, user logic work, required system clock and user patrol
Collect global reset signal, operational order data stream, the operational order of user logic desired data form, and current time thing
Reason layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and dispensing unit, infrastructure and
User applies logical layer each duty；Described operational order data stream packets containing storage instruction, read instruction, erasing instruction,
Initialization directive and functional configuration operational order each corresponding data stream.
Described memory maintenance and dispensing unit belong to independent functional unit in Memory Controller, for being connect by auxiliary
Mouth obtains the register configuration order that user logic sends over, and then resolves described register configuration order, after being resolved
Register configuration order, and will resolve after register configuration order be respectively sent to physical layer, Media Interface Connector layer, storage
Device layer order and storage link layer；Simultaneous memory safeguard and dispensing unit for read respectively physical layer, Media Interface Connector layer,
Memory command layer and the storage each self-corresponding register configuration order of link layer, and patrolled to user by satellite interface transmission
Volume.
Required system clock and user logic Global reset when described infrastructure obtains user logic work by system interface
Signal, when then working described user logic, required system clock and user logic global reset signal carry out phase-locked successively
Ring, clock fan-out and reset simultaneously operating, it is thus achieved that multiple work clocks and the work the most synchronize with multiple work clocks are multiple
Position signal, and multiple work clocks and the power on reset signal the most synchronize with multiple work clocks are respectively sent to physics
Layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and dispensing unit；Meanwhile, by multiple works
Make clock and the power on reset signal the most synchronize with multiple work clocks exports to user logic.
Described state acquisition unit is used for obtaining current time physical layer, Media Interface Connector layer, memory command layer, storage link
Layer, memory maintenance and dispensing unit, infrastructure and user apply logical layer each duty, and are connect by state
Mouthful by current time physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and dispensing unit,
Infrastructure and user apply logical layer each duty to send to user logic.
Described user applies logical layer to be the layering of user logic custom feature, for obtaining user logic by user interface
The operational order data stream sended over and the operational order of user logic desired data form, and be organized into memorizer control connect
Mouth (MIF) desired data form and operational format, then control interface (MIF) by memorizer and send to storing link layer；
The most described storage link layer obtains, from user logic, the operational order that Nand flash storage array can identify, described
The operational order that Nand flash storage array can identify includes that storage, reading, functional configuration operate, directly store visit
Ask (Direct Menory Access, DMA) write, DMA read, input and output able to programme (Program Input Output,
PIO) write, PIO reading, bulk erasure, simple erasing or initialization operation order, and described Nand Flash is deposited
The operational order that memory array can identify resolves successively and reconstructs, and obtains the operation life of user logic desired data form
Order, then by state interface, the operational order of described user logic desired data form is sent to user logic.
(2) with reference to Fig. 3, for the structural representation of PCIe bus control unit；PCIe controller comprises physical layer, link
Layer and transport layer, described transport layer comprises register file, direct memory access (Direct Memory Access, DMA)
Controller, power management；The IP that physical layer and link layer are provided by Xilinx respectively completes respective function；Transport layer carries
For two bidirectional ports, respectively user register port (User Register Port) and direct memory access (Direct
Memory Access, DMA) port, during the transmission of its Program input/output, user is accessed by user register port
During register file, the up arrow of this port the most corresponding and down arrow), register file is saturating by PCIe protocol
The bright memory area being mapped in main control computer is read out, and described access includes reading and writing；DMA port is controlled by DMA
Device processed completes high-volume data transmit-receive work；User data is entered PCIe bus control unit by DMA port, sequentially passes through DMA
Controller, link layer and physical layer are packaged according to PCIe protocol, obtain communication data, and send through PCIe bus
To main control computer；Main control computer issues communication data through PCIe bus simultaneously, through physical layer, link layer and biography
Defeated layer decapsulates successively, obtains user data, and is sent by DMA port by user data；Described power management is
Power management module, for powering for PCIe bus control unit.
(3) SRIO controller uses full mesh interconnection architecture, it is possible to realizes the high speed interconnection of arbitrary node, i.e. realizes between plate
At a high speed current, as shown in Figure 4, SRIO controller comprise user logic, direct memory access (Direct Memory Access,
DMA) controller, transport layer, link layer, physical layer, infrastructure；User logic transmits data to dma controller,
After dma controller encapsulates, sequentially pass through transport layer, link layer and physical layer by SRIO agreement again be packaged,
To the data finally encapsulated, and the data finally encapsulated are sent by SRIO link according to SRIO agreement；With
Time receive the data on SRIO link, and export after sequentially passing through physical layer, link layer and transport layer decapsulation and patrol to user
Volume.
(4) embedded software core processor is the control core of the present invention, is responsible for state-maintenance and the operation distribution of whole system,
Major function is to receive and parse through from the operational order of main control computer detection lug internal controller state total by PCIe
Alignment host computer reports, and instruction explanation function is responsible for the operational order of host computer is construed to memory array controller, SRIO
The register instruction of controller, is responsible for configuration feature depositor and fill state depositor.
Above-mentioned four big functional modules, with embedded software core processor as core, are connected by AXI bus, and Embedded Soft Core processes
PCIe controller, SRIO controller and all solid state semicondctor storage array controller are completed respectively by device by AXI bus
Function setting and state are read, as shown in the FPGA internal frame diagram of Fig. 1；Secondly, PCIe controller, SRIO controller and complete
There is special high speed interface between solid state semiconductor memory array control unit respectively, meet AXI_Stream standard,
Can control to carry out data at a high speed by embedded software core processor to transmit.
Wherein, above-mentioned embedded software core processor, PCIe bus control unit, all solid state semicondctor storage array controller and
SRIO controller all realizes inside onboard FPGA, by the I/O interface bus marco of Nand Flash onboard all solid state half
Conductor memory array realizes the storage of high-speed high capacity data；In apparatus of the present invention, all solid state semiconductor memory of high density
Array stores plate is attached with main control computer by PCIe bus, completes order control and data transmission (envelope importing
And derive), be respectively completed the data cube computation between other equipment by SRIO controller, and complete data record and
Playback；Other equipment described such as AD analog input card, signal processing board, and connected by VPX bus backplane.
In the global structure of the present invention that Fig. 1 shows, main control computer plays center control, data storage as host computer and returns
Deposit function.Fig. 5 is that memory plane controls surface chart；In Figure 5, label 1 indication part is fileinfo list, is used for showing
Show and record the class file information of storage device, including filename, file type, record time, file size, starting point
Location, end address and Data Source, described class file information is stored in main control computer by XML file, main control computer
Complete the communication between memory plane by the host interface protocol being defined in PCIe bus, it is achieved state self-inspection, record,
Play back, import, derive, delete, format and force to stop function, illustrate the effect of each function in detail below.
In Fig. 5, label 2 indication part is self-inspection, i.e. sends the self-inspection order in Host Interface Commands to memory plane, the completeest
Becoming detection the feedback testing result of memory plane duty, wherein said detection includes all solid state semicondctor storage array control
Device duty processed, the mode of operation of all solid state semicondctor storage array and current state, PCIe controller duty,
The link UNICOM state of SRIO controller and embedded software core processor running status.
In Fig. 5, label 3 indication part is record, i.e. sends the record order in Host Interface Commands, described note to memory plane
Record order includes record start address and record length, and Fig. 6 shows the sub-interface of writing task, and in this interface, user can join
Putting recording parameters, described recording parameters is log file name, record time, record start address, record length；Memory plane
After receiving order, embedded software core processor carries out resolve command, it is thus achieved that record length and record start address, to all solid state
Semicondctor storage array controller sends batch write operation, and sends reception operation to SRIO controller, and controls SRIO
All solid state semicondctor storage array controller is sent in record length and record start address by controller, complete record length and
Record start address is received and recorded in all solid state semicondctor storage array.
In Fig. 5, label 4 indication part is playback, i.e. playback command in memory plane transmission Host Interface Commands, described time
Putting order to include playing back initial address, playback length and flow-control option, Fig. 7 shows the playback sub-interface of work, on this boundary
In face, user can configure playback parameter, and described playback parameter is playback file name, playback duration, playback initial address, returns
Degree of lengthening, playback flow-control enable, play back flow control word etc.；After memory plane receives order, embedded software core processor
Scheduling SRIO controller and all solid state semicondctor storage array controller read number from all solid state semicondctor storage array
According to and sent toward other equipment by SRIO interface, other equipment described are AD analog input card, signal processing board, and lead to
Cross VPX bus backplane to connect；Wherein, described flow-control option belongs to source flow-control, is used for controlling to send data speed
Degree.
In Fig. 5, label 5 indication part is for deriving, and i.e. sends the export (swf) command in Host Interface Commands to memory plane, described in lead
Going out order to include deriving initial address and derived length, Fig. 8 shows the derivation sub-interface of work, and in this interface, user can join
Putting derived parameter, described derived parameter is export name, derivation time, derives initial address, derived length etc.；Storage
After plate receives order, embedded software core processor resolve command, it is thus achieved that derive initial address and derived length, total by AXI
Line traffic control all solid state semicondctor storage array controller is read, simultaneously by AXI bus to PCIe controller
Sending direct memory access order, PCIe controller receives direct memory access order and sends to main control computer, master control meter
Dma controller in PCI allocation e controller after the reception direct memory access order of calculation machine；Wherein, described configuration includes DMA
The packet length of controller, the bag number of dma controller and the address of dma controller；Finally, all solid state semiconductor memory
Array control unit read derivation initial address and derived length by by the dma controller of PCIe controller with dma mode
Send to main control computer.
In Fig. 5, label 6 indication part is for importing, and i.e. sends the importing order in Host Interface Commands to memory plane, described in lead
Entering order to include importing initial address and importing length, Fig. 9 shows the importing sub-interface of work, and in this interface, user can join
Putting importing parameter, described importing parameter is for importing filename, importing time, importing initial address, importing length etc..Board
Being sent to embedded software core processor by AXI bus after receiving importing order, embedded software core processor receives and imports order
And resolve, it is thus achieved that import initial address and import length, the then dma controller in PCI allocation e controller leading to
Know that main control computer, main control computer receive the dma controller imported after command response in PCI allocation e controller, then
Receive from main control computer and import initial address and import length and write all solid state semicondctor storage array；Wherein, institute
State configuration and include the packet length of dma controller, the bag number of dma controller and the address of dma controller.
In Fig. 5, label 7 indication part is for deleting, and i.e. sends the delete command in Host Interface Commands to memory plane, described in delete
Except order includes deleting initial address and deleting length, the respective file note during main control computer removes fileinfo list simultaneously
Record, after memory plane receives delete command, Embedded Soft Core processor scheduling all solid state semicondctor storage array controller also opens
Dynamic erasing operation, carries out physics erasing operation to described respective file record.
In Fig. 5, label 8 indication part is for formatting, and i.e. sends the formatting command in Host Interface Commands to memory plane, with
Time main control computer empty the All Files record in fileinfo list, after board receives formatting command, Embedded Soft Core
Processor scheduling all solid state semicondctor storage array controller also starts the erasing operation of full array, and then to all solid state quasiconductor
Memory array carries out physics erasing operation.
In Fig. 5, label 9 indication part is for forcing to stop, and i.e. stops for the pressure in memory plane transmission Host Interface Commands
Order, main control computer waits the state feedback between memory plane simultaneously；Board receives after pressure ceases and desist order, embedded software
Core processor is according to current operating state, to SRIO controller, PCIe controller and all solid state semicondctor storage array control
Device processed sends the emergent stopping of correspondence respectively and controls, and then memory plane enters Auto-Sensing Mode, and detection memory plane current state is the most anti-
Feed main control computer.
It addition, special purpose device of the present invention possesses following function:
(1) all solid state semiconductor array reinforces storage device: under conditions of outfield experiments and real system are run, collect
Original data stream at a high speed contributes to the analysis of phenomenon, technological adjustment and system mode and monitors, under most conditions, needs to add
Solid special equipment could tackle real system run mal-condition, include high temperature difference, high humility, strong motion, many dust
Deng weather and climate condition.The present invention uses all solid state semiconductor storage, belongs to reinforcement embedded device, possesses technical grade ring
Border conditional indicator, its intrinsic mechanical stability ensure that the reliable and stable operation under severe conditions of this equipment from design.
(2) record of high sDeed real-time digital signal and broadcasting: in embedded system for real-time signal processing at a high speed, original
The high bandwidth of data is proposed high requirement to gathering, storing and play；And the collection of initial data and playback are for being
System Performance Evaluation, system running state monitoring will be indispensable, and the present invention is achieved by multinomial technological means and embedding
Formula system realizes collection and the playback of high speed raw digital signal.
(3) for the random waveform signal digital signal broadcast source of HWIL simulation: the joint debugging work of large scale system often relates to
And many common joint debuggings of unit, extension set inspection, the performance of algorithm during the subsystem debugging, use of research and development early stage are commented
Estimate and be required for digital signal playback equipment to signal processing subsystem offer numeral stable, controlled, that simulate true front end
Signal, the present invention is that this type of HWIL simulation demand provides complete solution.It is specific that initial data, emulation construct
Wave data or other any data meeting particular demands can import this equipment beforehand through main control computer, and
Embedded system is play these data, it is achieved that the function of HWIL simulation validation test.
The present invention achieves integrated special high density high speed storing and broadcasting by techniques below means:
(1) the high density large-capacity semiconductor memory array controller using customization solves memorizer control problem: this
Bright employing separate semiconductor storage granule is as basic storage medium；Special control is not still had for large-scale storage array
Device IP provides use, and therefore, the present invention uses the memory array controller of customized development, completes high density arrays
The read and write access of high speed zero defect controls.
(2) PCIe bus is used to achieve the control with main control computer and data exchange: outside the present invention is as computer
Peripheral equipment accesses computer system by PCIe bus, and carry, in the PCIe bus of computer-internal, is calculated by master control
Machine realizes the order control to the present invention and data access operation, has bigger control motility and data interface bandwidth.
(3) SRIO data/address bus is used to achieve collection and the broadcasting of high speed original data stream: in embedded device,
The present invention and other embedded boards use SRIO controller to realize interconnection, and carry out the collection of high speed original data stream and broadcast
Put, belong to isomery full mesh interconnection architecture, it is provided that the system interconnection that high speed is controlled.
(4) source flow control technique and storage dedicated frame design is used to achieve controlled speed and play: present invention employs
The initial data of storage is packaged by special storage dedicated frame structure, improves memory reliability, and coordinates the present invention's
Source flow control technique, it is possible to realize the output effective data rate of controllable variable, meets rear end and receives system to different numbers
According to the requirement of rate, improve system adaptation performance.
(5) use embedded software core processor to achieve system remote upgrade as master controller and demand changes: the present invention
Use SOC(system on a chip) as onboard master controller, between embedded software core processor with onboard peripheral hardware, use AXI bus to be connected,
Ensure that the high bandwidth of connection, the motility of control and expansion easily, the external interface that embedded software core processor is abundant
It is the characteristic that the invention provides remote system upgrade with the characteristic of software programmable.
Obviously, those skilled in the art the present invention can be carried out various change and modification without deviating from the present invention spirit and
Scope；So, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof,
Then the present invention is also intended to comprise these change and modification.
Claims (8)
1. a radar digital signal processing device based on all solid state semicondctor storage array, it is characterised in that including:
High density all solid state semicondctor storage array memory plane and main control computer；Described high density all solid state semiconductor memory battle array
Row memory plane includes FPGA and all solid state semicondctor storage array；Described FPGA includes: embedded software core processor, AXI
Bus, PCIe controller, all solid state semicondctor storage array controller and SRIO controller；Described main control computer bag
Containing a bidirectional port, described embedded software core processor comprises a bidirectional port, and described AXI bus packet is two-way containing four
Port, described PCIe controller comprises two bidirectional ports, and described all solid state semicondctor storage array controller comprises four
Individual bidirectional port, described SRIO controller comprises two bidirectional ports, and described all solid state semicondctor storage array comprises one
Individual bidirectional port；
A main control computer bidirectional port by PCIe bus two-way electrical connection PCIe controller, four of AXI bus
Bidirectional port is electrically connected the bidirectional port of embedded software core processor, another bidirectional port of PCIe controller, Quan Gu
One bidirectional port of state semicondctor storage array controller, a bidirectional port of SRIO controller；All solid state quasiconductor
The other three bidirectional port of memory array controller is electrically connected one bidirectional port of residue of PCIe controller, complete
The bidirectional port of solid state semiconductor memory array, another bidirectional port of SRIO controller；
Described main control computer is used for obtaining control instruction and radar return, and by PCIe bus by described control instruction and
Radar return sends to PCIe controller；Described control instruction includes storage instruction, reads instruction, erasing instruction, initially
Change instruction and functional configuration operational order；
Described PCIe controller is used for receiving control instruction and radar return, and resolves the control instruction received,
Then the control instruction after being resolved by AXI bus is sent to embedded software core processor；Embedded software core processor is used for
Receive and perform the control instruction after resolving, then by PCIe controller to main control computer feedback operation state；To solve
Control instruction after analysis sends to all solid state semicondctor storage array controller；Radar is returned by the most described PCIe controller
Ripple is packed, and communicates with main control computer according to PCIe protocol；Described duty is that the control after resolving refers to
Order starts to perform, be carrying out or be finished；
Described all solid state semicondctor storage array controller is used for the control instruction after obtaining parsing and radar return, and to thunder
Reach echo to encode, it is thus achieved that the radar return after coding, and the radar return transmission after coding is deposited to all solid state quasiconductor
Memory array stores；Radar return after the coding of storage is sent to all solid state half by all solid state semicondctor storage array
Conductor memory array control unit is decoded, and obtains radar return, and sends radar return to main control computer；Quan Gu
It is solid with complete that state semicondctor storage array controller obtains all solid state semicondctor storage array according to the control instruction after resolving
State semicondctor storage array controller each duty, and by all solid state semicondctor storage array and all solid state quasiconductor
Memory array controller each duty sends to embedded software core processor, and embedded software core processor is for receiving also
Pack all solid state semicondctor storage array and all solid state semicondctor storage array controller each duty, then pass through
PCIe controller feeds back all solid state semicondctor storage array to main control computer and all solid state semicondctor storage array controls
Device each duty；Radar return after coding is sent to SRIO controller simultaneously；
Described SRIO controller radar return after obtaining control instruction and coding, and the control instruction obtained is sent
Resolve to embedded software core processor and perform, then feeding back current SRIO by AXI bus to PCIe controller and control
The duty of device processed；Radar return after coding is carried out half by SRIO link transmission to external equipment in kind imitative simultaneously
True or Radar Signal Processing.
A kind of radar digital signal processing device based on all solid state semicondctor storage array,
It is characterized in that, the modular structure of described all solid state semicondctor storage array controller includes all solid state semiconductor memory battle array
Row memorizer, user logic, infrastructure and state acquisition unit: described all solid state semicondctor storage array memorizer bag
Include: storage control, user logic layer, infrastructure, state acquisition unit；Described storage control includes: physical layer,
Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and dispensing unit；Described physical layer with given an account of
Matter interface layer connects, and described Media Interface Connector layer is connected with described memory command layer, described memory command layer and described storage
Link layer connects, and described storage link layer applies logical layer to be connected with described user；Described user logic comprises four ports,
Connecting described user respectively applies logical layer, described memory maintenance and dispensing unit, described infrastructure and described state to adopt
Collection unit.
A kind of radar digital signal processing device based on all solid state semicondctor storage array,
It is characterized in that, described physical layer is used for the control instruction after receiving parsing and radar return, the control instruction after described parsing
Including storage instruction, read instruction, erasing instruction, initialization directive and functional configuration operational order, and obtain Double Data Rate
Weight after synchronous sequence interface model physical layer data stream, single times of rate synchronous sequential interface model physical layer data stream or parsing
Group data stream, and radar return is carried out data edge synchronization, postpones adjustment, sequential adjustment or fan-out, obtain the time sequential routine,
It is then forwarded in Nand flash storage array；Physical layer is additionally operable to from Nand flash storage array received simultaneously
Sequential data stream, adjusts then in turn through cache synchronization, sequential, postpones adjustment, timing reconstruction, data resampling or number
According to alignment operation, obtain Double Data Rate synchronous sequence interface model physical layer data stream or single times of rate synchronous sequential interface model
Physical layer data stream, and send to Media Interface Connector layer；
Described Media Interface Connector layer is for receiving the Double Data Rate synchronous sequence interface model physical layer data that physical layer sends over
Stream or single times of rate synchronous sequential interface model physical layer data stream, and after obtaining the storage decomposition that sends over of layer order
Nand Flash manipulation of data stream, and according to Double Data Rate synchronous sequence interface model physical layer data stream or single times of rate synchronous
Sequential interface model carries out resolving operation and recombination data stream successively, and the recombination data stream after being resolved, then by described solution
Recombination data stream after analysis sends to physical layer；The Double Data Rate that Media Interface Connector layer sends over for receiving physical layer simultaneously is same
Restructuring after step sequential interface model physical layer data stream, single times of rate synchronous sequential interface model physical layer data stream or parsing
Data stream, and resolve successively and reconstruct, obtain Nand Flash manipulation of data stream, then by described Nand Flash
Manipulation of data stream sends to memory command layer.
A kind of radar digital signal processing device based on all solid state semicondctor storage array,
It is characterized in that, described memory command layer is used for receiving described Nand Flash manipulation of data stream, and respectively from storage chains
Road floor obtains the corresponding instruction of Nand Flash manipulation of data stream, and meets command interface sequential from storage link layer acquisition
Frame, resolve the most successively and decompose, the Nand Flash manipulation of data stream after being decomposed, then by described
Nand Flash manipulation of data stream after decomposition sends to Media Interface Connector layer；Simultaneous memory layer order is used for receiving medium and connects
Nand Flash manipulation of data stream after the decomposition that mouth layer sends over, obtains command interface sequential after packing, and will
Described command interface sequential sends to storing link layer；
Described storage link layer is used for receiving described command interface sequential, and obtains the operation that user applies logical layer to send over
Order and respective operations data, and sequentially pass through tissue frame format, add error control coding, data traffic control after, obtain
To meeting the Frame of command interface sequential, then according to deposit command interface timing requirements by the described command interface sequential that meets
Frame sends to memory command layer；Simultaneously storage link layer described command interface sequential is sequentially passed through parsing frame format,
After decoding is extracted, obtain decoded command interface sequential, and should to user by the transmission of described decoded command interface sequential
Use logical layer.
A kind of radar digital signal processing device based on all solid state semicondctor storage array,
It is characterized in that, required system clock when described user logic is respectively used to obtain register configuration order, user logic work
With user logic global reset signal, operational order and data stream, the operational order of user logic desired data form, and
Current time physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and dispensing unit, base
Infrastructure and user apply logical layer each duty；Described operational order comprises storage instruction, reads instruction, erasing
Instruction, initialization directive and functional configuration operational order；
Described memory maintenance and dispensing unit, for obtaining the register configuration order that user logic sends over, then resolve
Described register configuration order, the register configuration order after being resolved, and the register configuration order after resolving is respectively
Send to physical layer, Media Interface Connector layer, memory command layer and storage link layer；Simultaneous memory is safeguarded and dispensing unit is used
In reading physical layer, Media Interface Connector layer, memory command layer and the storage each self-corresponding register configuration order of link layer respectively,
And send to user logic；
Required system clock and user logic global reset signal when described infrastructure obtains user logic work, then to institute
State user logic work time required system clock and user logic global reset signal carry out successively phaselocked loop, clock fan-out and
Reset simultaneously operating, it is thus achieved that multiple work clocks and the power on reset signal the most synchronize with multiple work clocks, and by multiple
Work clock and the power on reset signal the most synchronize with multiple work clocks are respectively sent to physical layer, Media Interface Connector layer, deposit
Reservoir layer order, storage link layer, memory maintenance and dispensing unit；Meanwhile, by multiple work clocks and with multiple work
The power on reset signal that clock synchronizes respectively exports to user logic.
A kind of radar digital signal processing device based on all solid state semicondctor storage array,
It is characterized in that, described state acquisition unit be used for obtaining current time physical layer, Media Interface Connector layer, memory command layer,
Storage link layer, memory maintenance and dispensing unit, infrastructure and user apply logical layer each duty, and lead to
Cross state interface by current time physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and
Dispensing unit, infrastructure and user apply logical layer each duty to send to user logic；
Described user applies logical layer to be used for obtaining operational order and the data stream that user logic sends over, and is organized into storage
Device controls interface desired data form and operational format, is then forwarded to store link layer；The most described storage link layer from
Family logic obtains the operational order that Nand flash storage array can identify, described Nand flash storage array institute
The operational order that can identify includes that storage, reading, functional configuration operation, direct memory access write, direct memory access are read
Take, input and output able to programme write, input and output reading able to programme, bulk erasure, simple erasing or initialization operation order,
And the operational order that can identify described Nand flash storage array resolves successively and reconstructs, obtain user and patrol
Collect the operational order of desired data form, then the operational order transmission of described user logic desired data form is patrolled to user
Volume.
A kind of radar digital signal processing device based on all solid state semicondctor storage array,
It is characterized in that, described PCIe controller comprises physical layer, link layer and transport layer, and described transport layer comprises depositor literary composition
Part, direct memory access controller, power management；The IP that physical layer and link layer are provided by Xilinx respectively completes respectively
From function；Transport layer provides two bidirectional ports, respectively user register port and direct memory access port, its intermediate range
During the transmission of sequence input/output, when user accesses register file by user register port, register file passes through PCIe
The memory area that protocol transparent is mapped in main control computer is read out；Direct memory access port is complete by dma controller
Become high-volume data transmit-receive work；User data is entered PCIe bus control unit by direct memory access port, sequentially passes through
Dma controller, link layer and physical layer are packaged according to PCIe protocol, obtain communication data, and through PCIe bus
Send to main control computer；Main control computer issues communication data through PCIe bus simultaneously, through physical layer, link layer
Decapsulate successively with transport layer, obtain user data, and user data is sent by direct memory access port；Institute
Stating power management is power management module, for powering for PCIe bus control unit.
A kind of radar digital signal processing device based on all solid state semicondctor storage array,
It is characterized in that, described SRIO controller comprise user logic, direct memory access controller, transport layer, link layer,
Physical layer, infrastructure；User logic transmits data to dma controller, encapsulates it through direct memory access controller
After sequentially pass through transport layer, link layer and physical layer by SRIO agreement again and be packaged, the data finally encapsulated,
And the data finally encapsulated are sent by SRIO link according to SRIO agreement；Receive the number on SRIO link simultaneously
According to, and sequentially pass through physical layer, link layer and transport layer decapsulation after export to user logic.
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