CN105741879B - A kind of simulation intelligent electric energy meter memory test plate system and its test method - Google Patents
A kind of simulation intelligent electric energy meter memory test plate system and its test method Download PDFInfo
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Abstract
The present invention relates to a kind of analog memory test board system and its test method based on intelligent electric meter software reliability test platform.The system includes detection computer, analog memory test board, unit under test, interface A and interface C；The detection computer carries out information exchange by interface A and analog memory test board；The unit under test carries out information exchange by interface C and analog memory test board.This method includes that the communication protocol between the analog storage chip read-write operation and ARM chip and memory analog board FPGA for analyzing memory analog board FPGA runs five steps of program after synthesis on analog memory test board.Analog memory test board provided by the invention is combined with ARM and FPGA, with the function of FPGA hardware logic simulation actual storage chip, solves the problem of ARM and storage chip module information interactive speed is slower can not simulate state needed for failure etc. is tested.
Description
Technical field
The present invention relates to a kind of test board and its test methods, in particular to a kind of to be based on intelligent electric meter software reliability
Test platform simulates intelligent electric energy meter memory test plate system and its test method.
Background technique
Intelligent electric meter is the intelligent terminal of smart grid, it is not traditional electric energy meter, and intelligent electric meter removes
Have other than the function of measuring of traditional electric energy meter basic electricity consumption, in order to adapt to also having using it for smart grid and new energy
Have power information storage, two-way a variety of rate function of measuring, user terminal control function, plurality of data transmission modes bi-directional data
The intelligentized function such as communication function, anti-stealing electricity function, intelligent electric meter represent following energy-conserving intelligent power grid end user's intelligence
The developing direction of terminal can be changed.With increasingly developed, demand of the countries in the world for intelligent user terminal of smart grid
Increasingly increase, according to statistics, in the five-year, construction with smart grid in countries in the world, number of the intelligent electric meter in whole world installation
Amount will be up to 200,000,000.Equally, the intelligent electric meter in China, with the progress of the strong smart grid construction of country, as user terminal
Demand can also increase by a wide margin, it is conservative, it is expected that market will have 1.7 hundred million or so demands.U.S. government is upgrading
In the appropriation of national power grid, some will be caused in future to 13% American family (18,000,000 family family) for 3 years
Intelligent electric meter can be loaded onto.In Europe, Italian and Sweden has completed the deployment of advanced measurement basis facility, by all common electricity
Table is changed to intelligent electric meter.France, Spain, Germany and Britain are estimated to complete also to complete intelligent electric meter in coming 10 years
It popularizes in an all-round way and applies.
Traditional intelligent electric meter is to be paid dues to supplement intellective IC card with money and input in ammeter by user, and ammeter could power, table
Middle electricity automatically switches off after being finished, and novel intelligent electric meter realizes network power purchase at present with perfection, just as prepaid mobile phone recharging one
Sample is simple.The background of intelligent electric meter industry be perhaps investor when thinking deeply this problem firstly the need of assurance: with China
After proposing building national smart grid concept, directly matched intelligent electric meter starts to become focus of attention therewith.Intelligence electricity
Energy table is a kind of electric energy meter, and relatively previous common electric energy meter, in addition to having basic function of measuring, intelligent electric energy meter is
Electronic power meter has high reliability, high safety grade and big storage with hardware clock and complete communication interface
The features such as capacity, complies fully with the requirement of Chinese future development " energy conservation and environmental protection ".
As more and more intelligent electric meters are put into the operation of scene, intelligent electric meter reliability of operation is most important,
Therefore it needs to detect intelligent electric meter before to ensure its reliability of operation.
Demand for intelligent electric meter software reliability test scheme to storage chip module, upper computer software needs pass through
ARM carries out relevant operations, the actual storage chip such as information configuration and failure write-in to storage chip module and is difficult to realize this
A little operations；And during the test, ARM will simultaneously interact host computer test software and tested ammeter storage chip
Operation, wherein the information exchange speed of the relatively entire test platform of the software processing speed run is too slow, it is possible to cause to test
As a result there is the problems such as deviation, therefore, it is necessary to use other modes simulation intelligent electric energy meter storage chip module practical to replace
Storage chip.
Summary of the invention
In view of the deficiencies of the prior art, it is flat based on intelligent electric meter software reliability test that the object of the present invention is to provide one kind
Platform analog memory test board system and its test method, analog memory test board of the present invention are combined with ARM and FPGA, with
The function of FPGA hardware logic simulation actual storage chip, solves ARM and storage chip module information interactive speed is slower, can not
The problem of state needed for simulation failure etc. is tested.
The purpose of the present invention is adopt the following technical solutions realization:
The present invention provides a kind of simulation intelligent electric energy meter memory test plate system, it is improved in that the test
Plate system is based on intelligent electric meter software reliability test platform, including detection computer 1, analog memory test board 2, quilt
Survey unit 3, interface A 4 and interface C 6；The detection computer 1 carries out letter by interface A 4 and analog memory test board 2
Breath interaction；The unit under test 3 carries out information exchange by interface C 6 and analog memory test board 2.
Further, the analog memory test board 2 includes the memory simulation that information exchange is carried out by interface B 5
Monitor board ARM7 and memory analog board FPGA8；
The memory analog board FPGA8 include i2c bus kernel 9, arbitration selecting module 10, three bus modules 11,
SRAM storage control module 12, sram chip 13, modification memory content module 14, read operation instruction module 15 and register
Module 16；The arbitration selecting module 10 carries out information exchange with i2c bus kernel 9；The I2C bus kernel 9, three bus moulds
Block 11, SRAM storage control module 12 and sram chip 13 successively carry out information exchange；The modification memory content module 14
It is connect respectively with SRAM storage control module 12 and register module 16；The read operation instruction module 15 respectively with SRAM core
Piece 13 and register module 16 connect；The SRAM storage control module 12 and register module 16 carry out information exchange.
Further, during testing progress, memory simulation monitoring plate ARM7 receives detection by interface A4 and calculates
The instruction that machine 1 is sent, while information exchange is carried out by interface B5 and memory analog board FPGA8, it completes detection computer 1 and wants
The operation asked；Unit under test 3 carries out information exchange by interface C6 and memory analog board FPGA8, simulates ammeter to EEPROM
Read-write operation；The memory simulation monitoring plate ARM7 is ARM chip；
The i2c bus kernel 9 meets EEPROM communication protocol.
Further, the interface A4 is the interface detected between computer 1 and analog memory test board 2, use with
Too network interface, analog memory test board 2 are used as server-side；The interface C6 is analog memory test board 2 and unit under test 3
Between interface, meet i2c bus protocol.
Further, analog memory test board utilizes 13 mould of memory analog board FPGA8 hardware logic and sram chip
Intend unit under test 3 to the read-write operation of the storage chip of intelligent electric energy meter, by ARM chip with memory analog board FPGA8's
Information exchange carries out special operation: the different intelligent ammeter according to used in test, the simulation to memory analog board FPGA8
Storage chip information is configured, configuration information include device address, amount of memory, memory capacity, whether paging and page
Size；Read the operational order and record mode of operation of storage chip module；The failure of simulation intelligent electric energy meter storage chip is write
Enter operation, meets the needs of intelligent electric meter software reliability test detection of platform out of memory.
Further, the special operation includes: the instruction that ARM chip receives host computer transmission by Ethernet, to read
It writes timing and memory analog board FPGA8 carries out information exchange, send an instruction to the deposit of memory analog board FPGA8 simulation
In device, according still further to memory analog board FPGA8 internal logic parse content of registers, realize memory chip information configuration,
Read operation instruction and failure write operation.
The present invention also provides a kind of test method for simulating intelligent electric energy meter memory test plate system, improvements exist
In the method includes the following steps:
Step 1: the analog storage chip read-write operation and ARM chip and memory mould of analysis memory analog board FPGA
Communication protocol between quasi- plate FPGA；
Step 2: being read and write between data and ARM chip and intelligent electric energy meter storage chip according to memory analog board FPGA
Communication protocol, design meet the sequential logic of agreement；
Step 3: according to the sequential logic of design, being based on Quartus ii software, realize storage chip using VHDL language
The hardware logic that the storage chip of kernel and intelligent electric energy meter and ARM chip interact；
Step 4: according to the demand of intelligent electric meter software reliability test platform, designing intelligent electric energy meter storage chip kernel
The hardware logic of periphery distributes pin, and integrates to the program that VHDL language is write；
Step 5: running the program after synthesis on analog memory test board, intelligent electric meter is tested, and to mould
The storage chip of quasi- intelligent electric energy meter is verified.
Compared with the immediate prior art, the excellent effect of the present invention is that:
Analog memory test board of the present invention is combined with ARM and FPGA, with FPGA hardware logic simulation actual storage core
The function of piece, solves ARM and storage chip module information interactive speed is slower, can not simulate asking for state needed for failure etc. is tested
Topic, specifically:
1) present invention can solve ARM to host computer test software and tested ammeter storage chip while interact operation
When, the software speed of service is slower, the problem of may cause test errors；
2) present invention can be directed to different ammeter types, believe storage chip type, storage chip quantity, memory capacity etc.
Breath is configured；
3) testing requirement of the invention that intelligent electric meter software reliability test platform can be directed to, the instruction of execution read operation,
The operations such as storage failure write-in.
Detailed description of the invention
Fig. 1 is the system construction drawing for the analog memory test board that ARM and FPGA provided by the invention are combined；
Wherein: 1- detects computer, and 2- analog memory test board, 3- unit under test, 4- interface A, 5- interface B, 6- connect
Mouthful C, 7- memory simulation monitoring plate ARM, 8- memory analog board FPGA, 9- meet in the i2c bus of EEPROM communication protocol
Core, 10- arbitrate selecting module, and tri- bus module of 11-, 12-SRAM storage control module, 13-SRAM, 14- are modified in memory
Molar block, 15- read operation instruction module, 16- register module.
Specific embodiment
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing.
The present invention provides a kind of analog memory test board system, and structure chart is as shown in Figure 1, include that 1- detection calculates
Machine, 2- analog memory test board, 3- unit under test, 4- interface A, 5- interface B, 6- interface C.Analog memory test board includes
7- memory simulation monitoring plate ARM and 8- memory analog board FPGA；Interface A 4 be detection computer and memory analog board it
Between interface, using Ethernet interface, memory analog board is as server-side；Interface B 5 is memory analog board internal control
Interface between MCU and peripheral hardware FPGA；Interface C 6 is the interface between memory analog board and unit under test, meets i2c bus
Agreement.During test carries out, memory simulation monitoring plate ARM 7 receives the instruction that detection computer is sent by interface A 4,
Information exchange is carried out by interface B5 and memory analog board FPGA 8 simultaneously, completes the operation that detection computer requires.It is tested
Unit 3 carries out information exchange, read-write operation of the simulation ammeter to EEPROM to memory analog board FPGA 8 by interface C 6.
It include the i2c bus kernel that 9- meets EEPROM communication protocol, 10- arbitration choosing inside analog memory test board 2
Module is selected, tri- bus module of 11-, 12-SRAM storage control module, 13-SRAM, 14- modify memory content module, 15- reading
Extract operation instruction module, 16- register module and 7-ARM, that is, memory simulation monitoring plate ARM.Its working principles are as follows:
Read-write operation of the simulation ammeter to EEPROM: pass through i2C bus kernel 9 (most analogs 8) receives ammeter MCU
Serial clock signal, serial data signal and the write-protect signal of transmission, i2C bus kernel 9 is according to i2C bus protocol will receive
Data-signal resolve to address, data and read-write control signal；It arbitrates selecting module 10 and receives i2What c bus kernel 9 was sent
Request signal carries out piece choosing, enables corresponding i2The information such as data, address, Read-write Catrol are sent to three always by c bus kernel 9
Wire module 11；The information such as the data received, address, Read-write Catrol are passed through SRAM storage control module 12 by three bus modules 11
Realize the read-write operation to SRAM13.
Read operation instruction: read operation instruction module 15 is by operational order control submodule and operational order FIFO submodule
Block two parts form, data, address in operational order control submodule reading SRMA memory control module 12.Read-write Catrol
Etc. information, and be sent to operational order FIFO submodule at a complete operational order according to certain combination of protocols.Due to
FIFO meets the sortord of first in, first out, therefore operational order can be stored in operational order FIFO by the sequencing for executing operation
Submodule.When register module 16 receives the signal of read operation instruction of memory simulation monitoring plate ARM7 transmission, i.e.,
The operational order in operational order FIFO submodule can be read, retransmit to memory simulation monitoring plate ARM7, realize and read behaviour
Make the function of instructing.
Storage failure write-in: memory simulation monitoring plate ARM7 sends modification memory content and instructs to register module
16, register module 16 presses the received instruction of protocol analysis, by data, address, writes in the modified memories of information such as control
Molar block 14 is sent to three bus modules 11, then SRAM13 is written in the data of modification by SRAM storage control module 12 and is corresponded to
Address.During executing storage failure write-in, the function that the address is written by i2c kernel need to be shielded, in order to avoid ARM7
The data cover that the data of modification are written by ammeter MCU.Meanwhile memory simulation monitoring plate ARM7 can pass through register module 16
Data, address, reading control information are sent to three bus modules 11, it is corresponding to read SRAM13 by SRAM storage control module 12
The data of address, to examine whether failure is successfully written.
Storage chip information configuration: the configuration storage chip information command that register module 16 sends ARM7 by agreement into
Row parsing, retransmits into i2c kernel 9, specific implementation is as follows: the i2c kernel 9 of enabled different number can configure storage
Number of chips；Modify beginning of the page address, can configure different page size and whether paging；Storage address digit is modified, can configure
Different memory capacity；I2c kernel 9 is write direct after being parsed by register module 16 in device address, can configure different storage cores
The device address of piece.
Analog memory test board, which removes, can use FPGA hardware logic and sram chip simulation unit under test to storage core
The read-write operation of piece module, can also by the information exchange of memory simulation monitoring plate ARM and memory analog board FPGA, into
The certain special operations of row: the difference ammeter according to used in test configures analog memory chip information, configuration information
Mainly include device address, amount of memory, memory capacity, whether paging, page size etc.；Storage chip module can be read
Operational order records mode of operation；The operation of analog memory failure of chip write-in meets test platform detection out of memory
Demand.
Certain special operations refer to: memory simulation monitoring plate ARM receives the instruction that host computer is sent by Ethernet,
Information exchange is carried out with certain read-write sequence and memory analog board FPGA, sends an instruction to memory analog board FPGA mould
In quasi- register, content of registers is parsed according still further to memory analog board FPGA internal logic, realizes the letter of memory chip
Breath configuration, read operation instruction and failure write operation.
The present invention also provides a kind of based on intelligent electric meter software reliability test platform simulation memory test plate system
Test method, comprising the following steps:
Step 1: the analog storage chip read-write operation and ARM chip and memory mould of analysis memory analog board FPGA
Communication protocol between quasi- plate FPGA；
Step 2: data and memory simulation monitoring plate ARM and storage chip mould are read and write according to memory analog board FPGA
Communication protocol between block, design meet the sequential logic of agreement；
Step 3: according to the sequential logic of design, being based on Quartus ii software, realize storage chip using VHDL language
The hardware logic that kernel and storage chip module and memory simulation monitoring plate ARM are interacted；
Step 4: according to the demand of intelligent electric meter software reliability test platform, designing the hardware of storage chip kernel periphery
Logic, e.g., the modules such as arbitration selection, read operation instruction, modification memory content, memory control.Reasonable distribution pin, and
The program program that VHDL language is write is integrated；
Step 5: running the program after synthesis on memory analog test board, electric energy meter is tested, to the program
The storage chip module of simulation is verified.
Simulation intelligent electric energy meter memory test plate system provided by the invention mainly includes analogue unit and monitoring unit,
Wherein, analogue unit mainly utilizes FPGA simulation intelligent electric energy meter and tests the information interactive process of chip, and monitoring unit utilizes
ARM is monitored and is controlled to the above process.Meet EEPROM communication in FPGA hardware logic main analog storage chip module
The i of agreement2C bus kernel, arbitrates selecting module, three bus modules, and SRAM storage control module modifies memory content mould
Block, read operation instruction module, register module.The storage chip module of FPGA simulation is except completion actual storage chip and is tested
, can also be in conjunction with ARM outside the information exchange of unit, realize some special operations: ARM receives host computer by Ethernet interface
Instruction, and carry out information exchange by certain agreement and storage chip module, realize storage chip information configuration, failure write-in and read
The functions such as extract operation instruction, to meet the specific requirements of intelligent electric meter testing scheme.
Finally it should be noted that: the above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, to the greatest extent
Invention is explained in detail referring to above-described embodiment for pipe, and those of ordinary skill in the art still can be to this hair
Bright specific embodiment is modified or replaced equivalently, these without departing from spirit and scope of the invention any modification or
Equivalent replacement, within the scope of the claims of the invention pending application.
Claims (6)
1. a kind of simulation intelligent electric energy meter memory test plate system, which is characterized in that the test board system is based on intelligence
Ammeter software reliability test platform, including detect computer (1), analog memory test board (2), unit under test (3), connect
Mouth A (4) and interface C (6)；The detection computer (1) carries out information friendship by interface A (4) and analog memory test board (2)
Mutually；The unit under test (3) carries out information exchange by interface C (6) and analog memory test board (2)；
The analog memory test board (2) includes the memory simulation monitoring plate ARM that information exchange is carried out by interface B (5)
(7) and memory analog board FPGA (8)；
The memory analog board FPGA (8) includes i2C bus kernel (9), arbitration selecting module (10), three bus modules (11),
SRAM storage control module (12), sram chip (13), modification memory content module (14), read operation instruction module (15)
With register module (16)；The arbitration selecting module (10) and i2C bus kernel (9) carries out information exchange；The I2C bus
Kernel (9), three bus modules (11), SRAM storage control module (12) and sram chip (13) successively carry out information exchange；Institute
Modification memory content module (14) is stated to connect with SRAM storage control module (12) and register module (16) respectively；The reading
Extract operation instruction module (15) is connect with sram chip (13) and register module (16) respectively；The SRAM storage control module
(12) and register module (16) carries out information exchange.
2. memory test plate system as described in claim 1, which is characterized in that during testing progress, memory mould
Quasi- monitor board ARM (7) receive the instruction that detection computer (1) is sent by interface A (4), while passing through interface B (5) and storage
Device analog board FPGA (8) carries out information exchange, completes the operation that detection computer (1) requires；Unit under test 3 passes through interface C (6)
Information exchange, read-write operation of the simulation ammeter to EEPROM are carried out with memory analog board FPGA (8)；The memory simulation prison
Controlling plate ARM (7) is ARM chip；
The i2C bus kernel (9) meets EEPROM communication protocol.
3. memory test plate system as described in claim 1, which is characterized in that the interface A (4) is detection computer
(1) interface between analog memory test board (2), using Ethernet interface, analog memory test board (2) is as service
End；The interface C (6) is the interface between analog memory test board (2) and unit under test (3), meets i2C bus protocol.
4. memory test plate system as described in claim 1, which is characterized in that analog memory test board (2) is utilized and deposited
Reservoir analog board FPGA (8) hardware logic and sram chip (13) simulate unit under test (3) to the storage chip of intelligent electric energy meter
Read-write operation, pass through the information exchange of ARM chip and memory analog board FPGA (8), carry out special operation；According in test
The different intelligent ammeter used configures the analog storage chip information of memory analog board FPGA (8), configuration information packet
Include device address, amount of memory, memory capacity, whether paging and page size；Read the operational order of storage chip module
With record mode of operation；The failure write operation for simulating intelligent electric energy meter storage chip meets the survey of intelligent electric meter software reliability
Try the demand of detection of platform out of memory.
5. memory test plate system as claimed in claim 4, which is characterized in that the special operation includes: that ARM chip is logical
It crosses Ethernet and receives the instruction that host computer is sent, information exchange is carried out with read-write sequence and memory analog board FPGA (8), will be referred to
Order is sent in the register of memory analog board FPGA (8) simulation, according still further to memory analog board FPGA (8) internal logic solution
Content of registers is analysed, realizes information configuration, read operation instruction and the failure write operation of memory chip.
6. a kind of test side of simulation intelligent electric energy meter memory test plate system according to any one of claims 1 to 5
Method, which is characterized in that the method includes the following steps:
Step 1: the analog storage chip read-write operation and ARM chip and memory analog board of analysis memory analog board FPGA
Communication protocol between FPGA；
Step 2: the communication between data and ARM chip and intelligent electric energy meter storage chip is read and write according to memory analog board FPGA
Agreement, design meet the sequential logic of agreement；
Step 3: according to the sequential logic of design, being based on Quartus II software, realize storage chip kernel using VHDL language
And the hardware logic that the storage chip of intelligent electric energy meter and ARM chip interact；
Step 4: according to the demand of intelligent electric meter software reliability test platform, designing intelligent electric energy meter storage chip kernel periphery
Hardware logic, distribute pin, and the program that VHDL language is write integrated；
Step 5: running the program after synthesis on analog memory test board, intelligent electric meter is tested, and to simulation
The storage chip of intelligent electric energy meter is verified.
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| CN108231132B (en) * | 2017-12-28 | 2020-12-25 | 北京兆易创新科技股份有限公司 | NAND flash memory verification device and verification system |
| CN109818790B (en) * | 2019-01-25 | 2021-10-08 | 上海创景信息科技有限公司 | Hardware real-time simulation multi-channel multi-type communication protocol chip system, method and medium |
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| CN104200846A (en) * | 2014-07-23 | 2014-12-10 | 北京空间机电研究所 | Embedded-type PROM test system and achieving method |
| CN104166119A (en) * | 2014-09-01 | 2014-11-26 | 国家电网公司 | Intelligent ammeter program stability test system based on error injection |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220094551A1 (en) * | 2020-09-21 | 2022-03-24 | Jason Burt | Verification of the reliability of software and devices against assertions and guarantees |
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