CN105741879A - Analog intelligent electric meter storage test board system and test method therefor - Google Patents
Analog intelligent electric meter storage test board system and test method therefor Download PDFInfo
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Abstract
The invention relates to an analog storage test board system based on an intelligent electric meter software reliability test platform, and a test method therefor. The system comprises a detection computer, an analog storage test board, a tested unit, an interface A and an interface C, wherein the detection computer performs information interaction with the analog storage test board through the interface A; and the tested unit performs information interaction with the analog storage test board through the interface C. The test method comprises five steps of analyzing a read-write operation of an analog storage chip of a storage analog board FPGA, analyzing the communication protocol between an ARM chip and the storage analog board FPGA, executing the comprehensive program on the analog storage test board, and the like. The analog storage test board provided by the invention is combined with the ARM and the FPGA; the function of the actual storage chip is simulated through the FPGA hardware logic; and therefore, the problem of relatively low information interaction speed between the ARM and the storage chip module, and the problem that the states, such as failure and the like, required by test cannot be simulated are solved.
Description
Technical field
The present invention relates to a kind of test board and method of testing thereof, in particular to one based on intelligent electric meter software reliability test platform simulation intelligent electric energy meter memory test plate system and method for testing thereof.
Background technology
Intelligent electric meter is the intelligent terminal of intelligent grid, it has not been traditional electric energy meter, intelligent electric meter is except possessing the function of measuring of traditional electric energy meter basic electricity amount, in order to adapt to intelligent grid and new forms of energy use it also to have power information storage, two-way multiple rate function of measuring, user side control the intelligentized functions such as function, the bidirectional data communication function of plurality of data transmission modes, anti-stealing electricity function, intelligent electric meter represents the developing direction of energy-conserving intelligent electrical network end user's intelligent terminal in future.Growing along with intelligent grid, countries in the world also increase day by day for the demand of intelligent user terminal, and according to statistics, at the five-year, along with intelligent grid is in the construction of countries in the world, the quantity that intelligent electric meter is installed in the whole world will be up to 200,000,000.Equally, in China, along with the progress that national strong intelligent grid is built, the demand as the intelligent electric meter of user side also can increase by a wide margin, conservative it is expected that the market demand that will have about 1.7 hundred million.U.S. government is in the appropriation of upgrading this country electrical network, is specifically designed to regard to some and within 3 years, will cause the American family (18,000,000 family family) of 13% can load onto intelligent electric meter in future.In Europe, Italy and Sweden are complete the deployment of advanced measurement basis facility, and all ordinary electric meter are replaced by intelligent electric meter.France, Spain, Germany and Britain estimate to complete also will complete all-round popularization and the application of intelligent electric meter in coming 10 years.
Traditional intelligent electric meter is to be paid dues by user intellective IC card is supplemented with money and inputs in ammeter, and ammeter could be powered, and in table, electricity automatically switches off after being finished, and novel intelligent electric meter realizes network power purchase with perfection at present, simple just as prepaid mobile phone recharging.The background of intelligent electric meter industry is perhaps investor when thinking deeply this problem firstly the need of holding: after proposing building national intelligent grid concept along with China, intelligent electric meter directly supporting with it starts to become the focus of concern.Intelligent electric energy meter is a kind of electric energy meter, relatively conventional common electric energy meter, except possessing basic function of measuring, intelligent electric energy meter is electronic power meter, with hardware clock and complete communication interface, there is the features such as high reliability, high safety grade and large storage capacity, comply fully with the requirement of China's future development " energy-conserving and environment-protective ".
Along with increasing intelligent electric meter is put in on-the-spot operation, intelligent electric meter reliability of operation is most important, it is therefore desirable to detect intelligent electric meter before use to guarantee its reliability of operation.
For the intelligent electric meter software reliability test scheme demand to storage chip module, upper computer software requires over ARM and storage chip module carries out the associative operation such as information configuration and fault write, and actual storage chip is difficult to these operations；And in test process, ARM host computer is tested software simultaneously and tested ammeter storage chip interacts operation, the information interactive speed of the relatively whole test platform of software processes speed wherein run is too slow, it is likely to result in test result and the problems such as deviation occur, accordingly, it would be desirable to adopt other modes to simulate intelligent electric energy meter storage chip module to replace the storage chip of reality.
Summary of the invention
For the deficiencies in the prior art, it is an object of the invention to provide a kind of based on intelligent electric meter software reliability test platform simulation memory test plate system and method for testing thereof, analog memory test board of the present invention combines with ARM and FPGA, function with FPGA hardware logical simulation actual storage chip, solve ARM slower with storage chip module information interactive speed, it is impossible to the problem of the required states of test such as simulation inefficacy.
It is an object of the invention to adopt following technical proposals to realize:
The present invention provides a kind of simulation intelligent electric energy meter memory test plate system, it thes improvement is that, described test board system is based on intelligent electric meter software reliability test platform, including detection computer 1, analog memory test board 2, unit under test 3, interface A4 and interface C6；It is mutual that described detection computer 1 carries out information by interface A4 and analog memory test board 2；It is mutual that described unit under test 3 carries out information by interface C6 and analog memory test board 2.
Further, described analog memory test board 2 includes carrying out information mutual memorizer simulation monitoring plate ARM7 and memorizer analog board FPGA8 by interface B5；
Described memorizer analog board FPGA8 includes i2c bus kernel 9, arbitration selection module 10, three bus module 11, SRAM storage control module 12, sram chip 13, amendment memory content module 14, read operation instruction module 15 and register module 16；It is mutual that described arbitration selects module 10 and i2c bus kernel 9 to carry out information；It is mutual that described I2C bus kernel 9, three bus module 11, SRAM storage control module 12 and sram chip 13 are sequentially carried out information；Described amendment memory content module 14 is connected with SRAM storage control module 12 and register module 16 respectively；Described read operation instruction module 15 is connected with sram chip 13 and register module 16 respectively；It is mutual that described SRAM storage control module 12 and register module 16 carry out information.
Further, carrying out in process in test, memorizer simulation monitoring plate ARM7 receives, by interface A4, the instruction that detection computer 1 sends, and carries out information by interface B5 and memorizer analog board FPGA8 mutual simultaneously, completes the operation that detection computer 1 requires；It is mutual that unit under test 3 carries out information by interface C6 and memorizer analog board FPGA8, simulates the ammeter read-write operation to EEPROM；Described memorizer simulation monitoring plate ARM7 is ARM chip；
Described i2c bus kernel 9 meets EEPROM communication protocol.
Further, described interface A4 is the interface between detection computer 1 and analog memory test board 2, adopts Ethernet interface, and analog memory test board 2 is as service end；Described interface C6 is the interface between analog memory test board 2 and unit under test 3, meets i2c bus protocol.
Further, analog memory test board utilizes memorizer analog board FPGA8 hardware logic and sram chip 13 to simulate the unit under test 3 read-write operation to the storage chip of intelligent electric energy meter, mutual by the information of ARM chip Yu memorizer analog board FPGA8, carry out special operational: according to the different intelligent ammeter used in test, the analog storage chip information of memorizer analog board FPGA8 is configured, and configuration information includes device address, amount of memory, memory span, whether paging and page size；Read operational order and the record mode of operation of storage chip module；The fault write operation of simulation intelligent electric energy meter storage chip, meets the demand of intelligent electric meter software reliability test detection of platform out of memory.
Further, described special operational includes: ARM chip receives, by Ethernet, the instruction that host computer sends, information is carried out mutual with read-write sequence and memorizer analog board FPGA8, send an instruction in the depositor of memorizer analog board FPGA8 simulation, content of registers is resolved, it is achieved the information configuration of memory chip, read operation instruction and fault write operation according still further to memorizer analog board FPGA8 internal logic.
The present invention also provides for a kind of method of testing simulating intelligent electric energy meter memory test plate system, and it thes improvement is that, described method comprises the steps:
Step 1: the analog storage chip read-write operation of analysis memorizer analog board FPGA and the communication protocol between ARM chip and memorizer analog board FPGA；
Step 2: read and write the communication protocol between data and ARM chip and intelligent electric energy meter storage chip according to memorizer analog board FPGA, design meets the sequential logic of agreement；
Step 3: the sequential logic according to design, based on Quartusii software, utilizes VHDL language to realize the hardware logic that the storage chip of storage chip kernel and intelligent electric energy meter interacts with ARM chip；
Step 4: the demand according to intelligent electric meter software reliability test platform, the hardware logic that design intelligent electric energy meter storage chip kernel is peripheral, distributes pin, and the program that VHDL language is write carries out comprehensively；
Step 5: run the program after comprehensively on analog memory test board, intelligent electric meter is tested, and the storage chip of the intelligent electric energy meter of simulation is verified.
Compared with immediate prior art, the excellent effect of the present invention is:
Analog memory test board of the present invention combines with ARM and FPGA, with the function of FPGA hardware logical simulation actual storage chip, solves ARM slower with storage chip module information interactive speed, it is impossible to the problem of the required states of test such as simulation inefficacy, particularly as follows:
1) present invention can solve ARM and host computer be tested software and tested ammeter storage chip when interacting operation simultaneously, and running software speed is slower, it is possible to the problem causing test errors；
2) information such as storage chip type, storage chip quantity, memory capacity for different ammeter types, can be configured by the present invention；
3) present invention for the testing requirement of intelligent electric meter software reliability test platform, can perform the operation such as read operation instruction, storage failure write.
Accompanying drawing explanation
Fig. 1 is the system construction drawing of ARM and the FPGA provided by the invention analog memory test board combined；
Wherein: 1-detects computer, 2-analog memory test board, 3-unit under test, 4-interface A, 5-interface B, 6-interface C, 7-memorizer simulation monitoring plate ARM, 8-memorizer analog board FPGA, 9-meet the i2c bus kernel of EEPROM communication protocol, 10-arbitration selects module, 11-tri-bus module, 12-SRAM storage control module, 13-SRAM, 14-revises memory content module, 15-read operation instruction module, 16-register module.
Detailed description of the invention
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
The present invention provides a kind of analog memory test board system, and its structure chart detects computer, 2-analog memory test board, 3-unit under test, 4-interface A, 5-interface B, 6-interface C as it is shown in figure 1, include 1-.Analog memory test board includes 7-memorizer simulation monitoring plate ARM and 8-memorizer analog board FPGA；Interface A4 is the interface between detection computer and memory analog board, adopts Ethernet interface, and memorizer analog board is as service end；Interface B5 is the interface between memory analog board internal control MCU and peripheral hardware FPGA；Interface C6 is the interface between memorizer analog board and unit under test, meets i2c bus protocol.Test carries out in process, and memorizer simulation monitoring plate ARM7 receives, by interface A4, the instruction that detection computer sends, and carries out information by interface B5 and memorizer analog board FPGA8 mutual simultaneously, completes the operation of detection computer requirement.Memorizer analog board FPGA8 is carried out information alternately by interface C6 by unit under test 3, simulates the ammeter read-write operation to EEPROM.
Analog memory test board 2 inside includes 9-and meets the i2c bus kernel of EEPROM communication protocol, 10-arbitration selects module, 11-tri-bus module, 12-SRAM storage control module, 13-SRAM, 14-revises memory content module, 15-read operation instruction module, 16-register module and 7-ARM and memorizer simulation monitoring plate ARM.Its operation principle is as follows:
The simulation ammeter read-write operation to EEPROM: pass through i2C bus kernel 9 (can simulate at most 8) receives ammeter MCU serial clock signal, serial data signal and write-protect signal, the i sent2C bus kernel 9 is according to i2The data signal of reception is resolved to address, data and read-write control signal by c bus protocol；Arbitration selects module 10 to receive i2The request signal that c bus kernel 9 sends, carries out chip select, enables corresponding i2The information such as data, address, Read-write Catrol are sent to three bus modules 11 by c bus kernel 9；The information such as the data received, address, Read-write Catrol are realized the read-write operation to SRAM13 by SRAM storage control module 12 by three bus modules 11.
Read operation instruction: read operation instruction module 15 is controlled submodule by operational order and operational order FIFO submodule two parts form, operational order controls submodule and reads the data in SRMA memory control module 12, address.The information such as Read-write Catrol, and according to certain protocol groups one complete operational order of synthesis, send to operational order FIFO submodule.Owing to FIFO meets the sortord of FIFO, therefore operational order can be stored in operational order FIFO submodule by the sequencing performing operation.When register module 16 receives the signal of the memorizer simulation monitoring plate ARM7 read operation instruction sent, get final product the operational order in read operation instruction FIFO submodule, retransmit to memorizer simulation monitoring plate ARM7, it is achieved the function of read operation instruction.
Storage failure writes: memorizer simulation monitoring plate ARM7 sends amendment memory content instruction to register module 16, register module 16 presses the instruction that protocol analysis receives, by data, address, write the modified memory content module 14 of the information such as control and send to three bus modules 11, will the address corresponding for data write SRAM13 of amendment again through SRAM storage control module 12.In the process performing storage failure write, the function being write this address by i2c kernel need to be shielded, in order to avoid the data cover that the data of ARM7 amendment are write by ammeter MCU.Meanwhile, memorizer simulation monitoring plate ARM7 can pass through register module 16 and data, address, reading are controlled information and sent to three bus modules 11, reads the data of SRAM13 corresponding address through SRAM storage control module 12, to check whether fault is successfully written.
Storage chip information configuration: the configuration storage chip information command that ARM7 is sent by register module 16 by agreement resolves, and retransmits to i2c kernel 9, and specific implementation is as follows: enable the i2c kernel 9 of varying number, configurable storage chip quantity；Amendment address, beginning of the page, configurable different page size and whether paging；Amendment storage address figure place, configurable different memory capacity；Write direct after being resolved by register module 16 i2c kernel 9 in device address, the device address of configurable different storage chips.
Analog memory test board is except utilizing FPGA hardware logic and the sram chip simulation unit under test read-write operation to storage chip module, the information that can also pass through memorizer simulation monitoring plate ARM and memorizer analog board FPGA is mutual, carry out some special operational: according to the different ammeters used in test, analog memory chip information is configured, and configuration information mainly includes device address, amount of memory, memory span, whether paging, page size etc.；Can read the operational order of storage chip module, record mode of operation；The operation of analog memory failure of chip write, meets the demand of test platform detection out of memory.
Some special operational refers to: memorizer simulation monitoring plate ARM receives, by Ethernet, the instruction that host computer sends, information is carried out mutual with certain read-write sequence and memorizer analog board FPGA, send an instruction in the depositor of memorizer analog board FPGA simulation, content of registers is resolved, it is achieved the information configuration of memory chip, read operation instruction and fault write operation according still further to memorizer analog board FPGA internal logic.
The present invention also provides for a kind of method of testing based on intelligent electric meter software reliability test platform simulation memory test plate system, comprises the following steps:
Step 1: the analog storage chip read-write operation of analysis memorizer analog board FPGA and the communication protocol between ARM chip and memorizer analog board FPGA；
Step 2: read and write the communication protocol of data and memorizer simulation monitoring plate ARM and storage chip intermodule according to memorizer analog board FPGA, design meets the sequential logic of agreement；
Step 3: the sequential logic according to design, based on Quartusii software, utilizes VHDL language to realize storage chip kernel and storage chip module and the memorizer simulation monitoring plate ARM hardware logic interacted；
Step 4: the demand according to intelligent electric meter software reliability test platform, the hardware logic that design storage chip kernel is peripheral, e.g., arbitration selection, read operation instruction, the amendment module such as memory content, memorizer control.Reasonable distribution pin, and the program program that VHDL language is write carries out comprehensively；
Step 5: run the program after comprehensively on memorizer analog test board, electric energy meter is tested, the storage chip module of program simulation is verified.
Simulation intelligent electric energy meter memory test plate system provided by the invention mainly includes analogue unit and monitoring unit, wherein, analogue unit mainly utilizes FPGA to simulate the information interactive process of intelligent electric energy meter and test chip, and monitoring unit utilizes ARM said process is monitored and controls.The i of EEPROM communication protocol is met in FPGA hardware logic main analog storage chip module2C bus kernel, arbitration selects module, three bus modules, SRAM storage control module, revises memory content module, read operation instruction module, register module.The storage chip module of FPGA simulation except the information completing actual storage chip and unit under test alternately except, can also be combined with ARM, realize some special operationals: ARM receives host computer instruction by Ethernet interface, and it is mutual to carry out information by certain agreement and storage chip module, realize the functions such as storage chip information configuration, fault write and read operation instruction, to meet the real needs of intelligent electric meter testing scheme.
Finally should be noted that: above example is only in order to illustrate that technical scheme is not intended to limit; although the present invention being described in detail with reference to above-described embodiment; the specific embodiment of the present invention still can be modified or equivalent replacement by those of ordinary skill in the field; these are without departing from any amendment of spirit and scope of the invention or equivalent replace, within the claims of the present invention all awaited the reply in application.
Claims (7)
1. a simulation intelligent electric energy meter memory test plate system, it is characterized in that, described test board system is based on intelligent electric meter software reliability test platform, including detection computer (1), analog memory test board (2), unit under test (3), interface A (4) and interface C (6)；It is mutual that described detection computer (1) carries out information by interface A (4) and analog memory test board (2)；It is mutual that described unit under test (3) carries out information by interface C (6) and analog memory test board (2).
2. memory test plate system as claimed in claim 1, it is characterized in that, described analog memory test board (2) includes being undertaken mutual memorizer simulation monitoring plate ARM (7) of information and memorizer analog board FPGA (8) by interface B (5)；
Described memorizer analog board FPGA (8) includes i2C bus kernel (9), arbitration select module (10), three bus modules (11), SRAM storage control module (12), sram chip (13), amendment memory content module (14), read operation instruction module (15) and register module (16)；Described arbitration selects module (10) and i2It is mutual that c bus kernel (9) carries out information；Described I2It is mutual that C bus kernel (9), three bus modules (11), SRAM storage control module (12) and sram chip (13) are sequentially carried out information；Described amendment memory content module (14) is connected with SRAM storage control module (12) and register module (16) respectively；Described read operation instruction module (15) is connected with sram chip (13) and register module (16) respectively；It is mutual that described SRAM storage control module (12) and register module (16) carry out information.
3. memory test plate system as claimed in claim 2, it is characterized in that, carry out in process in test, memorizer simulation monitoring plate ARM (7) receives, by interface A (4), the instruction that detection computer (1) sends, carry out information alternately by interface B (5) with memorizer analog board FPGA (8) simultaneously, complete the operation that detection computer (1) requires；Unit under test 3 carries out information alternately by interface C (6) with memorizer analog board FPGA (8), simulates the ammeter read-write operation to EEPROM；Described memorizer simulation monitoring plate ARM (7) is ARM chip；
Described i2C bus kernel (9) meets EEPROM communication protocol.
4. memory test plate system as claimed in claim 1, it is characterized in that, described interface A (4) is the interface between detection computer (1) and analog memory test board (2), adopting Ethernet interface, analog memory test board (2) is as service end；Described interface C (6) is the interface between analog memory test board (2) and unit under test (3), meets i2C bus protocol.
5. memory test plate system as claimed in claim 2, it is characterized in that, analog memory test board utilizes memorizer analog board FPGA (8) hardware logic and the sram chip (13) simulation unit under test (3) read-write operation to the storage chip of intelligent electric energy meter, mutual by the information of ARM chip Yu memorizer analog board FPGA (8), carry out special operational: according to the different intelligent ammeter used in test, the analog storage chip information of memorizer analog board FPGA (8) is configured, configuration information includes device address, amount of memory, memory span, whether paging and page size；Read operational order and the record mode of operation of storage chip module；The fault write operation of simulation intelligent electric energy meter storage chip, meets the demand of intelligent electric meter software reliability test detection of platform out of memory.
6. memory test plate system as claimed in claim 5, it is characterized in that, described special operational includes: ARM chip receives, by Ethernet, the instruction that host computer sends, information is carried out mutual with read-write sequence and memorizer analog board FPGA (8), send an instruction in the depositor that memorizer analog board FPGA (8) is simulated, content of registers is resolved, it is achieved the information configuration of memory chip, read operation instruction and fault write operation according still further to memorizer analog board FPGA (8) internal logic.
7. the method for testing of the simulation intelligent electric energy meter memory test plate system as according to any one of claim 1-6, it is characterised in that described method comprises the steps:
Step 1: the analog storage chip read-write operation of analysis memorizer analog board FPGA and the communication protocol between ARM chip and memorizer analog board FPGA；
Step 2: read and write the communication protocol between data and ARM chip and intelligent electric energy meter storage chip according to memorizer analog board FPGA, design meets the sequential logic of agreement；
Step 3: the sequential logic according to design, based on Quartusii software, utilizes VHDL language to realize the hardware logic that the storage chip of storage chip kernel and intelligent electric energy meter interacts with ARM chip；
Step 4: the demand according to intelligent electric meter software reliability test platform, the hardware logic that design intelligent electric energy meter storage chip kernel is peripheral, distributes pin, and the program that VHDL language is write carries out comprehensively；
Step 5: run the program after comprehensively on analog memory test board, intelligent electric meter is tested, and the storage chip of the intelligent electric energy meter of simulation is verified.
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| CN112834819B (en) * | 2021-01-04 | 2024-04-02 | 杭州万高科技股份有限公司 | Digital signal processing device and method for electric energy metering chip |
| CN113820649A (en) * | 2021-08-31 | 2021-12-21 | 中国电力科学研究院有限公司 | Method and device for testing service life reliability of electric energy meter firmware |
| CN113820649B (en) * | 2021-08-31 | 2024-05-17 | 中国电力科学研究院有限公司 | Method and device for testing service life reliability of firmware of electric energy meter |
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Effective date of registration: 20170111 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant after: State Power Networks Co Applicant after: China Electric Power Research Institute Applicant after: State Grid Zhejiang Electric Power Company Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant before: State Power Networks Co Applicant before: China Electric Power Research Institute |
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