CN106897033A - A kind of high speed acquisition tape deck based on FPGA and solid state hard disc - Google Patents
A kind of high speed acquisition tape deck based on FPGA and solid state hard disc Download PDFInfo
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- CN106897033A CN106897033A CN201710305976.3A CN201710305976A CN106897033A CN 106897033 A CN106897033 A CN 106897033A CN 201710305976 A CN201710305976 A CN 201710305976A CN 106897033 A CN106897033 A CN 106897033A
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- 238000003491 array Methods 0.000 claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 230000002123 temporal effect Effects 0.000 claims description 7
- 238000004458 analytical method Methods 0.000 claims description 3
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- 238000013500 data storage Methods 0.000 claims description 3
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- 230000035939 shock Effects 0.000 claims description 3
- 238000007726 management method Methods 0.000 description 3
- 239000005441 aurora Substances 0.000 description 2
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- 230000004913 activation Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1678—Details of memory controller using bus width
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0623—Securing storage systems in relation to content
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0689—Disk arrays, e.g. RAID, JBOD
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
The present invention provides a kind of high speed acquisition tape deck based on FPGA and solid state hard disc, including：FPGA main control units, data input cell, data outputting unit, monitoring interface unit, auxiliary signal input block, data buffer storage unit, SATA3 solid state hard discs array, PMU.SATA3 solid state hard disc arrays are controlled to realize that high-speed data acquisition is recorded by using FPGA, record data bandwidth is high, reaches as high as 4GB/s, and memory capacity easily extends；Simple structure, supports various data inputs outputs such as Camera Link, SDI, optical-fibre channel and Ethernet protocol, is particularly well-suited to embedded occasion to the requirement more than the high bandwidth of data record, low-power consumption, small volume and kind of interface.
Description
Technical field
The present invention relates to data acquiring and recording field, more particularly to a kind of high speed acquisition note based on FPGA and solid state hard disc
Recording device.
Background technology
With the resolution ratio and precision more and more higher of the imageing sensor such as visible ray, infrared, the speed of its output data interface
Rate also more and more higher, single sensor output speed is up to GB/s, the also more and more higher of the requirement to data acquisition recording device.Mesh
Before, the data acquisition recording device of main flow is realized using the computer platform of standard, mainly by high performance cpu motherboard, number
Constituted according to capture card, disk array, the operating system of operation standard wherein on cpu motherboard, such as Linux, Windows operation system
System, realizes the control and the management to disk array to input and output stream.Within the system, data are defeated by capture card
Enter, in the internal memory by the CPU board of computer-internal bus transfer to computer, file system management of the data in operating system
Under, interaction is multiple in internal memory, is finally written in disk array.Due to computer-internal bus and the complexity text of operating system
Part system operatio, can cause record data bandwidth to be difficult to break through the bandwidth of 1GB/s.Due to using high performance CPU, the work(of system
Consumption and volume are difficult to reduce, it is impossible to realize embedded system to low-power consumption and the requirement of small size.
The content of the invention
Present invention aim to address available data acquisition and recording device record data bandwidth it is low, embedded system cannot be realized
System is to low-power consumption and the problem of the requirement of small size.To achieve the above object, FPGA and solid-state are based on the invention provides one kind
The high speed acquisition tape deck of hard disk, including：FPGA main control units, data input cell, data outputting unit, monitoring interface list
Unit, auxiliary signal input block, data buffer storage unit, SATA3 solid state hard discs array, PMU.
The FPGA main control units, connection data input cell, data outputting unit, monitoring interface unit, auxiliary signal
Input block, data buffer storage unit, SATA3 solid state hard discs array, PMU, the operation for coordinating unit,
And according to the order of monitoring interface unit, realize input data, the Comprehensive Control of output data and storage.
The data input cell, one end connection FPGA main control units, the Data Input Interface outside the connection of one end is used for
Data to outside input carry out protocol analysis and level conversion.
The data outputting unit, one end connection FPGA main control units, the data output interface outside the connection of one end is used for
Realize the agreement and level conversion of data output.
The monitoring interface unit, one end connection FPGA main control units, monitoring and control unit outside the connection of one end are used
In to the operation realization control based on FPGA and the high speed acquisition tape deck of solid state hard disc and condition monitoring.
The auxiliary signal input block, one end connection FPGA main control units, the Data Input Interface outside the connection of one end,
Input for realizing trigger signal, power down protection signal, temporal information, positional information.
The data buffer storage unit, connects FPGA main control units, realizes the data buffer storage to input and output data, data
Buffer unit is formed by multi-disc DDR3SDRAM the parallel combineds.
The SATA3 solid state hard discs array, connects FPGA main control units, and multiple SATA3 solid state hard discs constitute SATA3 solid-states
Hard disk array, realizes the data storage of high bandwidth.
The PMU, connection FPGA main control units, data input cell, data outputting unit, monitoring interface
Unit, auxiliary signal input block, data buffer storage unit, SATA3 solid state hard disc arrays, for being powered to unit.
The record data bandwidth of the high speed acquisition tape deck based on FPGA and solid state hard disc reaches as high as 4GB/s.
The FPGA main control units support hardware encryption algorithm, and on the premise of data record bandwidth is not reduced, it is right to realize
The encryption of record data.
The data input cell supports the data input of Camera Link, SDI, optical-fibre channel and Ethernet protocol.
The data outputting unit supports the data output of Camera Link, SDI, optical-fibre channel and Ethernet protocol.
The monitoring interface unit supports the data input output of RS422, RS232 and Ethernet protocol.
The auxiliary signal input block supports power down protection, i.e., the high speed acquisition record dress based on FPGA and solid state hard disc
Put in course of normal operation, when running into improper power down, auxiliary signal input block sends power-off signal and gives FPGA main control units,
Be written to the data of caching in SATA3 solid state hard disc arrays by FPGA main control units, the number in protection SATA3 solid state hard disc arrays
According to without damage.
The auxiliary signal input block is supported to add longitude, latitude, temporal information in data recording process.
Using connector connection is reinforced between described SATA3 solid state hard discs array and FPGA main control units, with locking
Function, anti-vibration, shock resistance.
As shown from the above technical solution, the present invention controls SATA3 solid state hard disc arrays to realize high speed number by using FPGA
It is different types of using Camera Link, SDI, optical-fibre channel and Ethernet protocol etc. according to application demand according to acquisition and recording
Data input, input data is directly entered data buffer storage unit by interface conversion, under the control of FPGA main control units, write-in
In SATA3 solid state hard disc arrays, output data also supports the differences such as Camera Link, SDI, optical-fibre channel and Ethernet protocol
Species is exported, and is had the advantages that：
1. record data bandwidth is high, reaches as high as 4GB/s, and memory capacity easily extends.
2. simple structure, the inputoutput data species of support is more, is particularly well-suited to embedded occasion to data record
Requirement more than high bandwidth, low-power consumption, small volume and kind of interface.
Below by drawings and Examples, technical scheme is described in further detail.
Brief description of the drawings
The high speed acquisition recording device structure block diagram based on FPGA and solid state hard disc that Fig. 1 is provided for the present invention.
Specific embodiment
As shown in figure 1, being the high speed acquisition recording device structure block diagram based on FPGA and solid state hard disc for providing of the invention.
The high speed acquisition tape deck 10 based on FPGA and solid state hard disc, including：FPGA main control units 101, data input cell
102nd, data outputting unit 103, monitoring interface unit 104, auxiliary signal input block 105, data buffer storage unit 106, SATA3
Solid state hard disc array 107, PMU 108.
Wherein, FPGA main control units 101, connection data input cell 102, data outputting unit 103, monitoring interface unit
104th, auxiliary signal input block 105, data buffer storage unit 106, SATA3 solid state hard discs array 107, PMU 108,
Operation for coordinating unit, and according to monitoring interface unit 104 order, realize input data, output data it is comprehensive
Close control and store.
Data input cell 102, one end connects FPGA main control units 101, and the Data Input Interface outside the connection of one end is used
Protocol analysis and level conversion are carried out in the data to outside input.
Data outputting unit 103, one end connects FPGA main control units 101, and the data output interface outside the connection of one end is used
In the agreement and level conversion of realizing data output.
Monitoring interface unit 104, one end connects FPGA main control units 101, monitoring and control unit outside the connection of one end,
For realizing control and condition monitoring to the operation based on FPGA and the high speed acquisition tape deck 10 of solid state hard disc.
Auxiliary signal input block 105, one end connects FPGA main control units 101, and the data input outside the connection of one end connects
Mouthful, the input for realizing trigger signal, power down protection signal, temporal information, positional information.
Data buffer storage unit 106, connection FPGA main control units 101 realize the data buffer storage to input and output data, number
Formed by multi-disc DDR3SDRAM the parallel combineds according to buffer unit.
SATA3 solid state hard discs array 107, connection FPGA main control units 101, multiple SATA3 solid state hard discs composition SATA3 consolidate
State hard disk array 107, realizes the data storage of high bandwidth.SATA3 solid state hard discs array 107 uses the SSD of standard SATA interface
Solid state hard disc, SSD solid state hard discs have read or write speed high, readwrite performance stabilization the features such as, the lasting write-in bandwidth of single disc reaches
460MB/s, persistently reads bandwidth and reaches 540MB/s, can meet the record application demand of lasting high-speed data-flow.
108 PMUs, connection FPGA main control units 101, data input cell 102, data outputting unit 103,
Monitoring interface unit 104, auxiliary signal input block 105, data buffer storage unit 106, SATA3 solid state hard discs array 107, are used for
Powered to unit.
Two kinds of mode of operations of the record support of high speed acquisition tape deck 10 and playback based on FPGA and solid state hard disc, in note
Under record pattern, FPGA main control units 101 receive the data of data input cell 102, and are cached to data according to certain form
In buffer unit 106, after the data of caching reach certain threshold value, data parallel is write SATA3 and consolidated by FPGA master controls list 101
In state hard disk array 107；In the playback mode, FPGA main control units 101 read the data in SATA3 solid state hard discs array 107
In getting data buffer storage unit 106, and according to certain form, by data output.
The record data bandwidth of the high speed acquisition tape deck 10 based on FPGA and solid state hard disc is reached as high as
4GB/s。
FPGA main control units 101 support hardware encryption algorithm, on the premise of data record bandwidth is not reduced, realize to note
Record the encryption of data.
The data entry format of data input cell 102 is settable, supports Camera Link, SDI, optical-fibre channel
With the data input of Ethernet protocol, the wherein data input of the Xilinx Aurora agreements of optical-fibre channel support multidiameter delay.
If using Camera Link, SDI and Ethernet protocol, data input cell 102 turns the input data of high speed serialization
Parallel data is activation is changed into FPGA main control units 101；If using fiber channel protocol, data input cell 102
Convert optical signals into high-speed serial signals and be sent to FPGA main control units 101.
FPGA main control units 101 by the Data Format Transform of various inputs into unified AXI buses, and by internal total
Line switch unit is written in data buffer storage unit 106.Data buffer storage unit 106 is by the DDR3SDRAM chipsets of 8 16
Into interface clock is up to 1066MHz, bit wide 128.
The interface of FPGA main control units 101 and SATA3 solid state hard discs array 107 is by RAID0 controllers and 8 road SATA
3IPCORE is constituted.Wherein RAID0 controllers realize the concurrent management to 8 pieces of solid state hard discs and operation, so as to improve data write-in
With reading bandwidth, SATA 3IPCORE are used to realize the protocol interface of SATA3, so as to complete the operation to solid state hard disc.
The data output format of data outputting unit 103 is settable, supports Camera Link, SDI, optical-fibre channel
With the data output of Ethernet protocol, wherein Camera Link and SDI agreements support that data readback and analogue camera data are defeated
Go out, optical-fibre channel and Ethernet protocol support that data derivation, the data transfer with new technology file system, optical-fibre channel support multichannel
The data output of parallel Xilinx Aurora agreements.
Monitoring interface unit 104 supports the data input output of RS422, RS232 and Ethernet protocol.Monitoring interface unit
By RS422 or RS232 interfaces, the configuration to high speed acquisition tape deck and condition monitoring are realized, such as formatted diskette, adjusted
Number of disks, control high speed acquisition tape deck start recording and stop recording etc..
Auxiliary signal input block 105 supports power down protection, i.e., the high speed acquisition record dress based on FPGA and solid state hard disc
Put in 10 course of normal operation, when running into improper power down, auxiliary signal input block 105 sends power-off signal and gives FPGA master controls
Be written to the data of caching in SATA3 solid state hard discs array 107 by unit 101, FPGA main control units 101, protects SATA3 solid-states
Data in hard disk array 107 are without damage.
Auxiliary signal input block 105 is supported to add longitude, latitude, temporal information in data recording process.Auxiliary letter
Number input block 105 can receive time and the geographical location information that GPS, big-dipper satellite or other systems send, and by the time and
Geographical location information is transferred in FPGA main control units 101.Wherein, the temporal information that other systems send supports IRIG-B DC
With AC yards.
Using connector connection is reinforced between SATA3 solid state hard discs array 107 and FPGA main control units 101, with locking
Function, anti-vibration, shock resistance.
As shown from the above technical solution, the present invention controls SATA3 solid state hard discs array to realize adopting at a high speed by using FPGA
Collection record, according to application demand, using different types of data such as Camera Link, SDI, optical-fibre channel and Ethernet protocol
Input, input data is directly entered data buffer storage unit by interface conversion, under the control of FPGA main control units, writes SATA3
In solid state hard disc array, output data also supports that the variety classeses such as Camera Link, SDI, optical-fibre channel and Ethernet protocol are defeated
Go out, have the advantages that：
1. record data bandwidth is high, reaches as high as 4GB/s, and memory capacity easily extends.
2. simple structure, the inputoutput data species of support is more, is particularly well-suited to embedded occasion to data record
Requirement more than high bandwidth, low-power consumption, small volume and kind of interface.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention rather than is limited,
Although being described in detail to the present invention with reference to preferred embodiment, it will be understood by those within the art that：Its according to
Technical scheme can so be modified or equivalent, and these modifications or equivalent can not also make to repair
Technical scheme after changing departs from the spirit and scope of technical solution of the present invention.
Claims (9)
1. a kind of high speed acquisition tape deck based on FPGA and solid state hard disc, it is characterised in that：
The high speed acquisition tape deck based on FPGA and solid state hard disc includes：FPGA main control units, data input cell, number
According to output unit, monitoring interface unit, auxiliary signal input block, data buffer storage unit, SATA3 solid state hard discs array, power supply
Administrative unit；
The FPGA main control units, connection data input cell, data outputting unit, monitoring interface unit, auxiliary signal input
Unit, data buffer storage unit, SATA3 solid state hard discs array, PMU, the operation for coordinating unit, and root
According to the order of monitoring interface unit, input data, the Comprehensive Control of output data and storage are realized；
The data input cell, one end connection FPGA main control units, the Data Input Interface outside the connection of one end, for external
The data of portion's input carry out protocol analysis and level conversion；
The data outputting unit, one end connection FPGA main control units, the data output interface outside the connection of one end, for realizing
The agreement and level conversion of data output；
The monitoring interface unit, one end connection FPGA main control units, monitoring and control unit outside the connection of one end, for right
Control and condition monitoring are realized in the operation of the high speed acquisition tape deck based on FPGA and solid state hard disc；
The auxiliary signal input block, one end connection FPGA main control units, the Data Input Interface outside the connection of one end is used for
Realize trigger signal, power down protection signal, temporal information, the input of positional information；
The data buffer storage unit, connects FPGA main control units, realizes the data buffer storage to input and output data, data buffer storage
Unit is formed by multi-disc DDR3SDRAM the parallel combineds；
The SATA3 solid state hard discs array, connects FPGA main control units, and multiple SATA3 solid state hard discs constitute SATA3 solid state hard discs
Array, realizes the data storage of high bandwidth；
The PMU, connection FPGA main control units, data input cell, data outputting unit, monitoring interface unit,
Auxiliary signal input block, data buffer storage unit, SATA3 solid state hard disc arrays, for being powered to unit.
2. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
The record data bandwidth of the high speed acquisition tape deck based on FPGA and solid state hard disc reaches as high as 4GB/s.
3. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
The FPGA main control units support hardware encryption algorithm, on the premise of data record bandwidth is not reduced, realize to record
The encryption of data.
4. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
The data input cell supports the data input of Camera Link, SDI, optical-fibre channel and Ethernet protocol.
5. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
The data outputting unit supports the data output of Camera Link, SDI, optical-fibre channel and Ethernet protocol.
6. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
The monitoring interface unit supports the data input output of RS422, RS232 and Ethernet protocol.
7. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
The auxiliary signal input block is supporting power down protection, i.e. the high speed acquisition tape deck based on FPGA and solid state hard disc just
In the normal course of work, when running into improper power down, auxiliary signal input block sends power-off signal and gives FPGA main control units, FPGA
Be written to the data of caching in SATA3 solid state hard disc arrays by main control unit, protects data in SATA3 solid state hard disc arrays not
It is damaged.
8. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
The auxiliary signal input block is supported to add longitude, latitude, temporal information in data recording process.
9. the high speed acquisition tape deck based on FPGA and solid state hard disc according to claim 1, it is characterised in that：
Using connector connection is reinforced between described SATA3 solid state hard discs array and FPGA main control units, with locking function,
Anti-vibration, shock resistance.
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Cited By (6)
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| CN107862762A (en) * | 2017-10-27 | 2018-03-30 | 天津津航计算技术研究所 | A kind of airplane data Quick Acquisition and storage system |
| CN108519857A (en) * | 2018-03-16 | 2018-09-11 | 中北大学 | Multi-source unformatted wideband data high speed magnanimity formats storage and feature security method |
| CN108762663A (en) * | 2018-05-30 | 2018-11-06 | 北京电子工程总体研究所 | A kind of multi-source multi-format data recording device |
| CN110688263A (en) * | 2019-09-30 | 2020-01-14 | 中国工程物理研究院计算机应用研究所 | FPGA-based hard disk automatic switching device and application method |
| CN111258504A (en) * | 2020-01-15 | 2020-06-09 | 西安电子科技大学 | Storage control system based on SATA interface solid state hard drives |
| CN112988629A (en) * | 2021-03-11 | 2021-06-18 | 北京信息科技大学 | Data recording device and method, storage medium |
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Application publication date: 20170627 |