CN102761466B - IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method - Google Patents
IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method Download PDFInfo
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Abstract
The invention discloses an IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method. The system is used for catching all data packets on a 1394 bus, storing the data packets on a storage unit in a real-time manner and then performing analysis processing on data, and the system comprises a 1394 interface unit, a high-speed data acquisition unit, a high-speed data storage unit, the storage unit and a post-processing unit, wherein the interface unit comprises a 1394 link layer controller and a 1394 bus physical layer chip and is used for receiving all the data packets on the 1394 bus; the high-speed data acquisition unit is used for acquiring all the data received by the 1394 bus interface unit; the high-speed data storage unit is used for storing the acquired data on a hard disk at a speed which is high enough; the storage unit is used for saving all the data of the 1394 bus and reading back the data when necessary for post-processing; and the 1394 link layer controller comprises a host interface, a link layer core module, a data buffering and route control module, a high-speed data interface module and a configuration register.
Description
Technical field
The present invention relates to a kind of equipment for catching and store all packets in IEEE1394 bus, be specifically related to a kind of IEEE 1394 bus data recording processing system and method.
Background technology
IEEE1394 bus (hereinafter referred to as 1394 buses) derives from the live wire (FireWire) of American apple company, come from 1394 of business and there is business support widely, perfect communication protocol and effective development tool, and through the abundant checking of business.International Electro IEEE (IEEE) is received as IEEE1394-1995 standard in nineteen ninety-five FireWire, after this develops into IEEE1394a-2000 again, the new standards such as IEEE1394b-2002.
1394-1995 and 1394a bus has the data transmission bauds of 100,200 and 400Mbps, and 1394b standard supports the data transmission bauds of 800Mbps, 1600Mbps, 3200Mbps.1394 buses can support at most 63 equipment, can support that 1023 buses are connected together by the mode of bridge joint.The cable of 1394, with energy line, carries out communication when device powers down or damage by this equipment, and Suspend Mode can also save power consumption.The node address of 1394 does not need equipment to set, but automatically completes address when bus initialization by physical layer protocol chip and arrange, and has flexibility and the extensibility of height, has the ability of plug and play.Therefore, its unlike USB, Ethernet or optical-fibre channel, do not need main frame intervention when the work of IEEE1394 bus, any smart machine can realize the function of bus management.When 1394 buses have etc. and asynchronous-response two kinds of transmission meanss.Especially isochronous transfers mode, can ensure the high speed real-time Transmission of the Large Volume Datas such as video, audio frequency and image.
Due to the advantage of 1394 buses, 1394 buses are widely used in the videos such as consumer electronics, home entertaining and automobile and image transmitting application, have even also been applied in Aero-Space and military defense project more and more.
Each node in a bus must observe communication protocol.Bus analyzer is by recording and resolve packet in bus, and help project planner locates the various incompatibility problems on bus communication protocol.At present, nearly about 10 kinds of the bus protocol instrument equipment of 1394 buses that can see, they are all external products.These products can various packets in Real-time Collection bus, also can carry out protocal analysis.But these packets collected only are temporarily stored in the internal memory of Bus analyzer, the memory size of Bus analyzer is very limited, can only keep in the packet in the short period.
For the development late stage of large-scale 1394 bus network, the node more than the dozens of of single-spot testing starts group net operation, and mode of operation is various, and topological structure is complicated, and bus data amount is large, and packet kind is many.Therefore, in the test run of long-term (more than a few hours even a couple of days), in network, often there are sporadic fault, error in data, deadlock or reset etc.The feature that these problems have " instantaneous generation, probability extremely low, not easily reappear ".
At this moment, once played the import Bus analyzer of great function, and because it can not record when problem occurs and analyze data, be difficult to meet the needs of fault location; And domestic development 1394 bus apparatus can only measured 1394 chips, these 1394 chips do not possess the function receiving all packets in bus, the packet issuing oneself can only be received, other packets all can " be thrown away ", in application name, applicant of the present invention to be called in the application documents of " a kind of IEEE 1394 link layer controller " that disclosing a kind of 1394 link layer controllers can accept all data, the present invention is based on the content disclosed in this application file.
Such situation, uses 1394 buses to build the exploitation of catenet for Aeronautics and Astronautics, automobile and home entertaining etc., proposes serious challenge.And the present invention can address this problem well.
Summary of the invention
The object of the invention is to, for overcoming existing various 1394 bus tests and development in the market, such as, Bus analyzer etc., although the data can caught in real time in 1394 buses also carry out protocal analysis, but the memory capacity of its capture-data and memory time are limited all in the extreme, and there are 1394 bus interface, but the equipment that can store data in a large number can not receive the problem of all data in 1394 buses, thus provide a kind of IEEE 1394 bus data recording processing system and method.
A kind of IEEE 1394 bus data recording processing system of the present invention is based on PC or work station or embedded system, and this system specifically comprises 1394 interface units, high-speed data acquisition unit, high-speed data processing unit, memory cell, control unit and display unit.
The invention provides a kind of IEEE 1394 bus data recording processing system, this system for catch all packets in 1394 buses and in real-time storage to memory cell after and reprocessing is carried out to data, comprise:
1394 interface units, this interface unit comprises 1394 link layer controllers and 1394 bus physical layer chips further, for receiving all packets in 1394 buses;
High-speed data acquisition unit, for all data received from described 1394 Bus Interface Unit collections;
High-speed data processing unit, for being stored into hard disk by the data collected with sufficiently high speed;
Memory cell, for preserving all data of 1394 bus, and, carries out reprocessing when needs by retaking of a year or grade out;
Post-processing unit, carries out reprocessing for the 1394 bus initial data that will record, and is processed into the data packet format being convenient to identify, and parses the content of each data field in packet, provide the various statistical informations of packet.
Wherein, described 1394 interface units, high-speed data acquisition unit, high speed disk interfaces unit and memory cell are all inserted in PC mainboard internal bus slot, or on the local bus of embedded device, adopt bus to intercom mutually; And described IEEE 1394 bus data register system also adopts the support of PC Installed System Memory and CPU.
In technique scheme, described 1394 link layer controllers comprise: host interface, link layer nucleus module, data buffering and routing module control, high speed interface module and configuration register; Outer CPU can read and write configuration register, access data buffering and the data buffer zone in routing module control by described host interface; Described data buffering and routing module control are between link layer nucleus module and host interface and high speed interface, for providing different transceiving data interchannel switching controls, wherein, described data buffering and routing module control also use two asynchronous first-in/first-out memories, are respectively used to the buffering of transceiving data and the synchronous of clock-domain crossing data; Described configuration register, for providing initial configuration to link layer nucleus module, data buffering and routing module control and control, implements by described host interface read-write configuration register the operating state controlling and obtain each module of link layer controller; Described link layer nucleus module, for realizing all functions of IEEE1394 bus protocol link layer, comprising: physical layer link layer interface, data buffering processing unit, data packet transceive unit, cyclic-redundancy-check unit and cycle controller; Described physical layer link layer interface, the standard interface between the link layer specified for providing IEEE1394 bus protocol and physical layer; Described data buffering processing unit, uses an asynchronous first-in/first-out memory to provide data buffering function for transceiving data bag; Described data packet transceive unit is the core of link layer nucleus module, is connected with data buffering processing unit, cyclic-redundancy-check unit, cycle controller and data buffering by bidirectional data line with routing module control; Described cyclic-redundancy-check unit, for providing cyclic redundancy check (CRC) function during transceiving data; Described cycle controller, comprises cycle timer and cycle monitor, service during for waiting; When sending packet, write the packet of specified format to data buffering and routing module control by host interface; The control of the buffering of data, the synchronous of multi-clock zone data and data route is realized again by data buffering and the asynchronous first-in/first-out memory of routing module control; Then, enter link layer nucleus module, carry out framing and the cyclic redundancy check (CRC) of data according to the form of different types of data bag in IEEE1394 bus protocol; Send the bus application of respective type to physical layer finally by physical layer link layer interface; After this link layer chip place node obtains bus control right, begin through physical layer link layer interface according to the speed forwarding data bag of specifying to universal serial bus; After Packet Generation completes, if what send is non-Broadcasting-Asynchronous bag, then waits for that destination node returns and confirm bag, if this link layer control chip place node is cycle controller, also can produces and send circulation and start bag to bus; When receiving packet, forwarded by physical layer link layer interface reception physical layer, the packet that universal serial bus transmits, at link layer nucleus module, described data packet transceive unit carries out the decoding of address and type of data packet to the packet received, if the destination node of this packet is not this node, then abandon the reception of packet; Otherwise, start to receive packet and carry out CRC check, as check errors then abandons the reception of packet, as correct then the data received according to the formatted output of specifying to data buffering and routing module control, the synchronous of multi-clock zone data and buffering is completed in this module, and according to route test, export data to transaction layer or application program by host interface; If what receive is non-Broadcasting-Asynchronous bag, after completing receives data packets, link layer nucleus module returns one and confirms that bag is to universal serial bus.
Described IEEE 1394 bus data register system also comprises: display unit.
All packets in described 1394 buses comprise: master data bag, physical layer data bag and response data packet.
Described master data handbag is drawn together: asynchronous nybble write request bag, asynchronous data block write request bag, asynchronous write respond packet, asynchronous nybble read request packet, asynchronous data block read request packet, asynchronous nybble reads respond packet, and asynchronous data block reads respond packet, asynchronous data block read respond packet, circulation start bag, locking request bag, asynchronous flow bag, etc. time bag and lock respond packet;
Described physical layer data handbag is drawn together: physical layer data handbag is drawn together: tagging packet, unlatching link bag, physical layer configurations bag, the logical bag of examination, remote access bag, long-range response packet, remote command bag, remote acknowledgement bag and recovery bag.
The memory capacity of described memory cell can be expanded; Described high speed interface module adopts parallel Data Input Interface, and bit wide is 32; Described high-speed data acquisition adopts double buffering pattern; Described memory cell adopts hard disk or hard disk array; The hard disk that described hard disk adopts rotating speed to be greater than 10000 rpms, and the interface of hard disk adopts the hard disk with scsi interface.
A kind of IEEE 1394 bus data recording processing method is also provided based on above IEEE 1394 bus data recording processing system the present invention, the method adopts system according to claim 1, comprises: the step of data record and the data for record carry out the step of reprocessing:
Wherein, the step of described data record comprises following steps further:
1) mode of operation is set to receive all data by 1394 Bus Interface Chips;
2) according to system resource, high speed acquisition unit is set and is receiving mode and the size that buffering area is set;
3) size of the data file that hard disk stores and the disk partition of storage are set;
4) start high speed acquisition unit, start to receive 1394 Bus Interface Units and receive packet; On disk, generate a raw data file simultaneously, when the size of the data file that data accumulation is arranged to above time, complete the storage of data on disk, close data file; Generate new data file, this step continues always simultaneously;
5) in time not needing record data, described high-speed data acquisition unit no longer receives the packet that 1394 Bus Interface Units receive again, and disk stops storing data files simultaneously.
Described Data Post step comprises following steps further:
First all data received are opened; Then, the data content of CPU file reading successively; Often read 4 byte datas, and the packet header of the various packets of IEEE 1394 standard definition compares, and determines the kind of packet; If need, then read 4 byte datas, until can data class be judged; After determining packet kind, therefrom extract data package size field, read the data of respective byte quantity according to the size of this packet; If the packet of the type is not the type of data packet of wishing process, then directly skip this segment data, process data below; Then, according to the definition of this kind data packet format in IEEE 1394 standard, contrasting data, obtains the numerical value that in packet, each data field is corresponding; Finally, by the numerical value of each data field and correspondence thereof successively writing in files, the last handling process of data is completed.
The invention has the advantages that:
(1) all packets in 1394 buses can be received.No matter packet is that type, and no matter packet is which node in bus sends, and mail to which node, and no matter which grade is the speed of packet be, no matter when packet appears at, and this equipment can correctly intactly receive.(2) can catch in real time for a long time and store all data.Adopt due to the present invention and be integrated with data acquisition at a high speed and memory technology, the high-speed data of 1394 bus 400Mbps can be correctly intactly directly stored on the storage mediums such as hard disk, instead of is temporarily stored in internal memory.Therefore, as long as the capacity of the storage mediums such as hard disk is enough large, the time of record of the present invention just can long enough.And the storage mediums such as hard disk can expand when needed at any time and expand online.Can all packets in long record 1394 bus, for the data record in 1394 bus system uniting and adjustment processes, fault location and system verification provide means.(3) Data Post unit, can according to the needs of user, the data of care are picked out from the bus initial data of enormous amount, be treated as the packet easily identified, and parse the content of each data field in packet, and provide the various statistical informations of packet, to analyze the signal intelligence of bus.
Accompanying drawing explanation
Fig. 1 is the functional schematic of IEEE1394 bus data register system of the present invention;
The 1394 Bus Interface Unit composition function module map that Fig. 2 IEEE1394 bus data of the present invention register system adopts;
The 1394 bus links layer controller function composition frame charts that Fig. 3 1394 Bus Interface Units of the present invention comprise;
The high-speed data acquisition unit composition frame chart that Fig. 4 IEEE1394 bus data of the present invention register system adopts;
The data record method flow chart of steps of Fig. 5 IEEE1394 bus data of the present invention register system;
The data post processing method flow chart of steps of Fig. 6 IEEE1394 bus data of the present invention register system.
Embodiment
Below in conjunction with accompanying drawing, summary of the invention is elaborated:
As shown in Figure 1, this figure is the functional block diagram of a kind of 1394 bus data register systems provided by the invention, and this system builds based on PC or work station again.1394 bus data register systems comprise: 1394 interface units 1, for receiving all packets in 1394 buses; High-speed data acquisition unit 2, high speed disk interfaces unit 3, memory cell 4 and post-processing unit 7.They all insert in PC mainboard PCI slot, are connected in pci bus 6, and need the support of PC Installed System Memory and CPU etc. during this system works.
1394 Bus Interface Units 1 are primarily of 1394 general bus physical layer controllers and 1394 special bus links layer controller forming circuit plates.1394 general bus links layer controller can only receive the packet that destination is self, the packet of other nodes all can " be thrown away ", and 1394 special bus links layer controller can receive all packets, it is packet rs destination no matter which node in bus.1394 Bus Interface Units 1 comprise 1394 link layer controller 11 and 1394 bus physical layer controllers 12.1394 link layer controllers 11 are connected with 1394 bus physical layer controller 12 signals, and concrete on-link mode (OLM) as shown in Figure 2.Wherein 1394 bus links layer controller 11 can receive all packets in 1394 buses, no matter whether this packet sends to these 1394 Bus Interface Units, and this unit the name of REFERENCE TO RELATED people application can be called the application documents of " a kind of IEEE 1394 link layer controller ".
High-speed data acquisition unit 2, all data that can receive from 1394 Bus Interface Units with sufficiently high speed collection, and these data are transferred to storage unit in high speed.
High-speed data processing unit 3, can be stored into the high-speed data collected on hard disk with sufficiently high speed.
Memory cell 4, be the medium that data store, this unit saves all data of 1394 bus, and when needs by retaking of a year or grade out, can carry out reprocessing.
The all data files received are resolved to each packet, and parse the content of each data field according to the definition of each packet by post-processing unit 7, provide the various statistical informations of packet simultaneously.
1394 Bus Interface Units 1 can designed, designed and write the IP (intellectual property) that has and receives all packet functions and in the upper realization of FPGA (field programmable gate array).This embodiment has advantage easily of upgrading, and can provide the function such as packet segmentation, timestamp.The functional block diagram of this intellectual property as shown in Figure 3.The interface of this special chip outside and pin and do not possess general-purpose chip (the link layer controller TSB12LV32 that TI company produces of this function, the name of this chip is called " General Purpose 1394 Link layer Controller ", i.e. general 1394 link layer controllers) completely the same.
Other 1394 bus links layer controller 11, the link layer controller TSB12LV32 produced with Texas Instrument is completely compatible.As shown in Figure 3, the 1394 bus links layer controller 11 that the present invention adopts comprise link layer and physical layer interface unit 111, data buffer storage unit 112, processing data packets unit 113, control register unit 114, high speed interface unit 115 and control interface unit 116 form.Link layer physical layer interface 111 provides IEEE1394 bus specified standard interface, all packets in bus and state information are all forwarded to chip by this interface by physical layer, described chip can referenced patent application number for " a kind of IEEE 1394 link layer controller " namely 11 and " a kind of programmable IEEE 1394 bus monitoring system and monitoring method " two sections of patent documents described in chip.Link layer physical layer interface 111 is connected with data buffer storage unit 112, is made up of asynchronous FIFO, plays data buffering and synchronous effect, and bus state is updated directly into control register unit 114.Processing data packets unit 113 is connected with the data buffer storage unit 112 of upstream, and be connected with the high speed interface module 115 in downstream, be also connected with control register unit 114 simultaneously, its function is controlled the control of register 114 parameters.Processing data packets unit 113 arranges the information such as numerical value requiring record and the packet kind stored, length, particular data territory according to user, the various packets selectively or all record trunk transmitted, and is forwarded to high speed interface unit 115.Meanwhile, this unit can also provide the information such as packet capture time.Control interface unit 116, for being connected with ppu, realizes the function setting to 1394 link layer controllers 11.High speed interface unit 115 is connected with processing data packets unit 113, provides the high-speed interface that data export.In the present embodiment, the Data Mover interface of this interface and TSB12LV32 is completely the same.Phy controller 12 in 1394 Bus Interface Units directly uses general phy controller.This controller can select any a product in the market in theory.But, consider that phy controller directly determines the port number of 1394 bus interface, therefore, the TSB41AB3 that TIX produces can be adopted.
High-speed data acquisition unit 2 for gathering all packets received by 1394 bus interface.The present invention builds based on PC or work station, therefore, the concrete effect of high-speed data acquisition unit be exactly by packet according to PCI protocol forward in pci bus.Execution mode will in conjunction with the basic structure of PC or work station.Functional modules all in current PC or work station is all based on pci bus or PCIe bus, PCI or PCIe has the speed much larger than 1394 buses, therefore can complete the collection of high-speed data.The pci bus that the present embodiment adopts.
As shown in Figure 4, high-speed data acquisition unit 2 comprises high speed interface module 21, data cache module 22 and PCI bridge module 23.The high speed packet that high speed interface module 21 is caught for receiving 1394 bus data interface units, because data rate is higher, should adopt parallel Data Input Interface, and bit wide is 32.Data cache module 22 is for data buffer storage with synchronous, and the main FIFO of employing realizes, and largest buffered data volume is not less than 16K byte.PCI bridge module 23 completes the conversion of PCI agreement, is sent in the pci bus of main frame by high-speed data according to PCI agreement.PCI module can use special PCI bridging chip or IP kernel to realize.The execution mode of this unit both can designed, designed, also can adopt capture card finished product on market, the products such as the PCI7300A data collecting card of ADLINK company.
High-speed data acquisition adopts double buffering pattern, also can be described as cyclic buffer pattern.Here buffering area refers to the internal memory of system.Double buffering pattern can use internal memory comparatively in a small amount, and collecting is almost unlimited many data.The principle of this mode of operation is: the buffering area for continuous input operation has logically been divided into two complete equal parts (will divide below have another name called them be first half buffering area and second half buffering area); During work, first the data collected write in first half buffering area by capture card, while capture card starts to write data in second half buffering area, application program can do specific process to the data in first half buffering area as required: after second half buffering area is fully written, capture card will turn back to the section start of first half buffering area, by the mode covering front secondary data, data are write in first half buffering area.The process of whole data acquisition process so constantly can circulate and go on.
High speed disk interfaces unit 3 is for mating the interface of high speed hard-disk.When 1394 buses carry out data capture, high-speed data acquisition unit 2, in high-speed data processing unit 4, the speed of any one unit is lower, all can restrict the speed that whole system data store.Speed is lower often for the hard disk of memory cell 4.The storage speed of hard disk depends on the rotating speed of interface rate, disk and the access speed of magnetic head, but the rotation of magnetic head and magnetic sheet is the action of machinery, be difficult to reach flank speed, so the hard disk that rotating speed is as far as possible high can only be selected, by special method, other factors affecting hard disk speed must all be reduced to minimum simultaneously.Such as, the hard disk of scsi interface.Concrete implementation method, directly can adopt SCSI hard disk controlling card on market.When the Bus Speed of reality test is lower, time the lower contradiction of data storage of hard disk is not given prominence to, this unit can omit, and directly the data collected in internal memory can be write hard disk by Windows operating system.
Hard disk or hard disk array 4.In order to realize higher memory rate, hard disk can adopt the hard disk that rotating speed index is higher, and the present embodiment have employed the hard disk that rotating speed is greater than 10000 rpms.The interface of hard disk can adopt the interface of higher rate, such as, has the hard disk of scsi interface.When the Bus Speed of reality test is lower, time the lower contradiction of data storage of hard disk is not given prominence to, general hard disk can be adopted.
Installed System Memory 5 is internal memories of PC or industrial computer.
Work for IEEE1394 bus data register system provided by the invention also needs the control of actuation step, equipment rate-determining steps and Data Post step and man-machine interaction step.
Wherein, initialization (driving) method: high-speed data acquisition unit is arranged suitable data transfer rate and buffer area by PC or embedded type CPU; Hardware device is made to be in the pattern of wait-receiving mode order.
Apparatus control method: arranged and select the size of storing data files, memory location by man-machine interface, need the type of data packet of reprocessing.By clicking the button at interface, start data record; By clicking conclusion button, end data record; By clicking reprocessing button, start to carry out data record.
As shown in Figure 5, this figure is the workflow diagram of IEEE1394 bus data record system provided by the invention.Specifically describe as follows:
1) first, device power-on, mode of operation can be set to receive all data by 1394 Bus Interface Chips in IEEE1394 bus data register system of the present invention automatically, does not need artificial setting and intervenes.At this moment, 1394 Bus Interface Units have started to receive all packets in bus;
2) secondly, according to system resource, high speed acquisition unit is set and is receiving mode and the size that buffering area is set;
3) then, the size of the data file that hard disk stores, the disk partition of storage is arranged on by man-machine interface;
4) then, click " startup ", start high speed acquisition unit, start to receive 1394 Bus Interface Units and receive packet; On disk, generate a raw data file simultaneously, when the size of the data file that data accumulation is arranged to above time, complete the storage of data on disk, close data file; Generate new data file, this step continues always simultaneously;
5) in time not needing record data, click " end ", high-speed data acquisition unit no longer receives the packet that 1394 Bus Interface Units receive again, also not storing data files on disk;
6) last, the type of 1394 bus data bags of a kind of, multiple or whole hope process is selected in man-machine interface, click " reprocessing " button, PC or other systems with CPU start raw data file to read from disk, process in internal memory, concrete processing method is shown in Fig. 6.Again the data after process are stored on disk in the form of a file after being disposed.Whole process terminates.
The data post processing method flow chart of steps of Fig. 6 IEEE1394 bus data of the present invention register system, post-processing approach step provided by the invention is as follows:
1) first all data files received are opened by PC or industrial computer or other equipment with CPU;
2) then, the data content of CPU file reading successively.Often read 4 byte datas, and the packet header of the various packets of IEEE 1394 standard definition compares, and determines the kind of packet; If need, then read 4 byte datas, until can data class be judged;
3) after determining packet kind, therefrom extract data package size field, read the data of respective byte quantity according to the size of this packet; If the packet of the type is not the type of data packet of wishing process, then directly skip this segment data, process data below;
4) then, according to the definition of this kind data packet format in IEEE 1394 standard, contrasting data, obtains the numerical value that in packet, each data field is corresponding;
5) last, by the numerical value of each data field and correspondence thereof successively writing in files, complete the last handling process of data.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted.Although with reference to embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, modify to technical scheme of the present invention or equivalent replacement, do not depart from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (14)
1. an IEEE 1394 bus data recording processing system, this system for catch all packets in 1394 buses and in real-time storage to memory cell after and reprocessing is carried out to data, comprise:
1394 interface units, this interface unit comprises 1394 link layer controllers and 1394 bus physical layer chips further, for receiving all packets in 1394 buses;
High-speed data acquisition unit, for all data received from described 1394 Bus Interface Unit collections; Wherein, high-speed data acquisition adopts double buffering pattern, also can be described as cyclic buffer pattern; The principle of this mode of operation is: the buffering area for continuous input operation has logically been divided into two complete equal parts, below will divide another name they be first half buffering area and second half buffering area; During work, first the data collected write in first half buffering area by capture card, while capture card starts to write data in second half buffering area, application program can do specific process to the data in first half buffering area as required: after second half buffering area is fully written, capture card will turn back to the section start of first half buffering area, by the mode covering front secondary data, data are write in first half buffering area; The process of whole data acquisition process so constantly can circulate and go on;
High speed disk interfaces unit, for mating the interface of hard disk, the concrete hard disk adopting scsi interface;
High-speed data processing unit, for being stored into hard disk by the data collected with sufficiently high speed;
Memory cell, for preserving all data of 1394 bus, and, carries out reprocessing when needs by retaking of a year or grade out; With
Post-processing unit, carries out reprocessing for the 1394 bus initial data that will record, and is processed into the data packet format being convenient to identify, and parses the content of each data field in packet; Be specially: 1) first all data files received are opened by PC or industrial computer or other equipment with CPU; 2) then, the data content of CPU file reading successively; Often read 4 byte datas, and the packet header of the various packets of IEEE 1394 standard definition compares, and determines the kind of packet; If need, then read 4 byte datas, until can data class be judged; 3) after determining the kind of packet, therefrom extract data package size field, read the data of respective byte quantity according to the size of this packet; If the packet of the type is not the type of data packet of wishing process, then directly skip this segment data, process data below; 4) then, according to the definition of this kind data packet format in IEEE 1394 standard, contrasting data, obtains the numerical value that in packet, each data field is corresponding; 5) last, by the numerical value of each data field and correspondence thereof successively writing in files, complete the last handling process of data;
Wherein, described 1394 interface units, high-speed data acquisition unit, high speed disk interfaces unit and memory cell are all inserted in PC mainboard internal bus slot, or on the local bus of embedded device, adopt bus to intercom mutually; And described IEEE 1394 bus data recording processing system also comprises PC Installed System Memory and CPU.
2. IEEE 1394 bus data recording processing system according to claim 1, it is characterized in that, described 1394 link layer controllers comprise: host interface, link layer nucleus module, data buffering and routing module control, high speed interface module and configuration register; Outer CPU can read and write configuration register, access data buffering and the data buffer zone in routing module control by described host interface; Described data buffering and routing module control are between link layer nucleus module and host interface and high speed interface, for providing different transceiving data interchannel switching controls, wherein, described data buffering and routing module control also use two asynchronous first-in/first-out memories, are respectively used to the buffering of transceiving data and the synchronous of clock-domain crossing data; Described configuration register, for providing initial configuration to link layer nucleus module, data buffering and routing module control and control, implements by described host interface read-write configuration register the operating state controlling and obtain each module of link layer controller;
Described link layer nucleus module, for realizing all functions of IEEE 1394 bus protocol link layer, comprising: physical layer link layer interface, data buffering processing unit, data packet transceive unit, cyclic-redundancy-check unit and cycle controller;
Described physical layer link layer interface, for providing the standard interface between IEEE 1394 link layer that bus protocol specifies and physical layer;
Described data buffering processing unit, uses an asynchronous first-in/first-out memory to provide data buffering function for transceiving data bag;
Described data packet transceive unit is the core of link layer nucleus module, is connected with data buffering processing unit, cyclic-redundancy-check unit, cycle controller and data buffering by bidirectional data line with routing module control;
Described cyclic-redundancy-check unit, for providing cyclic redundancy check (CRC) function during transceiving data;
Described cycle controller, comprises cycle timer and cycle monitor, service during for waiting;
When sending packet, write the packet of specified format to data buffering and routing module control by host interface; The control of the buffering of data, the synchronous of multi-clock zone data and data route is realized again by data buffering and the asynchronous first-in/first-out memory of routing module control; Then, enter link layer nucleus module, carry out framing and the cyclic redundancy check (CRC) of data according to the form of different types of data bag in IEEE 1394 bus protocol; Send the bus application of respective type to physical layer finally by physical layer link layer interface; After this link layer chip place node obtains bus control right, begin through physical layer link layer interface according to the speed forwarding data bag of specifying to universal serial bus;
After Packet Generation completes, if what send is non-Broadcasting-Asynchronous bag, then waits for that destination node returns and confirm bag, if this link layer control chip place node is cycle controller, also can produces and send circulation and start bag to bus;
When receiving packet, forwarded by physical layer link layer interface reception physical layer, the packet that universal serial bus transmits, at link layer nucleus module, described data packet transceive unit carries out the decoding of address and type of data packet to the packet received, if the destination node of this packet is not this node, then abandon the reception of packet; Otherwise, start to receive packet and carry out CRC check, as check errors then abandons the reception of packet, as correct then the data received according to the formatted output of specifying to data buffering and routing module control, the synchronous of multi-clock zone data and buffering is completed in this module, and according to route test, export data to transaction layer or application program by host interface; If what receive is non-Broadcasting-Asynchronous bag, after completing receives data packets, link layer nucleus module returns one and confirms that bag is to universal serial bus.
3. IEEE 1394 bus data recording processing system according to claim 1, is characterized in that, described IEEE 1394 bus data register system also comprises: display unit.
4. IEEE 1394 bus data recording processing system according to claim 1, it is characterized in that, all packets in described 1394 buses comprise: master data bag, physical layer data bag and response data packet.
5. IEEE 1394 bus data recording processing system according to claim 4, is characterized in that,
Described master data handbag is drawn together: asynchronous nybble write request bag, asynchronous data block write request bag, asynchronous write respond packet, asynchronous nybble read request packet, asynchronous data block read request packet, asynchronous nybble reads respond packet, and asynchronous data block reads respond packet, asynchronous data block read respond packet, circulation start bag, locking request bag, asynchronous flow bag, etc. time bag and lock respond packet;
Described physical layer data handbag is drawn together: physical layer data handbag is drawn together: tagging packet, unlatching link bag, physical layer configurations bag, the logical bag of examination, remote access bag, long-range response packet, remote command bag, remote acknowledgement bag and recovery bag.
6. IEEE 1394 bus data recording processing system according to claim 1, it is characterized in that, the memory capacity of described memory cell can be expanded.
7. IEEE 1394 bus data recording processing system according to claim 1, is characterized in that, described high speed interface module adopts parallel Data Input Interface, and bit wide is 32.
8. IEEE 1394 bus data recording processing system according to claim 1, is characterized in that, described memory cell adopts hard disk or hard disk array.
9. IEEE 1394 bus data recording processing system according to claim 8, is characterized in that, the hard disk that described hard disk adopts rotating speed to be greater than 10000 rpms, and the interface of hard disk adopts the hard disk with scsi interface.
10. an IEEE 1394 bus data recording processing method, the method adopts system according to claim 1, comprises: the step of data record and the data for record carry out the step of reprocessing:
Wherein, the step of described data record comprises following steps further:
1) mode of operation is set to receive all data by 1394 Bus Interface Chips;
2) according to system resource, high speed acquisition unit is set and is receiving mode and the size that buffering area is set;
3) size of the data file that hard disk stores and the disk partition of storage are set;
4) start high speed acquisition unit, start to receive 1394 Bus Interface Units and receive packet; On disk, generate a raw data file simultaneously, when the size of the data file that data accumulation is arranged to above time, complete the storage of data on disk, close data file; Generate new data file, this step continues always simultaneously;
Wherein, high-speed data acquisition adopts double buffering pattern, also can be described as cyclic buffer pattern; The principle of this mode of operation is: the buffering area for continuous input operation has logically been divided into two complete equal parts, below will divide another name they be first half buffering area and second half buffering area; During work, first the data collected write in first half buffering area by capture card, while capture card starts to write data in second half buffering area, application program can do specific process to the data in first half buffering area as required: after second half buffering area is fully written, capture card will turn back to the section start of first half buffering area, by the mode covering front secondary data, data are write in first half buffering area; The process of whole data acquisition process so constantly can circulate and go on;
5) in time not needing record data, described high-speed data acquisition unit no longer receives the packet that 1394 Bus Interface Units receive again, and disk stops storing data files simultaneously;
Described Data Post step comprises following steps further:
First all data received are opened; Then, the data content of CPU file reading successively; Often read 4 byte datas, and the packet header of the various packets of IEEE 1394 standard definition compares, and determines the kind of packet; If need, then read 4 byte datas, until can data class be judged; After determining packet kind, therefrom extract data package size field, read the data of respective byte quantity according to the size of this packet; If the packet of the type is not the type of data packet of wishing process, then directly skip this segment data, process data below; Then, according to the definition of this kind data packet format in IEEE 1394 standard, contrasting data, obtains the numerical value that in packet, each data field is corresponding; Finally, by the numerical value of each data field and correspondence thereof successively writing in files, the last handling process of data is completed.
11. IEEE 1394 bus data recording processing methods according to claim 10, it is characterized in that, all packets in described 1394 buses comprise: master data bag, physical layer data bag and response data packet.
12. IEEE 1394 bus data recording processing methods according to claim 11, is characterized in that,
Described master data handbag is drawn together: asynchronous nybble write request bag, asynchronous data block write request bag, asynchronous write respond packet, asynchronous nybble read request packet, asynchronous data block read request packet, asynchronous nybble reads respond packet, and asynchronous data block reads respond packet, asynchronous data block read respond packet, circulation start bag, locking request bag, asynchronous flow bag, etc. time bag and lock respond packet;
Described physical layer data handbag is drawn together: physical layer data handbag is drawn together: tagging packet, unlatching link bag, physical layer configurations bag, the logical bag of examination, remote access bag, long-range response packet, remote command bag, remote acknowledgement bag and recovery bag.
13. IEEE 1394 bus data recording processing methods according to claim 10, it is characterized in that, the memory capacity of described memory cell can be expanded.
14. IEEE 1394 bus data recording processing methods according to claim 10, is characterized in that, described memory cell adopts hard disk or hard disk array.
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