CN102761466A - IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method - Google Patents
IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method Download PDFInfo
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Abstract
The invention discloses an IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method. The system is used for catching all data packets on a 1394 bus, storing the data packets on a storage unit in a real-time manner and then performing analysis processing on data, and the system comprises a 1394 interface unit, a high-speed data acquisition unit, a high-speed data storage unit, the storage unit and a post-processing unit, wherein the interface unit comprises a 1394 link layer controller and a 1394 bus physical layer chip and is used for receiving all the data packets on the 1394 bus; the high-speed data acquisition unit is used for acquiring all the data received by the 1394 bus interface unit; the high-speed data storage unit is used for storing the acquired data on a hard disk at a speed which is high enough; the storage unit is used for saving all the data of the 1394 bus and reading back the data when necessary for post-processing; and the 1394 link layer controller comprises a host interface, a link layer core module, a data buffering and route control module, a high-speed data interface module and a configuration register.
Description
Technical field
The present invention relates to a kind of equipment that is used to catch and store all packets on the IEEE1394 bus, be specifically related to a kind of IEEE 1394 bus data recording processing system and methods.
Background technology
IEEE1394 bus (hereinafter to be referred as 1394 buses) derives from the live wire (FireWire) of U.S. Apple, and come from 1394 of commerce and have the wide range of commercial support, perfect communication protocol and effective development tool, and through commercial abundant checking.International Electronic Engineering Association (IEEE) is received as the IEEE1394-1995 standard to FireWire in nineteen ninety-five, after this develops into new standards such as IEEE1394a-2000, IEEE1394b-2002 again.
1394-1995 and 1394a bus have 100,200 and the data transmission bauds of 400Mbps, and the 1394b standard is supported the data transmission bauds of 800Mbps, 1600Mbps, 3200Mbps.On one 1394 bus, can support 63 equipment at most, can support 1023 buses to connect together through the mode of bridge joint.1394 cable has energy line, under the situation of device powers down or damage, can carry out communication through this equipment, and Suspend Mode can also be saved power consumption.1394 node address does not need apparatus settings, but accomplishes address setting when the bus initialization automatically by the PHY chip, has the flexibility and the extensibility of height, has the ability of plug and play.Therefore it does not need the main frame intervention unlike USB, Ethernet or optical-fibre channel in the time of the work of IEEE1394 bus, and any smart machine can both be realized the function of bus management.When 1394 buses have etc. and asynchronous-two kinds of transmission meanss of response.Transmission means when especially waiting can guarantee the high-speed real-time transmission of Large Volume Datas such as video, audio frequency and image.
Because the advantage of 1394 buses, 1394 buses have obtained using widely in video such as consumer electronics, home entertaining and automobile and image transmission application, even also have been applied in more and more in Aero-Space and the military project project.
Each node in bus all must observe communication protocol.The bus analysis appearance is through record and resolve packet on the bus, helps the project planner to locate the various incompatibility problems on the bus communication protocol.At present, nearly about 10 kinds of the bus protocol appearance equipment of 1394 buses that can see, they all are external products.These products can both be gathered the various packets on the bus in real time, also can carry out protocal analysis.But these packets that collect only are temporarily stored in the internal memory of bus analysis appearance, and the memory size of bus analysis appearance is very limited, can only keep in the packet in the short period.
For the development late stage of large-scale 1394 bus network, the node above through the dozens of of single-spot testing begins group net operation, and mode of operation is various, and topological structure is complicated, and the bus data amount is big, and the packet kind is many.Therefore in the test run of long-term (more than several hours even a couple of days), tend to occur sporadic fault, error in data in the network, crash or reset etc.These problems have the characteristics of " extremely low, the difficult reproduction of instantaneous generation, probability ".
At this moment, once brought into play the import bus analysis appearance of huge effect, and, be difficult to satisfy the needs of fault location because it can not write down and analyze data when problem occurs; And domestic development 1394 bus apparatus can only measured 1394 chips; These 1394 chips do not possess the function that receives all packets on the bus; Can only receive the packet of issuing oneself; Other packets all can " be thrown away ", and applicant of the present invention discloses a kind of 1394 link layer controllers in application name is called the application documents of " a kind of IEEE 1394 link layer controllers " can accept all data, the present invention is based on the disclosed content of this application file.
Such situation uses 1394 buses to make up the exploitation of catenet for Aeronautics and Astronautics, automobile and home entertaining etc., has proposed serious challenge.And the present invention can address this problem well.
Summary of the invention
The objective of the invention is to; For overcoming existing in the market various 1394 bus tests and development; For example; Bus analysis appearance etc., though can captured in real time on 1394 buses data and carry out protocal analysis, its memory capacity and memory time of catching data is all limited in the extreme; But and have the problem that equipment 1394 EBIs, that can store data in a large number can not receive all data on 1394 buses, thereby a kind of IEEE 1394 bus data recording processing system and methods are provided.
A kind of IEEE of the present invention 1394 bus data recording processing systems are based on PC or work station or embedded system, and this system specifically comprises 1394 interface units, high-speed data acquisition unit, high-speed data memory cell, memory cell, control unit and display unit.
The present invention provides a kind of IEEE 1394 bus data recording processing systems, and this system is used to catch all packets and real-time storage on 1394 buses back and data are carried out reprocessing on the memory cell, comprises:
1394 interface units, this interface unit further comprise 1394 link layer controllers and 1394 bus physical layer chips, are used to receive all packets on 1394 buses;
The high-speed data acquisition unit is used for all data that receive from said 1394 Bus Interface Unit collections;
The high-speed data memory cell is used for storing the data that collect into hard disk with sufficiently high speed;
Memory cell is used to preserve all data of 1394 buses, and in needs, is come out by retaking of a year or grade, carries out reprocessing;
Post-processing unit is used for the 1394 bus initial data of noting are carried out reprocessing, is processed into and is convenient to the recognition data packet format, and parse the content of each data field in the packet, and the various statistic of packet is provided.
Wherein, said 1394 interface units, high-speed data acquisition unit, high speed disk interfaces unit and memory cell are all inserted in the PC mainboard internal bus slot, or on the local bus of embedded device, adopt bus to intercom mutually; And said IEEE 1394 bus data register systems also adopt the support of PC Installed System Memory and CPU.
In the technique scheme, said 1394 link layer controllers comprise: HPI, link layer nucleus module, data buffering and routing module control, high speed interface module and configuration register; Outer CPU can be read and write the data buffer zone in configuration register, access data buffering and the routing module control through described HPI; Described data buffering and routing module control are between link layer nucleus module and HPI and the high speed interface; Be used to provide different transceive data interchannel switching controls; Wherein, Described data buffering and routing module control have also used two asynchronous first-in/first-out memories, are respectively applied for the buffering and the cross clock domain synchronization of data of transceive data; Described configuration register is used to provide initial configuration and the control to link layer nucleus module, data buffering and routing module control, implements to control and obtain the operating state of each module of link layer controller through described HPI read-write configuration register; Described link layer nucleus module is used for realizing comprising all functions of IEEE1394 bus protocol link layer: physical layer link layer interface, data buffering processing unit, data packet transceive unit, cyclic-redundancy-check unit and cycle controller; Described physical layer link layer interface is used to provide the link layer of IEEE1394 bus protocol regulation and the standard interface between physical layer; Described data buffering processing unit uses an asynchronous first-in/first-out memory as the transceive data bag data buffering function to be provided; Described data packet transceive unit is the core of link layer nucleus module, links to each other with routing module control with data buffering processing unit, cyclic-redundancy-check unit, cycle controller and data buffering through bidirectional data line; Said cyclic-redundancy-check unit, the CRC function when being used to transceive data is provided; Said cycle controller comprises cycle timer and cycle monitor, service when being used for waiting; When sending packet, the packet that writes specified format through HPI is to data buffering and routing module control; Realize the control of buffering, multi-clock zone synchronization of data and the data route of data again through the asynchronous first-in/first-out memory of data buffering and routing module control; Then, get into the link layer nucleus module, carry out the framing and the CRC of data according to the form of different types of data bag in the IEEE1394 bus protocol; Send the bus application of respective type at last to physical layer through the physical layer link layer interface; After this link layer chip place node obtains bus control right, begin to transmit packet to universal serial bus according to the speed of appointment through the physical layer link layer interface; After packet send to be accomplished,, wait for then that destination node is returned and confirm bag,, also can produce and send circulation and begin to wrap bus if this link layer control chip place node is a cycle controller if what send is non-Broadcasting-Asynchronous bag; When receiving packet; Transmit through physical layer link layer interface reception physical layer; Data packets for transmission on universal serial bus, at the link layer nucleus module, said data packet transceive unit carries out the decoding of address and type of data packet to the packet that receives; If the destination node of this packet is not this node, then the reception of forgo data bag; Otherwise; Begin to receive packet and carry out CRC check; Like the then reception of forgo data bag of check errors, then output to data buffering and routing module control to the data that receive according to the form of appointment as correct, in this module, accomplish multi-clock zone synchronization of data and buffering; And, arrive transaction layer or application program through the HPI dateout according to route control; If what receive is non-Broadcasting-Asynchronous bag, after the completion packet received, the link layer nucleus module returned an affirmation and wraps universal serial bus.
Said IEEE 1394 bus data register systems also comprise: display unit.
All packets on said 1394 buses comprise: master data bag, physical layer data bag and response data packet.
Said master data bag comprises: asynchronous nybble is write request package; The asynchronous data piece is write request package, asynchronous write respond packet, asynchronous nybble read request packet; Asynchronous data piece read request packet; Asynchronous nybble is read respond packet, and the asynchronous data piece is read respond packet, the asynchronous data piece read respond packet, circulation begin bag, locking request bag, asynchronous flow bag, etc. the time bag and lock respond packet;
Said physical layer data bag comprises: the physical layer data bag comprises: tagging packet, unlatching link bag, physical layer configurations bag, the logical bag of examination, remote access bag, long-range response packet, remote command bag, remote acknowledgement bag and recovery bag.
The memory capacity of said memory cell can be expanded; Said high speed interface module adopts parallel Data Input Interface, and bit wide is 32; The double buffering pattern is adopted in said high-speed data acquisition; Said memory cell adopts hard disk or hard disk array; Said hard disk adopts rotating speed greater than 10000 rpms hard disk, and the interface of hard disk adopts the hard disk with scsi interface.
1394 bus data recording processing the present invention of system also provide a kind of IEEE 1394 bus data recording processing methods based on above IEEE; This method adopts the described system of claim 1, comprises: the step of data record and the step of carrying out reprocessing to data recorded:
Wherein, the step of said data record further comprises following steps:
1) 1394 Bus Interface Chip mode of operations are set to receive all data;
2) according to system resource, it is receiving mode and the size that buffering area is set that the high speed acquisition unit is set;
3) size of the data file of storing on the hard disk and the disk partition of storage are set;
4) start the high speed acquisition unit, begin to receive 1394 Bus Interface Units and receive packet; On disk, generate simultaneously a raw data file, in the time of the size of the data file that is provided with to the front when data accumulation, data file is closed in the storage of completion data on disk; Generate new data file simultaneously, this step continues always;
5) when not needing record data, said high-speed data acquisition unit no longer receives the packet that 1394 Bus Interface Units receive again, and disk stops storing data files simultaneously.
Said Data Post step further comprises following steps:
All data that at first will receive are opened; Then, CPU reads the data content of file successively; The packet header of whenever reading the various packets of 4 byte datas and IEEE 1394 standard definitions compares the kind of specified data bag; Then read 4 byte datas if desired again, till data class being judged; After specified data bag kind, therefrom extract the packet size field, read the respective byte quantity data according to the size of this packet; If the packet of the type is not the type of data packet of hoping processing, then directly skip this segment data, handle the data of back; Then, according to the definition of this kind data packet format in IEEE 1394 standards, contrasting data obtains each data field value corresponding in the packet; At last, each data field and value corresponding thereof are write in the file successively, accomplish the last handling process of data.
The invention has the advantages that:
(1) can receive all packets on 1394 buses.No matter packet is the sort of type, and no matter packet is that which node on the bus sends, and mail to which node, and no matter which grade is the speed of packet be, no matter when packet appears at, and this equipment can both correctly intactly receive.(2) captured in real time and store all data for a long time.Because the present invention adopts and the integrated data acquisition and the memory technology of high speed, the high-speed data of 1394 bus 400Mbps can both correctly intactly directly be stored on the storage medium such as hard disk, rather than temporarily stores in the internal memory.Therefore, as long as the capacity of storage mediums such as hard disk is enough big, the time of the present invention's record just can long enough.And storage mediums such as hard disk can expand and online expansion when needed at any time.All packets on can long record 1394 buses are that data record, fault location and the system verification in the 1394 bus system uniting and adjustment processes provides means.(3) Data Post unit; Can be according to user's needs; From the bus initial data of enormous amount, pick out the data of care, it is treated as easy recognition data bag, and parse the content of each data field in the packet; And the various statistic of packet is provided, so that analyze the signal intelligence of bus.
Description of drawings
Fig. 1 is the functional schematic of IEEE1394 bus data register system of the present invention;
The 1394 Bus Interface Unit composition function module map that Fig. 2 IEEE1394 bus data of the present invention register system adopts;
The 1394 bus links layer controller function composition frame charts that Fig. 3 1394 Bus Interface Units of the present invention comprise;
The high-speed data acquisition unit composition frame chart that Fig. 4 IEEE1394 bus data of the present invention register system adopts;
The data record method flow chart of steps of Fig. 5 IEEE1394 bus data of the present invention register system;
The Data Post method step flow chart of Fig. 6 IEEE1394 bus data of the present invention register system.
Embodiment
Below in conjunction with accompanying drawing summary of the invention is done detailed elaboration:
Shown in accompanying drawing 1, this figure is the functional block diagram of a kind of 1394 bus data register systems provided by the invention, and this system makes up based on PC or work station again.1394 bus data register systems comprise: 1394 interface units 1 are used to receive all packets on 1394 buses; High-speed data acquisition unit 2, high speed disk interfaces unit 3, memory cell 4 and post-processing unit 7.They all insert in the PC mainboard PCI slot, are connected on the pci bus 6, and need the support of PC Installed System Memory and CPU etc. during this system works.
1394 Bus Interface Units 1 are main by 1394 general bus physical layer controllers and 1394 special bus links layer controller forming circuit plates.1394 general bus links layer controller can only receive the packet that the destination is self; The packet of other nodes all can " be thrown away "; And 1394 special bus links layer controller can receive all packets, and no matter packet rs destination ground is which node on the bus.1394 Bus Interface Units 1 comprise 1394 link layer controllers 11 and 1394 bus physical layer controllers 12.1394 link layer controllers 11 link to each other with 1394 bus physical layer controllers, 12 signals, and concrete on-link mode (OLM) is as shown in Figure 2.Wherein 1394 bus links layer controller 11 can receive all packets on 1394 buses; No matter whether this packet sends to these 1394 Bus Interface Units, but and the name of this unit REFERENCE TO RELATED people application be called the application documents of " a kind of IEEE 1394 link layer controllers ".
High-speed data acquisition unit 2, all data that can receive from 1394 Bus Interface Units with sufficiently high speed collection, and give storage unit in high speed with these transfer of data.
High-speed data memory cell 3 can store the high-speed data that collects on the hard disk into sufficiently high speed.
Memory cell 4 is media of storage, and all data of 1394 buses have been preserved in this unit, and can in needs, be come out by retaking of a year or grade, carry out reprocessing.
Post-processing unit 7 resolves to each packet with all data files that receive, and parses the content of each data field according to the definition of each packet, and the various statistic of packet is provided simultaneously.
1394 Bus Interface Units 1 can design and write the IP (intellectual property) with all packet functions of reception voluntarily and on FPGA (field programmable gate array), realize.This embodiment has the advantage easily of upgrading, and functions such as packet is cut apart, timestamp can be provided.The functional block diagram of this intellectual property is as shown in Figure 3.Interface and the pin that this special chip is outside and do not possess general-purpose chip (the link layer controller TSB12LV32 of TI company production of this function; The name of this chip is called " General Purpose 1394 Link layer Controller ", promptly general 1394 link layer controllers) in full accord.
Other 1394 bus links layer controller 11, compatible fully with the link layer controller TSB12LV32 that Texas Instrument produces.As shown in Figure 3, the 1394 bus links layer controller 11 that the present invention adopts comprise link layer and physical layer interface unit 111, data buffer storage unit 112, processing data packets unit 113, control register unit 114, high speed interface unit 115 and control interface unit 116 are formed.Link layer physical layer interface 111 provides IEEE1394 bus specified standard interface; All packets and state information on the bus all are forwarded to chip through this interface by physical layer, but said chip referenced patent application number is " a kind of IEEE 1394 link layer controllers " promptly 11 and " a kind of programmable IEEE 1394 bus monitoring system and monitoring method " two pieces of chips that patent document is put down in writing.Link layer physical layer interface 111 is connected with data buffer storage unit 112, is made up of asynchronous FIFO, plays data buffering and synchronous effect, and is updated directly into control register unit 114 to bus state.Processing data packets unit 113 is connected with the data buffer storage unit 112 at the upper reaches, is connected with the high speed interface module 115 in downstream, also is connected with control register unit 114 simultaneously, and its function is controlled register 114 parameter control is set.Processing data packets unit 113 is provided with the information such as numerical value in the packet kind that requires record and storage, length, particular data territory according to the user, the various packets that selectively or all transmit on the record trunks, and be forwarded to high speed interface unit 115.Simultaneously, this unit can also provide information such as packet capture time.Control interface unit 116 is used for being connected with ppu, realizes the function setting to 1394 link layer controllers 11.High speed interface unit 115 is connected with processing data packets unit 113, and the high-speed interface of a data output is provided.In the present embodiment, the Data Mover interface of this interface and TSB12LV32 is in full accord.Phy controller 12 in 1394 Bus Interface Units directly uses general phy controller to get final product.This controller can be selected any a product in the market for use in theory.But, consider that phy controller has directly determined the port number of 1394 EBIs, therefore, the TSB41AB3 that can adopt TIX to produce.
High-speed data acquisition unit 2 be used to gather all packets that receive through 1394 EBIs.The present invention is based on PC or work station structure, and therefore, the concrete effect of high-speed data acquisition unit is forwarded to packet on the pci bus according to the PCI agreement exactly.Execution mode will combine the basic structure of PC or work station.All functional modules all are based on pci bus or PCIe bus in present PC or the work station, and PCI or PCIe have much larger than the speed of 1394 buses, therefore can accomplish the collection of high-speed data.The pci bus that present embodiment adopts.
As shown in Figure 4, high-speed data acquisition unit 2 comprises high speed interface module 21, data cache module 22 and PCI bridge module 23.High speed interface module 21 is used to receive the high speed packet that 1394 bus data interface units are caught, because data rate is higher, should adopt parallel Data Input Interface, and bit wide is 32.Data cache module 22 is used for metadata cache with synchronously, mainly adopts FIFO to realize that the largest buffered data volume is not less than the 16K byte.PCI bridge module 23 is accomplished the conversion of PCI agreement, and high-speed data is sent on the pci bus of main frame according to the PCI agreement.The PCI module can use special-purpose PCI bridging chip or IP kernel to realize.The execution mode of this unit both can design voluntarily, also can adopt capture card finished product on the market, products such as the PCI7300A data collecting card of ADLINK company.
The double buffering pattern is adopted in high-speed data acquisition, also can be described as the cyclic buffer pattern.The buffering area here refers to the internal memory of system.The double buffering pattern can be used internal memory in a small amount, and collecting almost is unlimited many data.The principle of this mode of operation is: the buffering area that is used for continuous input operation logically has been divided into two parts that equate fully (following will divide another name they be first half buffering area and second half buffering area); During work; Capture card at first writes the data that collect in first half buffering area; When capture card began in second half buffering area, to write data, application program can be done specific processing to the data in first half buffering area as required: after second half buffering area write completely, capture card will turn back to the section start of first half buffering area; Mode with secondary data before covering writes data in first half buffering area.The process that whole data collection is handled can so constantly circulate and go on.
High speed disk interfaces unit 3 is used to mate the interface of high speed hard-disk.When 1394 buses are carried out data capture, high-speed data acquisition unit 2, in the high-speed data memory cell 4, the speed of any one unit is lower, all can restrict the speed of whole system storage.The hard disk of memory cell 4 speed often is lower.The storage speed of hard disk depends on the access speed of the rotating speed and the magnetic head of interface rate, disk; But the rotation of magnetic head and magnetic sheet is the action of machinery; Be difficult to reach flank speed; So can only select the rotating speed high hard disk of trying one's best, must all reduce to minimum to other factors that will influence hard disk speed through special method simultaneously.For example, the hard disk of scsi interface.Concrete implementation method can directly adopt SCSI hard disk control card on the market.The Bus Speed of testing when reality is lower, and when the contradiction that the storage of hard disk is lower was outstanding, this unit can omit, and can directly the data that collect in the internal memory be write hard disk through Windows operating system.
Hard disk or hard disk array 4.In order to realize higher memory rate, hard disk can adopt the higher hard disk of rotating speed index, and present embodiment has adopted rotating speed greater than 10000 rpms hard disk.The interface of hard disk can adopt the interface of higher rate, for example, has the hard disk of scsi interface.When the Bus Speed of reality test is lower, when the contradiction that the storage of hard disk is lower is not outstanding, can adopt general hard disk.
Installed System Memory 5 is internal memories of PC or industrial computer.
Also need the control of actuation step, Equipment Control step and Data Post step and man-machine interaction step to the work of IEEE1394 bus data register system provided by the invention.
Wherein, initialization (driving) method: the high-speed data acquisition unit is provided with appropriate data rate and buffer area through PC or embedded type CPU; Make hardware device be in and wait for the pattern that receives order.
Apparatus control method: through the man-machine interface setting and select storing data files size, memory location, need the type of data packet of reprocessing.Through clicking the button at interface, the beginning data record; Through clicking conclusion button, end data record; Through clicking the reprocessing button, begin to carry out data record.
As shown in Figure 5, this figure is the workflow diagram that IEEE1394 bus data record provided by the invention is.Specifically describe as follows:
1) at first, device power-on, 1394 Bus Interface Chips in the IEEE1394 bus data register system of the present invention mode of operation automatically are set to receive all data, do not need artificial the setting and intervention.At this moment, 1394 Bus Interface Units have begun to have received all packets on the bus;
2) secondly, according to system resource, it is receiving mode and the size that buffering area is set that the high speed acquisition unit is set;
3) then, be arranged on the size of the data file of storing on the hard disk, the disk partition of storage through man-machine interface;
4) then, click " startup ", start the high speed acquisition unit, begin to receive 1394 Bus Interface Units and receive packet; On disk, generate simultaneously a raw data file, in the time of the size of the data file that is provided with to the front when data accumulation, data file is closed in the storage of completion data on disk; Generate new data file simultaneously, this step continues always;
5) when not needing again record data, click " end ", the high-speed data acquisition unit no longer receives the packet that 1394 Bus Interface Units receive, also storing data files on disk not;
6) last; Select the type of the 1394 bus data bags that a kind of, multiple or whole hope handle in man-machine interface, click " reprocessing " button, the system that PC or other have CPU begins raw data file is read from disk; In internal memory, handle, concrete processing method is seen Fig. 6.Data after will handling again after disposing with the stored in form of file to disk.Whole process finishes.
The Data Post method step flow chart of Fig. 6 IEEE1394 bus data of the present invention register system, post-processing approach step provided by the invention is following:
All data files that 1) at first will receive are opened through PC or industrial computer or other equipment with CPU;
2) then, CPU reads the data content of file successively.The packet header of whenever reading the various packets of 4 byte datas and IEEE 1394 standard definitions compares the kind of specified data bag; Then read 4 byte datas if desired again, till data class being judged;
3) after specified data bag kind, therefrom extract the packet size field, read the respective byte quantity data according to the size of this packet; If the packet of the type is not the type of data packet of hoping processing, then directly skip this segment data, handle the data of back;
4) then, according to the definition of this kind data packet format in IEEE 1394 standards, contrasting data obtains each data field value corresponding in the packet;
5) last, each data field and value corresponding thereof are write in the file successively, accomplish the last handling process of data.
It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is specified with reference to embodiment; Those of ordinary skill in the art is to be understood that; Technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and the scope of technical scheme of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (15)
1. IEEE 1394 bus data recording processing systems, this system are used to catch all packets and real-time storage on 1394 buses back and data are carried out reprocessing on the memory cell, comprise:
1394 interface units, this interface unit further comprise 1394 link layer controllers and 1394 bus physical layer chips, are used to receive all packets on 1394 buses;
The high-speed data acquisition unit is used for all data that receive from said 1394 Bus Interface Unit collections;
The high-speed data memory cell is used for storing the data that collect into hard disk with sufficiently high speed;
Memory cell is used to preserve all data of 1394 buses, and in needs, is come out by retaking of a year or grade, carries out reprocessing; With
Post-processing unit is used for the 1394 bus initial data of noting are carried out reprocessing, is processed into and is convenient to the recognition data packet format, and parse the content of each data field in the packet;
Wherein, said 1394 interface units, high-speed data acquisition unit, high speed disk interfaces unit and memory cell are all inserted in the PC mainboard internal bus slot, or on the local bus of embedded device, adopt bus to intercom mutually; And said IEEE 1394 bus data recording processing systems also comprise PC Installed System Memory and CPU.
2. IEEE according to claim 1 1394 bus data recording processing systems; It is characterized in that said 1394 link layer controllers comprise: HPI, link layer nucleus module, data buffering and routing module control, high speed interface module and configuration register; Outer CPU can be read and write the data buffer zone in configuration register, access data buffering and the routing module control through described HPI; Described data buffering and routing module control are between link layer nucleus module and HPI and the high speed interface; Be used to provide different transceive data interchannel switching controls; Wherein, Described data buffering and routing module control have also used two asynchronous first-in/first-out memories, are respectively applied for the buffering and the cross clock domain synchronization of data of transceive data; Described configuration register is used to provide initial configuration and the control to link layer nucleus module, data buffering and routing module control, implements to control and obtain the operating state of each module of link layer controller through described HPI read-write configuration register;
Described link layer nucleus module is used for realizing comprising all functions of IEEE1394 bus protocol link layer: physical layer link layer interface, data buffering processing unit, data packet transceive unit, cyclic-redundancy-check unit and cycle controller;
Described physical layer link layer interface is used to provide the link layer of IEEE1394 bus protocol regulation and the standard interface between physical layer;
Described data buffering processing unit uses an asynchronous first-in/first-out memory as the transceive data bag data buffering function to be provided;
Described data packet transceive unit is the core of link layer nucleus module, links to each other with routing module control with data buffering processing unit, cyclic-redundancy-check unit, cycle controller and data buffering through bidirectional data line;
Said cyclic-redundancy-check unit, the CRC function when being used to transceive data is provided;
Said cycle controller comprises cycle timer and cycle monitor, service when being used for waiting;
When sending packet, the packet that writes specified format through HPI is to data buffering and routing module control; Realize the control of buffering, multi-clock zone synchronization of data and the data route of data again through the asynchronous first-in/first-out memory of data buffering and routing module control; Then, get into the link layer nucleus module, carry out the framing and the CRC of data according to the form of different types of data bag in the IEEE1394 bus protocol; Send the bus application of respective type at last to physical layer through the physical layer link layer interface; After this link layer chip place node obtains bus control right, begin to transmit packet to universal serial bus according to the speed of appointment through the physical layer link layer interface;
After packet send to be accomplished,, wait for then that destination node is returned and confirm bag,, also can produce and send circulation and begin to wrap bus if this link layer control chip place node is a cycle controller if what send is non-Broadcasting-Asynchronous bag;
When receiving packet; Transmit through physical layer link layer interface reception physical layer; Data packets for transmission on universal serial bus, at the link layer nucleus module, said data packet transceive unit carries out the decoding of address and type of data packet to the packet that receives; If the destination node of this packet is not this node, then the reception of forgo data bag; Otherwise; Begin to receive packet and carry out CRC check; Like the then reception of forgo data bag of check errors, then output to data buffering and routing module control to the data that receive according to the form of appointment as correct, in this module, accomplish multi-clock zone synchronization of data and buffering; And, arrive transaction layer or application program through the HPI dateout according to route control; If what receive is non-Broadcasting-Asynchronous bag, after the completion packet received, the link layer nucleus module returned an affirmation and wraps universal serial bus.
3. IEEE according to claim 1 1394 bus data recording processing systems is characterized in that said IEEE 1394 bus data register systems also comprise: display unit.
4. IEEE according to claim 1 1394 bus data recording processing systems is characterized in that all packets on said 1394 buses comprise: master data bag, physical layer data bag and response data packet.
5. IEEE according to claim 3 1394 bus data recording processing systems is characterized in that,
Said master data bag comprises: asynchronous nybble is write request package; The asynchronous data piece is write request package, asynchronous write respond packet, asynchronous nybble read request packet; Asynchronous data piece read request packet; Asynchronous nybble is read respond packet, and the asynchronous data piece is read respond packet, the asynchronous data piece read respond packet, circulation begin bag, locking request bag, asynchronous flow bag, etc. the time bag and lock respond packet;
Said physical layer data bag comprises: the physical layer data bag comprises: tagging packet, unlatching link bag, physical layer configurations bag, the logical bag of examination, remote access bag, long-range response packet, remote command bag, remote acknowledgement bag and recovery bag.
6. IEEE according to claim 1 1394 bus data recording processing systems is characterized in that the memory capacity of said memory cell can be expanded.
7. IEEE according to claim 1 1394 bus data recording processing systems is characterized in that, said high speed interface module adopts parallel Data Input Interface, and bit wide is 32.
8. IEEE according to claim 1 1394 bus data recording processing systems is characterized in that, the double buffering pattern is adopted in said high-speed data acquisition.
9. IEEE according to claim 1 1394 bus data recording processing systems is characterized in that, said memory cell adopts hard disk or hard disk array.
10. IEEE according to claim 8 1394 bus data recording processing systems is characterized in that, said hard disk adopts rotating speed greater than 10000 rpms hard disk, and the interface of hard disk adopts the hard disk with scsi interface.
11. IEEE 1394 bus data recording processing methods, this method adopts the described system of claim 1, comprises: the step of data record and the step of carrying out reprocessing to data recorded:
Wherein, the step of said data record further comprises following steps:
1) 1394 Bus Interface Chip mode of operations are set to receive all data;
2) according to system resource, it is receiving mode and the size that buffering area is set that the high speed acquisition unit is set;
3) size of the data file of storing on the hard disk and the disk partition of storage are set;
4) start the high speed acquisition unit, begin to receive 1394 Bus Interface Units and receive packet; On disk, generate simultaneously a raw data file, in the time of the size of the data file that is provided with to the front when data accumulation, data file is closed in the storage of completion data on disk; Generate new data file simultaneously, this step continues always;
5) when not needing record data, said high-speed data acquisition unit no longer receives the packet that 1394 Bus Interface Units receive again, and disk stops storing data files simultaneously;
Said Data Post step further comprises following steps:
All data that at first will receive are opened; Then, CPU reads the data content of file successively; The packet header of whenever reading the various packets of 4 byte datas and IEEE 1394 standard definitions compares the kind of specified data bag; Then read 4 byte datas if desired again, till data class being judged; After specified data bag kind, therefrom extract the packet size field, read the respective byte quantity data according to the size of this packet; If the packet of the type is not the type of data packet of hoping processing, then directly skip this segment data, handle the data of back; Then, according to the definition of this kind data packet format in IEEE 1394 standards, contrasting data obtains each data field value corresponding in the packet; At last, each data field and value corresponding thereof are write in the file successively, accomplish the last handling process of data.
12. IEEE 1394 bus data recording processing methods according to claim 11 is characterized in that all packets on said 1394 buses comprise: master data bag, physical layer data bag and response data packet.
13. IEEE 1394 bus data recording processing methods according to claim 11 is characterized in that,
Said master data bag comprises: asynchronous nybble is write request package; The asynchronous data piece is write request package, asynchronous write respond packet, asynchronous nybble read request packet; Asynchronous data piece read request packet; Asynchronous nybble is read respond packet, and the asynchronous data piece is read respond packet, the asynchronous data piece read respond packet, circulation begin bag, locking request bag, asynchronous flow bag, etc. the time bag and lock respond packet;
Said physical layer data bag comprises: the physical layer data bag comprises: tagging packet, unlatching link bag, physical layer configurations bag, the logical bag of examination, remote access bag, long-range response packet, remote command bag, remote acknowledgement bag and recovery bag.
14. IEEE 1394 bus data recording processing methods according to claim 11 is characterized in that the memory capacity of said memory cell can be expanded.
15. IEEE 1394 bus data recording processing methods according to claim 11 is characterized in that, said memory cell adopts hard disk or hard disk array.
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