CN114327298A - FPGA (field programmable Gate array) -based method for simulating SSM (System management Module) configuration interface and SSM configuration interface - Google Patents

Abstract

The invention provides a method for simulating an SSM configuration interface based on an FPGA and the SSM configuration interface, wherein a data reading interface, a first asynchronous buffer for caching configuration code stream data read from the data reading interface and a write control circuit module for writing data into a high-bandwidth memory are arranged on a circuit for simulating the FPGA for simulating the SSM configuration interface; the read control circuit module is provided with a second asynchronous buffer and reads data to the second asynchronous buffer; and a data interface connected with the configured FPGA is also arranged, and the configuration bit width of the data interface is set by the analog FPGA. During configuration, the configuration bit width of the high-bandwidth memory and the data interface is freely set, so that the configuration interface of the analog SSM with high frequency and large bit width can be realized. By arranging the configuration clock circuit on the analog FPGA, the configuration speed can be adjusted by changing the frequency of the configuration clock, and further, the high-frequency configuration can be realized.

Description

FPGA (field programmable Gate array) -based method for simulating SSM (System management Module) configuration interface and SSM configuration interface

Technical Field

The invention belongs to the technical field of programmable gate arrays, and particularly relates to a method for simulating an SSM configuration interface based on an FPGA and the SSM configuration interface.

Background

A Field Programmable Gate Array (FPGA) is a large scale programmable device consisting of an array of different types of programmable blocks (logic, input output and others) that can use pre-fabricated routing channels and programmable fast-turn flexible interconnections between them. The configuration of the wiring switches and the functions of all FPGA blocks is controlled using millions of SRAM cells which are programmed to perform a particular function when in operation. A user compiles a functional design required by the description of the hardware description language into a code stream file for programming all configuration SRAMs of the FPGA, and the system programmability or reconfigurability is provided for the user.

Because the traditional slave SelectMap mode configuration FPGA is realized by a PROM or SDLlink analog configuration interface, the frequency and bit width of a configuration clock are greatly limited. The design process of the PROM configuration FPGA based on the traditional SlaveSelectMap is simple and convenient, but the configuration method has the following problems: a. the method comprises the steps of setting a PROM chip, setting a configuration clock, wherein the PROM chip is limited by the PROM chip, the bit width is only 8 to the maximum, the bit width is fixed and not selectable, b, the configuration clock is only 40Mhz to the maximum, c, when the FPGA needing to be configured is large, the configuration code stream is also enlarged, the maximum capacity of the PROM is only 4MB, the capacity of the PROM is exceeded, at the moment, the small FPGA needs to be replaced and used, and the function requirement can not be met. Multiple PROMs can also be cascaded, but PROMs are costly and uneconomical to cost.

The design process of configuring the FPGA based on the SDlink of the traditional SlaveSelectMap has the following problems: a. b, reading the SDcard, because of the limitation of a clock and the bit width, the bandwidth is small, the maximum speed is 40mbit/s in serial configuration, the maximum speed is 160mbit/s in parallel configuration, and the FPGA cannot be rapidly configured.

Disclosure of Invention

The invention aims to solve the technical problem of how to provide an extensible large-bit-width high-frequency configuration interface SlaveSelectMap with parameterized bit width, and provides a method for simulating an SSM configuration interface based on an FPGA and the SSM configuration interface.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows:

a method for simulating SSM configuration interface based on FPGA includes the following steps:

step 1: the circuit of the analog FPGA is provided with a data reading interface, a first asynchronous buffer FIFO _0 for caching configuration code stream data read from the data reading interface and a write control circuit module for reading the configuration code stream data from the first asynchronous buffer FIFO _0 to a high-bandwidth memory;

step 2: the circuit of the analog FPGA is also provided with a second asynchronous buffer FIFO _1 and a read control circuit module which is used for reading configuration code stream data from the high-bandwidth memory to the second asynchronous buffer FIFO _ 1;

and step 3: and when the FPGA is configured, starting a configuration clock circuit, reading configuration code stream data from the high-bandwidth memory to a second asynchronous buffer FIFO _1, reading the configuration code stream data from the second asynchronous buffer FIFO _1 through a data interface by the configured FPGA to configure the configured FPGA, and setting the configuration bit width of the data interface by the analog FPGA.

Further, in step 3, when the configuration code stream data is read from the high bandwidth memory to the second asynchronous buffer FIFO _1, it is first determined whether the storage state of the second asynchronous buffer FIFO _1 is full, and when not full, a code stream with a length of 1 burst is read from the DDR and stored into the FIFO _1, until the configuration code stream data in the high bandwidth memory is completely read, and when full, the configuration code stream data is stopped from being read.

Further, the configuration code stream data is burned on the nonvolatile memory.

Further, the non-volatile memory is a flash.

And further reading the configuration code stream data from a nonvolatile memory to the first asynchronous buffer FIFO _0, reading the configuration code stream data from the first asynchronous buffer FIFO _0 to a high-bandwidth memory, and realizing the cross-clock processing of the data by using an FIFO method.

Further, when the configuration code stream data is read from the high-bandwidth memory to the second asynchronous buffer FIFO _1 in step 3, the configuration code stream data is read from the second asynchronous buffer FIFO _1 to the configured FPGA through the data interface, and the FIFO method is used to implement the cross-clock processing.

Further, in step 3, when the configured FPGA reads configuration code stream data from the second asynchronous buffer FIFO _1 to configure the configured FPGA, when the second asynchronous buffer FIFO _1 is not empty, data is continuously read from the second asynchronous buffer FIFO _1 and transmitted to the configured FPGA for configuration.

Further, after the data transmission of the configuration code stream transmitted from the second asynchronous buffer FIFO _1 is completed, if the identification signal done that is successfully configured is raised, the configured FPGA is successfully configured, otherwise the configured FPGA is failed to be configured.

Further, the high bandwidth memory is a double data rate synchronous dynamic random access memory (DDR) memory.

The invention also provides an SSM configuration interface, which comprises an analog FPGA for simulating the SSM configuration interface, wherein a data reading interface is arranged on a circuit of the analog FPGA, a first asynchronous buffer FIFO _0 for caching configuration code stream data read from the data reading interface and a write control circuit module for reading the configuration code stream data from the first asynchronous buffer FIFO _0 to a high-bandwidth memory are also arranged on the circuit of the analog FPGA;

the circuit of the analog FPGA is also provided with a second asynchronous buffer FIFO _1 and a read control circuit module which is used for reading configuration code stream data from the high-bandwidth memory to the second asynchronous buffer FIFO _ 1;

the circuit of the analog FPGA is provided with a data interface connected with the configured FPGA, the configuration bit width of the data interface is set by the analog FPGA, and the circuit of the analog FPGA is also provided with a circuit for starting a configuration clock.

By adopting the technical scheme, the invention has the following beneficial effects:

according to the method for simulating the SSM configuration interface based on the FPGA and the SSM configuration interface, the configuration code stream data is read from the nonvolatile memory into the high-bandwidth memory DDR in advance, when configuration is needed, the configuration clock circuit is started, the configuration code stream data is read from the high-bandwidth memory DDR to be configured, the data interface is arranged on the simulation FPGA, the configuration bit width of the data interface can be set by the simulation FPGA, and the configuration interface of the simulation SSM with high frequency and large bit width can be realized due to the fact that the high bandwidth of the DDR and the configuration bit width of the data interface are freely set. By arranging the configuration clock circuit on the analog FPGA, the configuration speed can be adjusted by changing the frequency of the configuration clock, and further, the high-frequency configuration can be realized.

Drawings

FIG. 1 is a flow chart of the system of the present invention;

FIG. 2 is a schematic diagram of an SSM configuration interface according to the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The first embodiment is as follows:

fig. 1 shows a method for simulating an SSM configuration interface based on an FPGA according to the present invention, which includes the following steps:

step 1: the circuit for simulating the FPGA of the SSM configuration interface is provided with a data reading interface, and the circuit for simulating the FPGA is also provided with a first asynchronous buffer FIFO _0 for caching the configuration code stream data read from the data reading interface, and a write control circuit module for reading the configuration code stream data from the first asynchronous buffer FIFO _0 to a high-bandwidth memory. And the configuration code stream data is stored in the high-bandwidth memory in advance through the data reading interface by the first asynchronous buffer FIFO _0 and the write control circuit module.

In this embodiment, the configuration code stream data is burned on the nonvolatile memory, and in this embodiment, the nonvolatile memory is a flash memory, and the nonvolatile memory is used, so that the configuration code stream data is not lost after power failure and is convenient to store.

When the configuration code stream data is read from the nonvolatile memory flash to the first asynchronous buffer FIFO _0 through the data reading interface, the configuration code stream data is read from the first asynchronous buffer FIFO _0 to the high-bandwidth memory, the cross-clock processing of the data is realized by using the FIFO method, and because the clock for reading the configuration code stream data from the nonvolatile memory and the clock for writing the configuration code stream data to the high-bandwidth memory are inconsistent, the cross-clock processing of the data is realized by using the FIFO method. The FIFO _0 is reset before the configuration code stream data is read to the first asynchronous buffer FIFO _0, so that the influence of the last exception is avoided.

The read switch is arranged on the analog FPGA, the configuration code stream data in the flash is read firstly, and the configuration code stream data is cached in the high-bandwidth memory DDR in advance. During configuration, a configuration circuit clock is started, data is read from a high-bandwidth memory DDR for configuration, and the purpose is mainly to utilize the high bandwidth of the DDR so that configuration code stream data can be quickly read from the DDR to a configured FPGA to realize quick configuration.

Step 2: the circuit of the analog FPGA is also provided with a second asynchronous buffer FIFO _1 and a read control circuit module used for reading configuration code stream data from the high-bandwidth memory to the second asynchronous buffer FIFO _ 1.

The invention uses the high bandwidth memory DDR, therefore, the configuration code stream data is read from the nonvolatile memory and stored in the DDR in advance, during configuration, the configuration code stream data is read from the high bandwidth memory DDR, during reading, because the frequency of the configuration clock is different from the clock frequency of the data read from the DDR, the second asynchronous buffer FIFO _1 is set as buffer, the configuration code stream data is read from the high bandwidth memory to the second asynchronous buffer FIFO _1 by using the read control circuit module, then the configuration code stream data is read from the second asynchronous buffer FIFO _1 through the data interface to the configured FPGA, and the FIFO method is used for realizing the cross-clock processing.

And step 3: and when the FPGA is configured, starting a configuration clock circuit, reading code stream data from the high-bandwidth memory to a second asynchronous buffer FIFO _1, reading configuration code stream data from the second asynchronous buffer FIFO _1 through a data interface by the configured FPGA, and configuring the configured FPGA, wherein the configuration bit width of the data interface is set by the analog FPGA. Because the configuration code stream data is read from the DDR, the high bandwidth of the DDR and the configuration bit width of the data interface are added, and the frequency of the configuration clock is set, the configuration speed can be accelerated, and the configuration time is reduced. By using the high bandwidth of the DDR, the bandwidth of the DDR is larger than or equal to the configuration bit width to configure the clock frequency, and the configuration bit width can generally select 8 bits, 16 bits or 32 bits, so that the configuration speed is much faster than that of the direct configuration of a nonvolatile memory flash, a PROM and the like, and the configuration period is shortened. The configuration bit width of the data interface is set by the analog FPGA, so that the configuration bit width parameterization and bit width expansion requirements can be met.

In this embodiment, when the configuration code stream data is read from the high bandwidth memory DDR to the second asynchronous buffer FIFO _1, it is first determined whether the storage state of the second asynchronous buffer FIFO _1 is full, and when the storage state is not full, a code stream with a length of 1 burst is read from the high bandwidth memory DDR and stored into the FIFO _1, until the configuration code stream data in the DDR is completely read, and when the storage state is full, the configuration code stream data is stopped from being read. In order to prevent the data in the second asynchronous buffer FIFO _1 from overflowing, the storage state of the second asynchronous buffer FIFO _1 is monitored, and as long as the second asynchronous buffer FIFO _1 is not full, namely full, the data is continuously read from the DDR until the configuration code stream data is completely read. Before the configuration code stream data is read to the second asynchronous buffer FIFO _1, the second asynchronous buffer FIFO _1 needs to be reset, so that the influence of the last abnormity is avoided.

In this embodiment, when the configured FPGA reads configuration code stream data from the second asynchronous buffer FIFO _1 to configure the configured FPGA, when the second asynchronous buffer FIFO _1 is not empty, data is continuously read from the second asynchronous buffer FIFO _1 and transmitted to the configured FPGA for configuration.

In this embodiment, after the transmission of the code stream data transmitted from the second asynchronous buffer FIFO _1 is completed, if the successfully configured identification signal done is raised, the configured FPGA is successfully configured, otherwise, the configured FPGA is failed to be configured.

The method can update the content of the flash of the nonvolatile memory at any time according to the user requirement, and further update the content of the configuration code stream in the DDR. After the content of the configuration code stream in the DDR is updated, a user can start configuration at any time, and the configured FPGA can be configured without time limitation, so that different requirements are met.

Example two:

the invention also provides an SSM configuration interface based on the configuration method, as shown in FIG. 2, the SSM configuration interface comprises an analog FPGA for simulating the SSM configuration interface, a data reading interface is arranged in a circuit of the analog FPGA, a first asynchronous buffer FIFO _0 for caching configuration code stream data read from the data reading interface and a write control circuit module for reading the configuration code stream data from the first asynchronous buffer FIFO _0 to a high-bandwidth memory are also arranged in the circuit of the analog FPGA.

In this embodiment, the configuration code stream data is read in advance to the high bandwidth memory through the data reading interface, and since the configuration code stream reading clock is inconsistent with the clock for writing the configuration code stream data to the high bandwidth memory, the first asynchronous buffer FIFO _0 is used, and the FIFO method is used to implement the cross-clock processing of the data. And setting a write control circuit module, and writing the configuration code stream data into the high-bandwidth memory. The high-bandwidth memory in the embodiment is used for pre-storing configuration code stream data, and can be read and stored at any time by using idle time.

The circuit of the analog FPGA is also provided with a second asynchronous buffer FIFO _1 and a read control circuit module used for reading configuration code stream data from the high-bandwidth memory to the second asynchronous buffer FIFO _ 1. In this embodiment, a second asynchronous buffer FIFO _1 and a read control circuit module are provided, and configuration code stream data is read from the high-bandwidth memory to the second asynchronous buffer FIFO _1 through the read control circuit module, and then the configuration code stream data is read from the second asynchronous buffer FIFO _1 to the configured FPGA.

The circuit of the analog FPGA is provided with a data interface connected with the configured FPGA, the configuration bit width of the data interface is set by the analog FPGA, and the circuit of the analog FPGA is also provided with a circuit for starting a configuration clock.

In this embodiment, during configuration, the configuration circuit clock is started, and data is read from the DDR of the high bandwidth memory to perform configuration, so that the purpose of the configuration circuit clock is to use the high bandwidth of the DDR to quickly read configuration code stream data from the DDR to the configured FPGA, thereby realizing quick configuration. The principle is that the configuration code stream data is read from the DDR, the high bandwidth of the DDR and the configuration bit width of the data interface are combined, and the frequency of a configuration clock is set, so that the configuration speed can be increased, and the configuration time can be shortened. The DDR bandwidth is larger than or equal to the configuration bit width and the configuration clock frequency, and the configuration bit width can be generally 8 bits, 16 bits or 32 bits, so that the configuration speed is much faster than that of a nonvolatile memory flash, a PROM and the like, and the configuration period is shortened. In addition, the configuration bit width of the data interface is set by the analog FPGA, so that the configuration bit width parameterization and bit width expansion requirements can be met.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for simulating SSM configuration interface based on FPGA is characterized by comprising the following steps:

step 1: the circuit of the analog FPGA is provided with a data reading interface, a first asynchronous buffer FIFO _0 for caching configuration code stream data read from the data reading interface and a write control circuit module for reading the configuration code stream data from the first asynchronous buffer FIFO _0 to a high-bandwidth memory;

step 2: the circuit of the analog FPGA is also provided with a second asynchronous buffer FIFO _1 and a read control circuit module which is used for reading configuration code stream data from the high-bandwidth memory to the second asynchronous buffer FIFO _ 1;

and step 3: and when the FPGA is configured, starting a configuration clock circuit, reading configuration code stream data from the high-bandwidth memory to a second asynchronous buffer FIFO _1, reading the configuration code stream data from the second asynchronous buffer FIFO _1 through a data interface by the configured FPGA to configure the configured FPGA, and setting the configuration bit width of the data interface by the analog FPGA.

2. The method according to claim 1, wherein in step 3, when reading the configuration code stream data from the high bandwidth memory to the second asynchronous buffer FIFO _1, it is first determined whether the storage state of the second asynchronous buffer FIFO _1 is full, and when not full, 1 burst length of code stream is read from the DDR and stored in the FIFO _1, until the configuration code stream data in the high bandwidth memory is completely read, and when full, the configuration code stream data reading is stopped.

3. The method of claim 1, wherein the configuration code stream data is burned on a non-volatile memory.

4. The method of claim 3, wherein the non-volatile memory is a flash.

5. The method according to claim 4, wherein the configuration code stream data is read from the nonvolatile memory to the first asynchronous buffer FIFO _0 through a data reading interface, and then the configuration code stream data is read from the first asynchronous buffer FIFO _0 to a high bandwidth memory, and a FIFO method is used to implement the cross-clock processing of data.

6. The method according to claim 2, wherein in step 3, the configuration code stream data is read from the high bandwidth memory to a second asynchronous buffer FIFO _1, and then the configuration code stream data is read from the second asynchronous buffer FIFO _1 to the configured FPGA through a data interface, so as to implement cross-clock processing by using a FIFO method.

7. The method according to claim 6, wherein in step 3, when the configured FPGA reads configuration code stream data from the second asynchronous buffer FIFO _1 to configure the configured FPGA, when the second asynchronous buffer FIFO _1 is not empty, data is continuously read from the second asynchronous buffer FIFO _1 and transmitted to the configured FPGA for configuration.

8. The method according to claim 7, wherein after the data transmission of the configuration code stream transmitted from the second asynchronous buffer FIFO _1 is completed, if the identification signal done that is configured successfully is pulled high, the configured FPGA is configured successfully, otherwise the configured FPGA is configured unsuccessfully.

9. The method according to any of claims 1 to 8, characterized in that the high bandwidth memory is a double data rate synchronous dynamic random access memory, DDR, memory.

10. An SSM configuration interface is characterized by comprising an analog FPGA for simulating the SSM configuration interface, wherein a data reading interface is arranged on a circuit of the analog FPGA, a first asynchronous buffer FIFO _0 for caching configuration code stream data read from the data reading interface and a write control circuit module for reading the configuration code stream data from the first asynchronous buffer FIFO _0 to a high-bandwidth memory are further arranged on the circuit of the analog FPGA;

the circuit of the analog FPGA is also provided with a second asynchronous buffer FIFO _1 and a read control circuit module which is used for reading configuration code stream data from the high-bandwidth memory to the second asynchronous buffer FIFO _ 1;

the circuit of the analog FPGA is provided with a data interface connected with the configured FPGA, the configuration bit width of the data interface is set by the analog FPGA, and the circuit of the analog FPGA is also provided with a circuit for starting a configuration clock.

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