CN111176911A

CN111176911A - Novel large-storage-capacity high-speed FPGA auxiliary configuration system

Info

Publication number: CN111176911A
Application number: CN201911129123.4A
Authority: CN
Inventors: 李明哲; 陈雷; 李政; 李学武; 孙华波; 张帆; 李琦
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2019-11-18
Filing date: 2019-11-18
Publication date: 2020-05-19
Anticipated expiration: 2039-11-18
Also published as: CN111176911B

Abstract

The invention relates to a novel large-storage-capacity high-speed FPGA auxiliary configuration system.A configuration memory module stores an operation configuration file of a main control FPGA module in a configuration stage; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is powered on every time, and the main control FPGA module completes configuration; in a programming stage, the configuration file in the programming stage is sent to a main control FPGA module from an upper computer, the main control FPGA module completes programming control configuration, the upper computer programming module sends a configuration code stream to the main control FPGA module through a communication module, the main control FPGA module programs the configuration code stream to a code stream memory, and the system is powered off; in the configuration stage, the system is powered on, after the configuration is completed by the operation of the configuration file of the main control FPGA module, the configuration instruction sent from the outside is received, the corresponding configuration code stream is obtained from the code stream memory, and the obtained configuration code stream is sent to the FPGA to be tested through the communication module, so that the configuration of the FPGA to be tested is completed.

Description

Novel large-storage-capacity high-speed FPGA auxiliary configuration system

Technical Field

The invention relates to a novel large-storage-capacity high-speed FPGA auxiliary configuration system, and belongs to the technical field of integrated circuits.

Background

Very large Field Programmable Gate Arrays (FPGAs) with programmability contain a large number of Programmable resources, and these Programmable resources cannot be used simultaneously in one test code stream. With the progress of the process and the large increase of the circuit scale, the test code stream file is further increased. The capacity of a single code stream of the ultra-large-scale FPGA reaches dozens of megabits, and in addition, the number of code stream files required is greatly increased due to the fact that the complexity of a test structure of a device to be tested is improved to reach about 100-200, so that a certain fault coverage rate can be achieved only by carrying out configuration for hundreds of times in the test process. At present, the highest memory of equipment with higher configuration such as UltraFLEX, V93000 and the like is only 128Mbyte, files with hundreds of bits far exceed the capacity of the memory of a tester, and the capacity difference is more than 20 times, so the code stream configuration cannot be directly carried out by the tester. Meanwhile, for mass production test, hundreds of test vectors need to be tested in a short time, the configuration rate of a downloader provided by a device manufacturer is only about 12 megabits at most, and the test for completing one circuit may take one hour, so that the test cost is not of practical engineering value. Therefore, it is a challenge of the large-scale FPGA mass production test system to complete a large number of test configurations in a short time. The problem is solved, the number of the test vectors needs to be compressed, and more importantly, a special configuration auxiliary system is developed by using a high-speed configuration interface of a device, so that the speed of single configuration is increased, and the whole test system has feasibility of implementing mass production tests.

Disclosure of Invention

The technical problem solved by the invention is as follows: the system is used for the test of the mass production of the ultra-large-scale FPGA, not only solves the problems that the memory of the automatic test equipment is insufficient and a large amount of FPGA test code streams cannot be stored, but also meets the requirement of completing the high-speed configuration of the FPGA in the test of the mass production of the ultra-large-scale FPGA.

The technical scheme of the invention is as follows: a novel large-storage-capacity high-speed FPGA auxiliary configuration system comprises an upper computer programming module, a code stream memory, a main control FPGA module, a configuration memory module and a communication module, wherein the upper computer programming module runs on an upper computer;

the configuration memory module stores the operation configuration file of the main control FPGA module in the configuration stage; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is powered on every time, and the main control FPGA module completes configuration according to the operation configuration file;

in a programming stage, a configuration file in the programming stage is sent to a main control FPGA module from an upper computer, the main control FPGA module completes programming control configuration according to the configuration file in the programming stage, the upper computer programming module sends a configuration code stream to the main control FPGA module through a communication module, the main control FPGA module programs the configuration code stream to a code stream memory, and the system is powered off;

in the configuration stage, the system is powered on, after the configuration is completed by the operation of the configuration file of the main control FPGA module, the configuration instruction sent from the outside is received, the corresponding configuration code stream is obtained from the code stream memory, and the obtained configuration code stream is sent to the FPGA to be tested through the communication module, so that the configuration of the FPGA to be tested is completed.

Preferably, the FPGA type detection device further comprises an FPGA type selection module, different coded data are sent to the main control FPGA module through the FPGA type selection module, and the main control FPGA module determines the specific type of the FPGA to be detected according to the coded data; programming configuration code streams of different FPGA models in a code stream memory; and the main control FPGA module acquires a corresponding configuration code stream from the code stream memory according to the specific model for configuration.

Preferably, in the programming stage, after the configuration code stream is programmed into the code stream memory, the upper computer programming module sends a read-back check instruction to the main control FPGA module through the communication module, the main control FPGA module reads out the configuration code stream data stored in the code stream memory and sends the configuration code stream data to the upper computer through the communication module, the upper computer checks the pre-stored code stream, and if the check is qualified, the programming stage is completed, and the system is powered off; otherwise, under the configuration of the current main control FPGA module, the programming operation is carried out again until the verification is qualified.

Preferably, the code stream memory is a FLASH memory, a FLASH array is formed by a plurality of FLASH, the data signal and the control signal of each FLASH are connected with the data signal and the control signal of the main control FPGA module, and the main control FPGA module completes the reading, writing and erasing operations of each FLASH.

Preferably, in the programming stage, after the configuration of the main control FPGA module is completed, the main control FPGA module includes a control module, an FIFO module, an erasing module, a writing module, an address conversion module, and a communication control module;

the control module realizes the jump of standby state, mode judgment, handshake, erasing and writing state in a state machine mode;

the FIFO module is used for buffering data when writing operation is carried out on the code stream memory;

the address conversion module is used for determining the initial position and the end position of the current programming according to the preset configuration code stream storage address;

the erasing module is used for respectively performing erasing and writing operations on the code stream memory by the writing module under the control of the state machine; in the process of writing operation, the data is written from the FIFO module according to the starting position and the ending position determined by the address conversion module.

Preferably, in the programming stage, after the configuration of the main control FPGA module is completed, the main control FPGA module comprises a control module, an FIFO module, an erasing module, a reading module, a writing module, an address conversion module and a communication control module;

the control module realizes the jump of standby state, mode judgment, handshake, erasure, reading and writing states in a state machine mode;

the FIFO module is used for buffering data when the code stream memory is subjected to read-write operation;

the erasing module is used for respectively erasing and writing the code stream memory under the control of the state machine; in the writing operation process, the data is programmed in the slave FIFO module according to the starting position and the ending position determined by the address conversion module, and the reading operation process is used for code stream verification.

Preferably, the erasing module realizes the jump of a standby state, an unlocking instruction confirmation state, an erasing instruction confirmation state and an erasing time waiting state in a state machine mode;

when the control module enters a standby state, the erasing module simultaneously enters the standby state; when the control module enters an erasing state, the erasing module enters an unlocking instruction state from a standby state, enters an unlocking instruction confirmation state after delaying a preset time period, performs unlocking instruction operation on the code stream memory, enters an erasing instruction state after the operation is completed, enters an erasing instruction confirmation state after delaying the preset time period, performs erasing instruction operation on the code stream memory, enters an erasing time waiting state, and returns to the standby state after the time waiting is completed.

Preferably, the write module realizes the jump of a standby state, a write preparation state and a write operation state in a state machine mode;

when the control module enters a standby state, the writing module is in the standby state at the same time; when the control module enters a writing state, the writing module enters a writing preparation state and performs writing preparation operation on the code stream memory; and after the operation is finished, entering a write operation state, receiving configuration code stream data of the communication module according to an instruction sent by the upper computer, writing the configuration code stream data into a specified area of a code stream memory, and jumping back to a standby state after the operation is finished.

Preferably, the read module realizes a standby state, a read preparation state and a read data state in a state machine mode;

when the control module enters a standby state, the reading module is in the standby state at the same time; when the control module enters a reading state, the reading module enters a reading preparation state to perform reading preparation operation on the code stream memory; and entering a data reading state after the operation is finished, reading code stream data of the designated area according to the address provided by the address conversion module, and jumping back to a standby state after the operation is finished.

Preferably, in the configuration stage, after the configuration of the main control FPGA module is completed, the main control FPGA module includes a control module, an FIFO module, a read module, an address conversion module, and a code stream output module;

the control module realizes the skipping of standby state, handshake, address judgment, address conversion, read state and code stream output state in a state machine mode, and controls the corresponding module through the skipping of the state;

the FIFO module is used for buffering data when reading operation is carried out on the code stream memory;

the address conversion module is used for judging an address according to the received address sent by the external tester, determining a code stream serial number which needs to be read currently, and determining the initial position and the end position of the reading operation of the current reading module according to the code stream serial number;

the reading module reads the corresponding code stream from the code stream memory according to the starting position and the ending position;

and the code stream output module outputs the read code stream to the communication module.

Compared with the prior art, the invention has the beneficial effects that:

(1) the system can be used for the mass production test of the ultra-large-scale FPGA, not only solves the problems that the automatic test equipment has insufficient memory and can not store a large number of FPGA test code streams, but also meets the requirement of completing high-speed configuration on the FPGA in the mass production test of the ultra-large-scale FPGA.

(2) Compared with the memory of the traditional automatic test equipment, the high-capacity FLASH memory can store a large number of test code streams, and the test of mass production of the ultra-large-scale FPGA is met;

(3) compared with the traditional JTAG configuration mode, the highest configuration rate is only 6 Mbits, the method adopts the SelectMap configuration mode, the configuration clock is 30 MHz, the data width is configured by 8 bits, the configuration rate reaches 240 Mbits, and the configuration efficiency of the FPGA is improved;

(4) the invention has the advantages that two stages of burning FLASH and configuring FPGA are completely independent, and the FPGA model selection function is matched, so that the flexibility and the universality are strong, and the test efficiency of FPGA mass production can be greatly improved.

(5) The invention is designed with the FPGA model selection module, so that the invention can complete the configuration function of various types of FPGAs, and the universality of the auxiliary configuration system are improved.

(6) The read-write module state machine designed by the invention is additionally provided with read and write preparation operation, so that the read-write operation time sequence of the memory is clearer, and the stability of the whole auxiliary configuration system is improved.

(7) In the state machine of the erasing module, enough delay time is preset in an unlocking instruction state, an erasing instruction state and an erasing time waiting state, so that the memory has enough time to confirm the instruction and respond the instruction, and the stability of the auxiliary configuration system is improved.

Drawings

FIG. 1 is a detailed block diagram of an auxiliary configuration system during a programming phase according to the present invention;

FIG. 2 is a detailed block diagram of a main control FPGA module of the auxiliary configuration system in the programming stage according to the present invention;

FIG. 3 is a control module state transition diagram of the auxiliary configuration system in the main control FPGA module during the programming phase according to the present invention;

FIG. 4 is a state transition diagram of the FIFO module in the FPGA module of the auxiliary configuration system according to the present invention;

FIG. 5 is a state transition diagram of a FLASH erase module in a main control FPGA module of the auxiliary configuration system during a programming phase according to the present invention;

FIG. 6 is a state transition diagram of a FLASH read module in a main control FPGA module of the auxiliary configuration system according to the present invention;

FIG. 7 is a state transition diagram of a FLASH write module in a main control FPGA module of the auxiliary configuration system in the programming stage according to the present invention;

FIG. 8 is a state transition diagram of an address translation module in a main control FPGA module of the auxiliary configuration system during a programming phase according to the present invention;

FIG. 9 is a state transition diagram of a communication control module in a main control FPGA module of the auxiliary configuration system in a programming phase according to the present invention;

FIG. 10 is a detailed block diagram of the assisted configuration system of the present invention during the configuration phase;

fig. 11 is a detailed module diagram of the main control FPGA module of the auxiliary configuration system in the configuration stage according to the present invention;

fig. 12 is a control module state transition diagram of the auxiliary configuration system in the configuration stage of the main control FPGA module;

fig. 13 is a state transition diagram of an address translation module in the main control FPGA module of the auxiliary configuration system in the configuration stage according to the present invention;

fig. 14 is a state transition diagram of a configuration output module in a main control FPGA module of the auxiliary configuration system in the configuration stage.

Detailed Description

The invention is further illustrated by the following examples.

A novel large-storage-capacity high-speed FPGA auxiliary configuration system comprises an upper computer programming module 205 running on an upper computer, a code stream memory 201, a main control FPGA module 202, a configuration memory module 208 and a communication module 204; the code stream memory 201, the main control FPGA module 202, the configuration memory module 208, and the communication module may be manufactured on a circuit board, or may adopt other different forms according to actual needs. The configuration memory module is used for storing an operation configuration file of the main control FPGA module in the configuration stage; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is powered on every time, and the main control FPGA module completes configuration according to the operation configuration file;

in a programming stage, a programming stage configuration file is sent to the main control FPGA module 202 from an upper computer, the main control FPGA module 202 completes programming control configuration according to the programming stage configuration file, the upper computer programming module 205 sends a configuration code stream to the main control FPGA module through a communication module, the main control FPGA module 202 programs the configuration code stream to the code stream memory 201, and the system is powered off; fig. 1 is a detailed block diagram of the auxiliary configuration system in the programming stage, wherein the communication module 204 is composed of an upper computer communication module 206 and a test interface module 207. In the programming stage, an additional FPGA model selection module 203 is configured to send different coded data to the main control FPGA module, and the main control FPGA module determines the specific model of the FPGA to be tested according to the coded data; programming configuration code streams of different FPGA models in a code stream memory; and the main control FPGA module acquires a corresponding configuration code stream from the code stream memory according to the specific model for configuration.

In the programming stage, the code stream memory 201, the FPGA model selection module 203 and the upper computer communication module 206 are respectively connected with the main control FPGA module 202 and perform data interaction. The upper computer programming module 205 is connected with the main control FPGA module 202 through an upper computer communication module 206.

The code stream storage module 201 is mainly composed of a FLASH array, a control signal and a data signal of each FLASH are connected with the main control FPGA module 202, and the signals include: DATA signal terminals DATA [31:0], address signal terminals ADDR [26:0], a clock signal CLK, a chip select signal terminal CE, an output enable signal terminal OE, a write enable signal terminal WE. The FPGA model selecting module 203 is connected to the FPGA through 4-bit signals, which are respectively: m3, M2, M1, M0; the upper computer communication module 206 is connected with the main control FPGA module 202 through DATA signals DATA [7:0], a chip selection signal end CE, an output enable signal end OE, a write enable signal end WR and a read enable signal end RD, and is connected with the upper computer programming module 205 through TX and RX signals.

The invention is designed in a sub-module mode, and takes a code stream storage module 201 as a core storage module. The FLASH array is used for storing the configuration code stream of the FPGA to be tested.

In the programming phase, as shown in fig. 2, the main control FPGA module 202 includes a control module 301, a FIFO module 302, an erasing module 303, a reading module 304, a writing module 305, an address converting module 306, and a communication control module 307.

After the system is powered on and enters a working state, as shown in fig. 3, the control module 301 enters a state 401; after entering the state 401, entering a state 402 under the action of a control signal provided by the upper computer programming module 205; in the programming mode, the working steps are as follows in sequence: state 401, state 402, state 403, state 404, state 405, state 406.

Wherein, the state 401 is a standby state after entering into work, and waits for an instruction of the upper computer programming module 205; the state 402 is a mode judgment state, and is selected to enter one of the states 401, 403, 404, 405 and 406 according to a command from the upper computer programming module 205; the state 403 is a handshake state, when receiving an instruction from the upper computer programming module 205 to request to enter the state 403, the main control FPGA module 202 sends the current encoded data to specify the FPGA model according to the encoded data of the FPGA model selection module 203, realizes handshake with the upper computer programming module 205, and then enters a state 401; the state 404 is a FLASH erasing state, when receiving an instruction from the upper computer programming module 205 to request to enter the state 404, the main control FPGA module 202 performs an erasing operation on a specified FLASH area according to instruction data of the upper computer programming module 205, after the erasing is completed, feeds back the completion state to the upper computer programming module 205, and then enters a state 401; the state 405 is a FLASH read state, when receiving an instruction from the upper computer programming module 205 and requesting to enter the state 405, the main control FPGA module 202 performs read operation on a specified FLASH region according to instruction data of the upper computer programming module 205, uploads the read data to the upper computer programming module 205, and after completing data reading work of the specified region, feeds back the completion state to the upper computer programming module 205, and then enters the state 401; the state 406 is a FLASH writing state, when receiving an instruction from the upper computer programming module 205 to request to enter the state 406, the main control FPGA module 202 performs a writing operation on a designated FLASH area according to instruction data of the upper computer programming module 205, writes data into the designated area of the FLASH by receiving code stream data from the upper computer programming module 205, and after completing the writing operation, feeds back a completion state to the upper computer programming module 205, and then enters the state 401.

The FIFO module 302 is a data buffering module when the control module 301 performs read/write operations on the bitstream memory, and plays roles of buffering data and asynchronous reading. As shown in fig. 4, the operation steps include a standby state 407, a reset FIFO state 408, a write operation state 409, and a read operation state 410, and the specific operation steps sequentially include: state 407, state 408, state 409, state 410.

The state 407 is a standby state, and when the control module 301 enters the standby state, the FIFO module 302 simultaneously enters the standby state; the state 408 is a reset FIFO state, and when the FIFO module leaves the standby state 407, the FIFO module enters the reset FIFO state, and resets the FIFO for read-write operation; the state 409 is a write operation state, and when the control module 301 executes the state 405, data read from the code stream memory is written into the FIFO module first; when the control module 301 executes the state 406, the data received from the upper computer programming module 205 is written into the FIFO module first; the state 410 is a read operation state, and when the control module 301 executes the state 405, data is read from the FIFO module and uploaded to the upper computer programming module 205; when the control module 301 executes state 406, data is read from the FIFO module and written to FLASH.

The erase module 303 is a module called by the control module 301 when performing a block erase operation on the code stream memory, and as shown in fig. 5, is divided into a standby state 411, an unlock command state 412, an unlock command confirmation state 413, an erase command state 414, an erase command confirmation state 415, and an erase time waiting state 416, and the working steps are a state 411, a state 412, a state 413, a state 414, a state 415, and a state 416.

The state 411 is a standby state, and when the control module 301 enters the standby state, the erase module enters the standby state at the same time; the state 412 is an unlocking instruction state, when the control module 301 enters the state 404, the erasing module enters the state 412 from the state 411, and the specified FLASH is subjected to unlocking instruction operation; the state 413 is an unlocking instruction confirmation state, and after the state 412 is completed, the state 413 is entered, the unlocking instruction confirmation operation is performed on the designated FLASH, and the preparation work for erasing the FLASH is completed; the state 414 is an erasing instruction state, and after the state 413 is completed, the state 414 is entered, and the block erasing instruction operation is performed on the FLASH in the designated area; the state 415 is an erase instruction confirmation state, after the state 414 is completed, the state 415 is entered, block erase instruction confirmation operation is performed on the FLASH in the designated area, and after the completion, the FLASH starts to erase the designated area; the state 416 is an erase time waiting state, and after the state 415 is completed, the state 416 is entered, since the FLASH block erase needs a certain time, the state 416 sets an erase waiting time of one block, and after the timing is completed, the state 411 is skipped.

The read module 304 is a module that is called when the control module 301 enters the state 405 and performs a read operation on the FLASH, and as shown in fig. 6, the read module is divided into a standby state 417, a read preparation state 418, and a read data state 419, and the working steps are as follows: state 417, state 418, state 419.

Wherein, the state 417 is a standby state, and when the control module 301 enters the standby state, the read module is in the standby state at the same time; the state 418 is a read preparation state, and when the control module 301 enters the state 405, the read module enters the read preparation state to perform read preparation operation on the FLASH related enable pin; the state 419 is a read operation state, and after the state 418 is completed, the state 419 is entered, the FLASH data in the designated area is read according to the address provided by the address conversion module, and after the operation is completed, the state 417 is jumped back.

The write module 305 is a module that is called when the control module 301 enters the state 406 and performs write operation on the FLASH, and as shown in fig. 7, is divided into a standby state 420, a write preparation state 421, and a write operation state 422, and the working steps are as follows: state 420, state 421, state 422.

Wherein, the state 420 is a standby state, and when the control module 301 enters the standby state, the write module is in the standby state at the same time; the state 421 is a write ready state, and when the control module 301 enters the state 406, the write module enters the write ready state to perform write ready operation on the FLASH related enable pin; the state 422 is a write operation state, and after the state 421 is completed, the state 422 is entered, the code stream data of the upper computer programming module 205 is received according to the instruction of the upper computer programming module 205, the code stream data is written into the designated area of the FLASH, and after the operation is completed, the state 420 is skipped.

The address conversion module 306 is configured to divide an address area in a code stream memory according to a code stream of a designated FPGA type and a serial number thereof in instruction data sent by the upper computer programming module 205 in a state 404, a state 405, and a state 406 of the control module 301, so as to facilitate writing and reading of code stream data. As shown in fig. 8, the standby state 423, the address transition waiting state 424, the FLASH mode determination state 425, and the code stream number determination state 426 are divided. The working steps are as follows: state 423, state 424, state 425, state 426;

wherein, the state 423 is a standby state of the address conversion module, and when the control module 301 enters the standby state, the address conversion module enters the standby state at the same time; state 424 is an address transition waiting state, and when the control module 301 enters state 403 and handshake succeeds, the address transition module waits for receiving a start enable signal and is ready to jump to the next state; the state 425 is a FLASH mode determination state, and after the state 424 is completed, the address conversion module receives an instruction of the control module, and determines to enter the following three modes according to the current instruction: one of a FLASH erasing mode, a FLASH reading mode and a FLASH writing mode; the state 426 is a code stream sequence number judgment state, and after the state 425 is completed, a designated FLASH area is allocated according to the code stream sequence number in the instruction of the control module, and is provided for the FLASH erasing module, the FLASH reading module and the FLASH writing module, corresponding operation is performed on the designated area, and after the operation is completed, the state 423 is skipped.

The communication control module 307 is a module for realizing data interaction with the upper computer communication module 206 by the main control FPGA module 202, and performs read or write operation on the upper computer communication module 206 according to the state of the corresponding pin of the upper computer communication module 206; as shown in fig. 9, the status is divided into a standby status 427, a mode determination status 428, a read mode status 429, and a write mode status 430; the work step is state 427, state 428, state 429 or state 430.

Wherein the state 427 is a standby state, and when the control module 301 enters the standby state, the communication control module 307 simultaneously enters the standby state; the state 428 is a mode determination state, and when the control module 301 jumps out of the standby state, the communication control module 307 simultaneously jumps out of the standby state, and determines to perform the following two modes according to the level state of the corresponding pin of the upper computer communication module 206: one of a read mode and a write mode; the state 429 is a read mode state, and after the state 428 is completed, it is determined that the read mode condition is met, the communication control module 307 enters the read mode state, reads valid data output by the upper computer communication module 206, transmits the valid data to the control module 301, and allows the control module 301 to analyze an instruction, and after the operation is completed, jumps back to the state 427; the state 430 is a write mode state, and after the state 428 is completed, it is determined that the write mode condition is met, the communication control module 307 enters the write mode state, receives data from the control module 301, transmits the data to a corresponding pin of the upper computer communication module 206, and after the operation is completed, jumps back to the state 427.

The FPGA model selection module 203 provides the specific model of the FPGA to be tested for the main control FPGA module through different coded data, and the same auxiliary configuration system can be used for volume production tests of FPGAs of different models by adjusting the coded value of the FPGA model selection module 203, so that the universality of the auxiliary configuration system is improved.

The communication module 204 is composed of an upper computer communication module 206 and a test interface module 207. In the programming stage, the upper computer communication module 206 mainly completes communication between the upper computer programming module 205 and the main control FPGA module 202. The upper computer communication module 206 is connected with the upper computer programming module 205 through a USB interface, and realizes communication with the main control FPGA module 202 through data signals and control signals.

The upper computer programming module 205 mainly completes configuration and read-back verification. The upper computer programming module 205 realizes interaction of data and control signals with the main control FPGA module 202 through the upper computer communication module 206. When configuring the code stream, the upper computer sends a clock, configuration code stream data and a control instruction, and the upper computer communication module 206 is connected with the main control FPGA module 202 to complete the operation of programming the configuration code stream to the code stream memory. During code stream verification, the upper computer programming module 205 sends a read-back verification instruction to the main control FPGA module 202 through the upper computer communication module 206, and the main control FPGA module 202 reads configuration code stream data stored in the code stream memory, sends the configuration code stream data to the upper computer through the main control FPGA module 202 and the upper computer communication module 206, and verifies the configuration code stream data with a code stream pre-stored in the upper computer.

Fig. 10 is a detailed module diagram of the auxiliary configuration system in the configuration stage, and in the configuration stage, the auxiliary configuration system mainly includes a code stream memory 201, a main control FPGA module 202, an FPGA model selection module 203, a communication module 204, and a configuration memory module 208; the communication module 204 is composed of an upper computer communication module 206 and a test interface module 207.

The code stream memory 201, the configuration memory module 208, the communication module 204 and the FPGA model selection module 203 are respectively connected with the main control FPGA module 202 and perform data interaction. When the FPGA to be tested is configured, the automatic tester sends an address signal and a control signal, and the main control FPGA module 202 reads a configuration code stream from the code stream memory module 201 after receiving the address signal and the control signal and writes the configuration code stream into the FPGA to be tested. In the configuration stage, the FPGA model selecting module 203 provides the specific model of the FPGA to be tested for the main control FPGA module 202 through different encoded data.

In the configuration stage, the main control FPGA module 202 includes a control module 501, a FIFO module 502, a read module 503, an address translation module 504, and a configuration output module 505;

as shown in fig. 11, after the system is powered on and enters the working state, the control module 501 enters a standby state 601; after entering state 601, entering handshake state 602 under the action of control signals provided by the automatic tester; in the configuration mode, as shown in fig. 12, the working steps are in sequence: state 601, state 602, state 603, state 604, state 605, state 606.

Wherein, the state 601 is a standby state after the system is powered on and enters a working state; the state 602 is a handshake state, and the control module 501 implements the handshake state according to the corresponding pin level state of the test interface module 207; the state 603 is an address determination state, and after the state 602 is completed, the control module 501 calculates the serial number of the code stream that needs to be read currently according to the corresponding pin level state of the test interface module 207; the state 604 is an address conversion state, and after the state 603 is completed, the control module 501 obtains corresponding address information through the address conversion module according to the code stream serial number; the state 605 is a FLASH read mode state, and the control mode 501 reads FLASH data in a corresponding area according to the address information; the state 606 is a configuration output state, and in the present invention, a configuration mode of SelectMAP is adopted, and code stream data is transmitted to the test interface module 207 through the configuration output module 506 by using read data until the FPGA to be tested completes the operation, and then the state is switched back to the state 601.

The FIFO block 502 is a data buffer block for the control block 501 to perform read operations on the code stream memory, and plays roles of buffering data and asynchronous reading. As shown in fig. 4, the operation steps include a standby state 607, a reset FIFO state 608, a write operation state 609, and a read operation state 610, which sequentially include: state 607, state 608, state 609, state 610.

Wherein, the state 607 is a standby state, and when the control module 501 enters the standby state, the FIFO module 502 simultaneously enters the standby state; the state 608 is a reset FIFO state, and when the FIFO module leaves the standby state 607, the FIFO module enters the reset FIFO state, and resets the FIFO for read-write operation; the state 609 is a write operation state, when the control module 501 executes the state 605, the data read from the code stream memory is written into the FIFO module first, and after the operation is completed, the state 607 is skipped back; the state 610 is a read operation state, and when the control module 501 executes the state 606, the data read from the FIFO module is transferred to the configuration output module 506, and after the operation is completed, the state 607 is skipped.

The read module 503 is a module called when the control module 501 enters the state 605 and performs a read operation on the FLASH, and as shown in fig. 6, is divided into a standby state 611, a read preparation state 612, and a read data body 613, and the working steps are as follows: state 611, state 612, state 613.

The state 611 is a standby state, and when the control module 501 enters the standby state, the read module is in the standby state at the same time; the state 612 is a read preparation state, and when the control module 501 enters the state 605, the read module enters the read preparation state to perform read preparation operation on the FLASH related enable pin; the state 613 is a read operation state, and after the state 612 is completed, the state 613 is entered, the FLASH data in the designated area is read according to the address provided by the address translation module, and after the operation is completed, the state 611 is skipped.

The address conversion module 504 is a module for calculating a corresponding address according to the currently selected FPGA model and the code stream serial number sent by the automatic tester by the control module 501 in the state 604. As shown in fig. 13, the state is divided into a standby state 614, an address transition waiting state 615, and a code stream sequence number determination state 616. The working steps are as follows: state 614, state 615, state 616.

The state 614 is a standby state of the address conversion module, and when the control module 501 enters the standby state, the address conversion module 504 enters the standby state at the same time; the state 615 is an address transition waiting state, and when the control module 501 enters the state 603 and the handshake is successful, the address transition module waits for receiving a start enable signal and is ready to jump to the next state; the state 616 is a state judged by the code stream serial number, and after the state 615 is completed, the corresponding FLASH region is calculated according to the code stream serial number, and is provided for a FLASH reading module to read the designated region, and after the operation is completed, the state is jumped back to the state 614.

The configuration output module 505 is a module that is called by the control module 501 to output a data stream in the form of SelectMAP to the test interface module 207 in the state 606, and completes the work of configuring the FPGA to be tested, and is divided into a standby state 617, a handshake state 618, and a data output state 619 as shown in fig. 14. The working steps are divided into state 617, state 618 and state 619.

The state 617 is a standby state, and when the control module 501 enters the standby state, the configuration output module 505 simultaneously enters the standby state; state 618 is a handshake state, and when the control mode 501 enters state 606, the configuration output module 505 sends a Program request signal and determines whether the handshake is successful according to a change in the received Initial signal; the state 619 is a data output state, and after the state 618 is completed, the configuration output module 505 sends the data of the corresponding area in the FLASH to the test interface module 207 according to the SelectMAP data format until the FPGA to be tested is in the state 617 after the operation is completed.

The invention has not been described in detail in part in the common general knowledge of a person skilled in the art.

Claims

1. A novel large-memory-capacity high-speed FPGA auxiliary configuration system is characterized in that: the system comprises an upper computer programming module running on an upper computer, a code stream memory, a main control FPGA module, a configuration memory module and a communication module;

2. The system of claim 1, wherein: the FPGA model selecting module is used for sending different coded data to the main control FPGA module, and the main control FPGA module determines the specific model of the FPGA to be detected according to the coded data; programming configuration code streams of different FPGA models in a code stream memory; and the main control FPGA module acquires a corresponding configuration code stream from the code stream memory according to the specific model for configuration.

3. The system of claim 1, wherein: in the programming stage, after the configuration code stream is programmed into the code stream memory, the upper computer programming module sends a read-back check instruction to the main control FPGA module through the communication module, the main control FPGA module reads out the configuration code stream data stored in the code stream memory and sends the configuration code stream data to the upper computer through the communication module, the upper computer checks the pre-stored code stream, and if the check is qualified, the programming stage is completed, and the system is powered off; otherwise, under the configuration of the current main control FPGA module, the programming operation is carried out again until the verification is qualified.

4. The system of claim 1, wherein: the code stream memory is a FLASH memory, a FLASH array is formed by a plurality of FLASH chips, the data signal and the control signal of each FLASH chip are connected with the data signal and the control signal of the main control FPGA module, and the main control FPGA module finishes the reading, writing and erasing operations of each FLASH chip.

5. The system of claim 1, wherein: in the programming stage, after the configuration of the main control FPGA module is completed, the main control FPGA module comprises a control module, an FIFO module, an erasing module, a writing module, an address conversion module and a communication control module;

6. The system of claim 3, wherein: in the programming stage, after the configuration of the main control FPGA module is completed, the main control FPGA module includes a control module 301, a FIFO module 302, an erasing module 303, a reading module, a writing module 305, an address conversion module 306, and a communication control module 307;

the FIFO module 302 is used for performing data buffering when performing read-write operation on the code stream memory;

7. The system according to claim 5 or 6, characterized in that: the erasing module realizes the skipping of a standby state, an unlocking instruction confirmation state, an erasing instruction confirmation state and an erasing time waiting state in a state machine mode;

8. The system according to claim 5 or 6, characterized in that: the writing module realizes the skipping of a standby state, a writing preparation state and a writing operation state in a state machine mode;

9. The system of claim 6, wherein: the reading module realizes a standby state, a reading preparation state and a reading data state in a state machine mode;

10. The system of claim 1, wherein: in the configuration stage, after the main control FPGA module is configured, the main control FPGA module comprises a control module, an FIFO module, a reading module, an address conversion module and a code stream output module;