CN111176911B - Novel high-speed FPGA auxiliary configuration system of large storage capacity - Google Patents
Novel high-speed FPGA auxiliary configuration system of large storage capacity Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention relates to a novel high-speed FPGA auxiliary configuration system with large storage capacity, wherein an operation configuration file of a main control FPGA module in a configuration stage is stored in a configuration memory module; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is electrified every time, and the main control FPGA module completes configuration; in the programming stage, a programming stage configuration file is sent to a main control FPGA module from an upper computer, the main control FPGA module completes programming control configuration, the upper computer programming module sends a configuration code stream to the main control FPGA module through a communication module, the main control FPGA module writes the configuration code stream to a code stream memory, and the system is powered off; in the configuration stage, the system is powered on, after the configuration file is run by the main control FPGA module to complete configuration, a configuration instruction sent from the outside is received, a corresponding configuration code stream is obtained from the code stream memory, and the obtained configuration code stream is sent to the FPGA to be tested by the communication module to complete configuration of the FPGA to be tested.
Description
Technical Field
The invention relates to a novel high-speed FPGA auxiliary configuration system with large storage capacity, and belongs to the technical field of integrated circuits.
Background
A very large field programmable gate array (FPGA, field Programmable Gate Array) with programmable capability contains a large number of programmable resources and these cannot be used simultaneously in one test code stream. With the progress of the process and the large increase of the circuit scale, the test code stream file is further increased. Aiming at the fact that the single code stream capacity of the ultra-large-scale FPGA reaches tens of megabits, in addition, the number of required code stream files is greatly increased to about 100-200 due to the improvement of the complexity of the test structure of the device to be tested, and therefore, in the test process, hundreds of configurations are usually needed to reach a certain fault coverage rate. At present, the memory of the devices with higher configuration, such as UltraFLEX, V93000 and the like, is only 128Mbyte at most, and hundreds of bit files far exceed the capacity of the memory of the tester, and the capability difference is more than 20 times, so that the code stream configuration cannot be directly carried out through the tester. Meanwhile, for mass production test, hundreds of test vectors need to be tested in a short time, and the configuration rate of the downloader provided by a device manufacturer is only about 12 megabits at the highest, and one hour may be required for testing one circuit, so that the test cost is not practical engineering value. Thus, completing a large number of test configurations in a short period of time is a challenge for a millions of gate-level FPGA mass production test systems. The problem is solved, the number of the test vectors is required to be compressed, and more importantly, a special configuration auxiliary system is developed by utilizing a high-speed configuration interface of the device, so that the speed of single configuration is increased, and the whole test system has the feasibility of implementing mass production test.
Disclosure of Invention
The invention solves the technical problems that: the system is used for ultra-large-scale FPGA production test, solves the problems that automatic test equipment is insufficient in memory and cannot store a large amount of FPGA test code streams, and meets the requirement of completing high-speed configuration on the FPGA in ultra-large-scale FPGA production test.
The solution of the invention is as follows: a novel high-speed FPGA auxiliary configuration system with large storage capacity comprises an upper computer programming module running on an upper computer, a code stream memory, a main control FPGA module, a configuration memory module and a communication module;
the configuration memory module stores an operation configuration file of the configuration stage master control FPGA module; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is electrified every time, and the main control FPGA module completes configuration according to the operation configuration file;
in the programming stage, a programming stage configuration file is sent to a main control FPGA module from an upper computer, the main control FPGA module completes programming control configuration according to the programming stage configuration file, the upper computer programming module sends a configuration code stream to the main control FPGA module through a communication module, the main control FPGA module writes the configuration code stream to a code stream memory, and the system is powered off;
in the configuration stage, the system is powered on, after the configuration file is run by the main control FPGA module to complete configuration, a configuration instruction sent from the outside is received, a corresponding configuration code stream is obtained from the code stream memory, and the obtained configuration code stream is sent to the FPGA to be tested by the communication module to complete configuration of the FPGA to be tested.
Preferably, the system further comprises an FPGA model selection module, different coding data are sent to the main control FPGA module through the FPGA model selection module, and the main control FPGA module determines the specific model of the FPGA to be tested according to the coding data; the configuration code streams of different FPGA models are programmed in the code stream memory; and the main control FPGA module acquires a corresponding configuration code stream from the code stream memory according to the specific model for configuration.
Preferably, in the programming stage, after the configuration code stream is programmed into the code stream memory, the upper computer programming module sends a read-back verification instruction to the main control FPGA module through the communication module, the main control FPGA module reads out the stored configuration code stream data in the code stream memory, the configuration code stream data is sent to the upper computer through the communication module, the upper computer and the pre-stored code stream are verified, and if the configuration code stream is qualified, the programming stage is completed, and the system is powered off; otherwise, under the configuration of the current main control FPGA module, the programming operation is carried out again until the verification is qualified.
Preferably, the code stream memory is a FLASH memory, a FLASH array is formed by a plurality of FLASH, the data signal and the control signal of each FLASH are connected with the data signal and the control signal of the main control FPGA module, and the main control FPGA module finishes the reading, writing and erasing operations of each FLASH.
Preferably, after the configuration of the main control FPGA module is completed in the programming stage, the main control FPGA module comprises a control module, a FIFO module, an erasing module, a writing module, an address conversion module and a communication control module;
the control module realizes the jump of standby state, mode judgment, handshake, erasure and writing state in a state machine mode;
the FIFO module is used for carrying out data buffering when writing operation is carried out on the code stream memory;
the address conversion module is used for determining the starting position and the ending position of the current programming according to the preset configuration code stream storage address;
the erasing module and the writing module respectively erase and write the code stream memory under the control of the state machine; in the writing operation process, the data is burnt from the FIFO module according to the starting position and the ending position determined by the address conversion module.
Preferably, after the configuration of the main control FPGA module is completed in the programming stage, the main control FPGA module comprises a control module, a FIFO module, an erasing module, a reading module, a writing module, an address conversion module and a communication control module;
the control module realizes the jump of standby state, mode judgment, handshake, erasure, reading and writing states in a state machine mode;
the FIFO module is used for buffering data when the code stream memory is subjected to read-write operation;
the address conversion module is used for determining the starting position and the ending position of the current programming according to the preset configuration code stream storage address;
the erasing module, the reading module and the writing module respectively erase and write the code stream memory under the control of the state machine; in the writing operation process, the data is burnt from the FIFO module according to the starting position and the ending position determined by the address conversion module, and the reading operation process is used for code stream verification.
Preferably, the erasing module realizes the skip of standby state, unlocking instruction confirmation state, erasing instruction confirmation state and erasing time waiting state in a state machine mode;
when the control module enters a standby state, the erasing module simultaneously enters the standby state; when the control module enters the erasing state, the erasing module enters the unlocking instruction state from the standby state, enters the unlocking instruction confirmation state after a preset time period is delayed, performs unlocking instruction operation on the code stream memory, enters the erasing instruction state after the operation is completed, enters the erasing instruction confirmation state after the preset time period is delayed, performs erasing instruction operation on the code stream memory, enters the erasing time waiting state, and returns to the standby state after the time waiting is completed.
Preferably, the write module realizes the skip of standby state, write ready state and write operation state by means of a state machine;
when the control module enters a standby state, the writing module is in the standby state at the same time; when the control module enters a writing state, the writing module enters a writing preparation state, and writing preparation operation is carried out on the code stream memory; after the operation is finished, the operation enters a writing operation state, the configuration code stream data of the communication module is received according to the instruction sent by the upper computer, the configuration code stream data is written into the designated area of the code stream memory, and after the operation is finished, the operation is resumed to a standby state.
Preferably, the read module realizes a standby state, a read preparation state and a read data state in a state machine mode;
when the control module enters a standby state, the reading module is in the standby state at the same time; when the control module enters a reading state, the reading module enters a reading preparation state, and the code stream memory is subjected to reading preparation operation; after the operation is finished, the data reading state is entered, the code stream data of the designated area is read according to the address provided by the address conversion module, and after the operation is finished, the standby state is skipped.
Preferably, in the configuration stage, after the configuration of the main control FPGA module is completed, the main control FPGA module comprises a control module, a FIFO module, a reading module, an address conversion module and a code stream output module;
the control module realizes the skip of standby state, handshake, address judgment, address conversion, reading state and code stream output state in a state machine mode, and controls the corresponding module through state skip;
the FIFO module is used for buffering data when the code stream memory is subjected to reading operation;
the address conversion module is used for carrying out address judgment according to the received address sent by the external tester, determining the code stream serial number to be read currently, and determining the starting position and the ending position of the reading operation of the current reading module according to the code stream serial number;
the reading module reads the corresponding code stream from the code stream memory according to the starting position and the ending position;
the code stream output module outputs the read code stream to the communication module.
Compared with the prior art, the invention has the beneficial effects that:
(1) The system can be used for ultra-large-scale FPGA throughput test, solves the problem that the memory of automatic test equipment is insufficient and a large amount of FPGA test code streams cannot be stored, and meets the requirement of completing high-speed configuration of the FPGA in the ultra-large-scale FPGA throughput test.
(2) Compared with the memory of the traditional automatic test equipment, the high-capacity FLASH memory can store a large amount of test code streams, and meets the ultra-large-scale FPGA throughput production test;
(3) Compared with the traditional JTAG configuration mode, the highest configuration rate is only 6 megabits, the method adopts the SelectMap configuration mode, configures the clock to 30 megahertz, adopts 8 bits to configure the data width, and has the configuration rate reaching 240 megabits, thereby improving the configuration efficiency of the FPGA;
(4) The two stages of programming FLASH and configuring FPGA are completely independent, and the FPGA model selection function is provided, so that the FPGA mass production testing method has strong flexibility and universality, and can greatly improve the testing efficiency of FPGA mass production.
(5) The invention is designed with the FPGA model selection module, so that the invention can complete the configuration functions of various models of FPGAs, and the universality of the auxiliary configuration system are improved.
(6) The read-write module state machine designed by the invention is added with read-write preparation operation, so that the read-write operation time sequence of the memory is clearer, and the stability of the whole auxiliary configuration system is improved.
(7) The state machine of the erasing module has enough delay time preset in the unlocking instruction state, the erasing instruction state and the erasing time waiting state, so that the memory has enough time to confirm the instruction and respond the instruction, and the stability of the auxiliary configuration system is improved.
Drawings
FIG. 1 is a detailed view of the auxiliary configuration system of the present invention during the programming phase;
FIG. 2 is a detailed view of the modules of the auxiliary configuration system of the present invention in the programming stage of the main control FPGA module;
FIG. 3 is a state transition diagram of a control module in a main control FPGA module of the auxiliary configuration system in the programming stage;
FIG. 4 is a state transition diagram of a FIFO module in the main control FPGA module of the auxiliary configuration system;
FIG. 5 is a state transition diagram of a FLASH erase module in a main control FPGA module of the auxiliary configuration system in the programming stage;
FIG. 6 is a state transition diagram of a FLASH read module in a main control FPGA module of the auxiliary configuration system;
FIG. 7 is a state transition diagram of a FLASH write module in a main control FPGA module of the auxiliary configuration system in the programming stage;
FIG. 8 is a state transition diagram of an address conversion module in a main control FPGA module of the auxiliary configuration system in the programming stage;
FIG. 9 is a state transition diagram of a communication control module in a main control FPGA module of the auxiliary configuration system in the programming stage;
FIG. 10 is a detailed block diagram of the auxiliary configuration system of the present invention at a configuration stage;
FIG. 11 is a detailed view of the modules of the master FPGA module of the auxiliary configuration system of the present invention during the configuration phase;
FIG. 12 is a state transition diagram of a control module in a main control FPGA module of the auxiliary configuration system in the configuration stage;
FIG. 13 is a state transition diagram of an address conversion module in a main control FPGA module of the auxiliary configuration system in the configuration stage;
fig. 14 is a state transition diagram of a configuration output module in a main control FPGA module in a configuration stage of the auxiliary configuration system according to the present invention.
Detailed Description
The invention is further illustrated below with reference to examples.
A novel high-speed FPGA auxiliary configuration system with large storage capacity comprises an upper computer programming module 205 running on an upper computer, a code stream memory 201, a main control FPGA module 202, a configuration memory module 208 and a communication module 204; the code stream memory 201, the main control FPGA module 202 and the configuration memory module 208 can be manufactured on a circuit board, and of course, other different forms can be adopted according to actual needs. The configuration memory module is used for storing an operation configuration file of the main control FPGA module in the configuration stage; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is electrified every time, and the main control FPGA module completes configuration according to the operation configuration file;
in the programming stage, a programming stage configuration file is sent to the main control FPGA module 202 from the upper computer, the main control FPGA module 202 completes programming control configuration according to the programming stage configuration file, the upper computer programming module 205 sends a configuration code stream to the main control FPGA module through the communication module, the main control FPGA module 202 writes the configuration code stream to the code stream memory 201, and the system is powered off; fig. 1 is a detailed view of the auxiliary configuration system in the programming stage, wherein the communication module 204 is composed of a host communication module 206 and a test interface module 207. In the programming stage, different coding data can be sent to the main control FPGA module by additionally configuring an FPGA model selection module 203, and the main control FPGA module determines the specific model of the FPGA to be tested according to the coding data; the configuration code streams of different FPGA models are programmed in the code stream memory; and the main control FPGA module acquires a corresponding configuration code stream from the code stream memory according to the specific model for configuration.
In the programming stage, the code stream memory 201, the FPGA model selection module 203 and the upper computer communication module 206 are respectively connected with the main control FPGA module 202 and perform data interaction. The upper computer programming module 205 is connected with the main control FPGA module 202 through the upper computer communication module 206.
The code stream storage module 201 is mainly composed of FLASH arrays, and control signals and data signals of each FLASH are connected with the main control FPGA module 202, wherein the signals comprise: DATA signal terminals DATA [31:0], address signal terminals ADDR [26:0], clock signal CLK, chip select signal terminal CE, output enable signal terminal OE, and write enable signal terminal WE. The FPGA model selection module 203 is connected with the FPGA through 4-bit signals, and is respectively: m3, M2, M1, M0; the upper computer communication module 206 is connected with the main control FPGA module 202 through DATA signals DATA [7:0], chip select signal terminals CE, an output enable signal terminal OE, a write enable signal terminal WR and a read enable signal terminal RD, and is connected with the upper computer programming module 205 through TX and RX signals.
The invention adopts a sub-module design, and takes a code stream storage module 201 as a core storage module. The device consists of a FLASH array and is used for storing configuration code streams of the test FPGA.
In the programming stage, as shown in fig. 2, the main control FPGA module 202 includes a control module 301, a fifo module 302, an erasing module 303, a reading module 304, a writing module 305, an address conversion module 306, and a communication control module 307.
After the system is powered on and enters a working state, as shown in fig. 3, the control module 301 enters a state 401; after entering the state 401, entering the state 402 under the control signal provided by the upper computer programming module 205; in the programming mode, the working steps are as follows: state 401, state 402, state 403, state 404, state 405, state 406.
The state 401 is a standby state after entering into operation, and waits for an instruction of the upper computer programming module 205; the state 402 is a mode judgment state, and one of the states 401, 403, 404, 405, and 406 is selected to be entered according to a command from the upper computer programming module 205; the state 403 is a handshake state, when receiving an instruction from the upper computer programming module 205 to enter the state 403, the main control FPGA module 202 sends current coded data to specify an FPGA model according to the coded data of the FPGA model selecting module 203, and handshake is realized with the upper computer programming module 205, and then enters the state 401; the state 404 is a FLASH erasing state, when receiving an instruction from the upper computer programming module 205 to enter the state 404, the main control FPGA module 202 performs erasing operation on a designated FLASH area according to instruction data of the upper computer programming module 205, and after the erasing is completed, the completed state is fed back to the upper computer programming module 205, and then enters the state 401; the state 405 is a FLASH read state, when receiving an instruction from the upper computer programming module 205 to request to enter the state 405, the main control FPGA module 202 performs a read operation on a designated FLASH area according to instruction data of the upper computer programming module 205, uploads the read data to the upper computer programming module 205, feeds back the completion state to the upper computer programming module 205 after finishing the data read operation of the designated area, and then enters the state 401; the state 406 is a FLASH writing state, when receiving an instruction from the upper computer programming module 205 to request to enter the state 406, the main control FPGA module 202 performs writing operation on the designated FLASH area according to the instruction data of the upper computer programming module 205, and writes the data into the designated area of the FLASH by receiving the code stream data from the upper computer programming module 205, and after completing writing operation, feeds back the completion state to the upper computer programming module 205, and then enters the state 401.
The FIFO module 302 is a data buffer module when the control module 301 performs read-write operation on the code stream memory, and plays roles of buffering data and asynchronous reading. As shown in fig. 4, the method is divided into a standby state 407, a reset FIFO state 408, a write operation state 409, and a read operation state 410, and the specific working steps are as follows: state 407, state 408, state 409, state 410.
Wherein, the state 407 is a standby state, and when the control module 301 enters the standby state, the FIFO module 302 simultaneously enters the standby state; the state 408 is a reset FIFO state, and when the FIFO module leaves the standby state 407, the FIFO module enters a reset FIFO state, and resets the FIFO for read-write operation; the state 409 is a write operation state, and when the control module 301 executes the state 405, the data read from the code stream memory will be written into the FIFO module first; when the control module 301 executes the state 406, the data received from the upper computer programming module 205 is first written into the FIFO module; the state 410 is a read operation state, and when the control module 301 executes the state 405, the data is read from the FIFO module and uploaded to the upper computer programming module 205; when the control module 301 executes state 406, data is read from the FIFO module and written into FLASH.
The erasing module 303 is a calling module when the control module 301 performs a block erasing operation on the code stream memory, and as shown in fig. 5, the modules are divided into a standby state 411, an unlock instruction state 412, an unlock instruction confirmation state 413, an erase instruction state 414, an erase instruction confirmation state 415, and an erase time waiting state 416, and the working steps are state 411, state 412, state 413, state 414, state 415, and state 416.
Wherein, the state 411 is a standby state, and when the control module 301 enters the standby state, the erasing module simultaneously enters the standby state; the state 412 is an unlock instruction state, and when the control module 301 enters the state 404, the erase module enters the state 412 from the state 411, and performs an unlock instruction operation on the designated FLASH; the state 413 is an unlock instruction confirmation state, after the state 412 is completed, the state 413 is entered, the unlock instruction confirmation operation is performed on the designated FLASH, and the preparation work of erasing the FLASH is completed; state 414 is an erase command state, after state 413 is completed, state 414 is entered, and a block erase command operation is performed on the FLASH in the designated area; the state 415 is an erase command confirmation state, after the state 414 is completed, the state 415 is entered, the FLASH of the designated area is subjected to block erase command confirmation operation, and after the completion, the FLASH starts to erase the designated area; state 416 is an erase wait state, after state 415 is completed, state 416 is entered, and since FLASH block erase requires a certain time, state 416 sets an erase wait time for a block, and after the timer is completed, state 411 is skipped.
The read module 304 is a module called when the control module 301 enters the state 405 to perform a read operation on FLASH, and as shown in fig. 6, the read module is divided into a standby state 417, a read ready state 418, and a read data state 419, and the working steps are as follows: state 417, state 418, state 419.
Wherein, the state 417 is a standby state, and when the control module 301 enters the standby state, the read module is in the standby state at the same time; state 418 is a read ready state, and when the control module 301 enters state 405, the read module enters a read ready state, and performs a read ready operation on the FLASH related enable pin; state 419 is a read operation state, after completion of state 418, state 419 is entered, FLASH data in the designated area is read according to the address provided by the address translation module, and after completion of the operation, state 417 is skipped.
The write module 305 is a module called when the control module 301 enters the state 406 to perform write operation on FLASH, and as shown in fig. 7, the write module is divided into a standby state 420, a write ready state 421, and a write operation state 422, and the working steps are as follows: state 420, state 421, state 422.
Wherein, the state 420 is a standby state, and when the control module 301 enters the standby state, the writing module is in the standby state at the same time; the state 421 is a write ready state, and when the control module 301 enters the state 406, the write module enters the write ready state, and performs write ready operation on the FLASH related enable pin; state 422 is a write operation state, after the completion of state 421, state 422 is entered, the code stream data of the upper computer programming module 205 is received according to the instruction of the upper computer programming module 205, written into the designated area of FLASH, and after the completion of the operation, the state 420 is skipped.
The address conversion module 306 is that the control module 301 divides an address area in the code stream memory according to the code stream of the specified FPGA model and the serial number thereof in the instruction data sent by the upper computer programming module 205 in the state 404, the state 405 and the state 406, so as to facilitate writing and reading of the code stream data. As shown in fig. 8, the configuration is divided into a standby state 423, an address transition standby state 424, a FLASH mode determination state 425, and a stream number determination state 426. The working steps are as follows: state 423, state 424, state 425, state 426;
the state 423 is a standby state of the address conversion module, and when the control module 301 enters the standby state, the address conversion module simultaneously enters the standby state; state 424 is an address translation wait state, where after the control module 301 enters state 403 and the handshake is successful, the address translation module waits to receive a start enable signal, ready to jump to the next state; state 425 is a FLASH mode determination state, and after completion of state 424, the address translation module receives the command from the control module, and determines to enter the following three modes according to the current command: one of a FLASH erasing mode, a FLASH reading mode and a FLASH writing mode; the state 426 is a code stream sequence number judging state, after the state 425 is completed, the designated FLASH region is allocated according to the code stream sequence number in the instruction of the control module, and is provided for the FLASH erasing module, the FLASH reading module and the FLASH writing module, the designated region is correspondingly operated, and after the operation is completed, the state 423 is skipped.
The communication control module 307 is a module for implementing data interaction with the upper computer communication module 206 by the main control FPGA module 202, and performs a read or write operation on the upper computer communication module 206 according to the state of the corresponding pin of the upper computer communication module 206; as shown in fig. 9, the configuration is divided into a standby state 427, a mode determination state 428, a read mode state 429, and a write mode state 430; the working steps are state 427, state 428, state 429 or state 430.
Wherein, the state 427 is a standby state, and when the control module 301 enters the standby state, the communication control module 307 simultaneously enters the standby state; state 428 is a mode determination state, when the control module 301 goes out of the standby state, the communication control module 307 goes out of the standby state at the same time, and determines to perform the following two modes according to the level state of the corresponding pin of the upper computer communication module 206: one of a read mode and a write mode; the state 429 is a read mode state, after the state 428 is completed, the communication control module 307 judges that the read mode condition is met, the communication control module 307 enters the read mode state, reads the effective data output by the upper computer communication module 206, and transmits the effective data to the control module 301 for the control module 301 to analyze the instruction, and after the operation is completed, the state 427 is skipped; state 430 is a write mode state, after completion of state 428, the communication control module 307 determines that the write mode condition is met, enters the write mode state, receives data from the control module 301, and transmits the data to the corresponding pins of the host communication module 206, and after completion of the operation, jumps back to state 427.
The FPGA model selection module 203 provides the main control FPGA module with specific models of the FPGA to be tested through different coding data, and the same auxiliary configuration system can be used for carrying out mass production test of different types of FPGAs through adjusting the coding values of the FPGA model selection module 203, so that the universality of the auxiliary configuration system is improved.
The communication module 204 is composed of an upper computer communication module 206 and a test interface module 207. In the programming stage, the upper computer communication module 206 mainly completes the communication between the upper computer programming module 205 and the main control FPGA module 202. The upper computer communication module 206 is connected with the upper computer programming module 205 through a USB interface, and realizes communication with the master control FPGA module 202 through data signals and control signals.
The upper computer programming module 205 mainly completes configuration and read-back verification. The upper computer programming module 205 is used for realizing interaction of data and control signals with the main control FPGA module 202 through the upper computer communication module 206. When the code stream is configured, the upper computer sends a clock, configuration code stream data and a control instruction, and the upper computer communication module 206 is connected with the main control FPGA module 202 to complete the operation of programming the configuration code stream into the code stream memory. During code stream verification, the upper computer programming module 205 sends a read-back verification instruction to the main control FPGA module 202 through the upper computer communication module 206, the main control FPGA module 202 reads out configuration code stream data stored in a code stream memory, and the configuration code stream data is sent to the upper computer through the main control FPGA module 202 and the upper computer communication module 206 to be verified with a code stream stored in the upper computer in advance.
Fig. 10 is a detailed module diagram of the auxiliary configuration system in the configuration stage, in which the auxiliary configuration system mainly comprises a code stream memory 201, a main control FPGA module 202, an FPGA model selection module 203, a communication module 204, and a configuration memory module 208; the communication module 204 is composed of an upper computer communication module 206 and a test interface module 207.
The code stream memory 201, the configuration memory module 208, the communication module 204 and the FPGA model selection module 203 are respectively connected with the main control FPGA module 202 and perform data interaction. When the FPGA to be tested is configured, an automatic tester sends an address signal and a control signal, and the main control FPGA module 202 reads a configuration code stream from the code stream memory module 201 after receiving the address signal and the control signal, and writes the configuration code stream into the FPGA to be tested. In the configuration stage, the FPGA model selection module 203 provides the specific model of the FPGA to be tested for the main control FPGA module 202 through different encoded data.
In the configuration stage, the main control FPGA module 202 includes a control module 501, a fifo module 502, a read module 503, an address conversion module 504, and a configuration output module 505;
as shown in fig. 11, after the system is powered on and enters an operating state, the control module 501 enters a standby state 601; after entering state 601, entering handshake state 602 under the control signal provided by the automatic tester; in the configuration mode, as shown in fig. 12, the working steps are in sequence: state 601, state 602, state 603, state 604, state 605, state 606.
The state 601 is a standby state after the system is powered on and enters a working state; the state 602 is a handshake state, and the control module 501 implements the handshake state according to the corresponding pin level state of the test interface module 207; the state 603 is an address judging state, and after the state 602 is completed, the control module 501 calculates the serial number of the code stream to be read currently according to the corresponding pin level state of the test interface module 207; the state 604 is an address conversion state, and after the state 603 is completed, the control module 501 obtains corresponding address information through the address conversion module according to the code stream sequence number; the state 605 is a FLASH read mode state, and the control mode 501 reads FLASH data of a corresponding area according to the address information; the state 606 is a configuration output state, in the present invention, a SelectMAP configuration mode is adopted, and the code stream data is transmitted to the test interface module 207 through the configuration output module 506 by the read data until the FPGA to be tested, and after the operation is completed, the state 601 is skipped.
The FIFO module 502 is a data buffer module when the control module 501 performs a read operation on the code stream memory, and plays roles of buffering data and asynchronous reading. As shown in fig. 4, the method is divided into a standby state 607, a reset FIFO state 608, a write operation state 609, a read operation state 610, and the specific working steps are as follows: state 607, state 608, state 609, state 610.
Wherein, the state 607 is a standby state, and when the control module 501 enters the standby state, the FIFO module 502 simultaneously enters the standby state; the state 608 is a reset FIFO state, and when the FIFO module leaves the standby state 607, the FIFO module enters a reset FIFO state, and resets the FIFO for read-write operation; state 609 is a write operation state, when the control module 501 executes state 605, the data read from the code stream memory will be written into the FIFO module first, and after the operation is completed, the state 607 is skipped; state 610 is a read operation state, and when the control module 501 executes state 606, data is read from the FIFO module and transferred to the configuration output module 506, and after the operation is completed, the state 607 is skipped.
The read module 503 is a module called when the control module 501 performs a read operation on FLASH after entering the state 605, and as shown in fig. 6, is divided into a standby state 611, a read ready state 612, and a read data state 613, and comprises the following working steps: state 611, state 612, state 613.
Wherein state 611 is a standby state, when control module 501 enters the standby state, the read module is in the standby state at the same time; state 612 is a read ready state, and when the control module 501 enters state 605, the read module enters a read ready state, and performs a read ready operation on the FLASH related enable pin; state 613 is a read operation state, after completion of state 612, state 613 is entered, FLASH data in the designated area is read according to the address provided by the address translation module, and after completion of the operation, state 611 is skipped.
The address conversion module 504 is a module that, in the state 604, the control module 501 calculates a corresponding address according to the currently selected FPGA model and the code stream sequence number sent by the automatic tester. As shown in fig. 13, the system is divided into a standby state 614, an address transition standby state 615, and a stream number determination state 616. The working steps are as follows: state 614, state 615, state 616.
Wherein, the state 614 is a standby state of the address translation module, and when the control module 501 enters the standby state, the address translation module 504 simultaneously enters the standby state; state 615 is an address translation wait state, when the control module 501 enters state 603 and handshakes successfully, the address translation module waits to receive a start enable signal, and prepares to jump to the next state; state 616 is a code stream sequence number determination state, after completion of state 615, the corresponding FLASH region is calculated according to the code stream sequence number, provided to the FLASH read module, read the designated region, and after completion of the operation, jump back to state 614.
The configuration output module 505 is that the control module 501 calls the module to output a data stream in the form of SelectMAP to the test interface module 207 in the state 606 to complete the task of configuring the FPGA to be tested, and is divided into a standby state 617, a handshake state 618 and a data output state 619 as shown in FIG. 14. The working steps are divided into a state 617, a state 618 and a state 619.
Wherein, the state 617 is a standby state, and when the control module 501 enters the standby state, the output module 505 is configured to enter the standby state at the same time; state 618 is a handshake state, and when the control mode 501 enters state 606, the configuration output module 505 sends a Program request signal, and determines whether handshake is successful according to the change of the received Initial signal; state 619 is a data output state, after completing state 618, the configuration output module 505 sends the data of the corresponding area in the FLASH to the test interface module 207 according to the SelectMAP data format until the FPGA to be tested is completed, and after completing the operation, the state 617 is skipped.
The invention is not described in detail in part as being common general knowledge to a person skilled in the art.
Claims (8)
1. A novel high-speed FPGA auxiliary configuration system with large storage capacity is characterized in that: the system comprises an upper computer programming module running on an upper computer, a code stream memory, a main control FPGA module, a configuration memory module and a communication module;
the configuration memory module stores an operation configuration file of the configuration stage master control FPGA module; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is electrified every time, and the main control FPGA module completes configuration according to the operation configuration file;
in the programming stage, a programming stage configuration file is sent to a main control FPGA module from an upper computer, the main control FPGA module completes programming control configuration according to the programming stage configuration file, the upper computer programming module sends a configuration code stream to the main control FPGA module through a communication module, the main control FPGA module writes the configuration code stream to a code stream memory, and the system is powered off; after the configuration of the main control FPGA module is completed in the programming stage, the main control FPGA module comprises a control module, a FIFO module, an erasing module, a writing module, an address conversion module and a communication control module; the control module realizes the jump of standby state, mode judgment, handshake, erasure and writing state in a state machine mode; the FIFO module is used for carrying out data buffering when writing operation is carried out on the code stream memory; the address conversion module is used for determining the starting position and the ending position of the current programming according to the preset configuration code stream storage address; the erasing module and the writing module respectively erase and write the code stream memory under the control of the state machine; in the writing operation process, the data is burnt from the FIFO module according to the starting position and the ending position determined by the address conversion module;
in the configuration stage, the system is powered on, after the configuration file is run by the main control FPGA module to complete configuration, a configuration instruction sent from the outside is received, a corresponding configuration code stream is obtained from the code stream memory, and the obtained configuration code stream is sent to the FPGA to be tested by the communication module to complete configuration of the FPGA to be tested;
after the configuration of the main control FPGA module is completed in the configuration stage, the main control FPGA module comprises a control module, a FIFO module, a reading module, an address conversion module and a code stream output module;
the control module realizes the skip of standby state, handshake, address judgment, address conversion, reading state and code stream output state in a state machine mode, and controls the corresponding module through state skip;
the FIFO module is used for buffering data when the code stream memory is subjected to reading operation;
the address conversion module is used for carrying out address judgment according to the received address sent by the external tester, determining the code stream serial number to be read currently, and determining the starting position and the ending position of the reading operation of the current reading module according to the code stream serial number;
the reading module reads the corresponding code stream from the code stream memory according to the starting position and the ending position;
the code stream output module outputs the read code stream to the communication module.
2. The system according to claim 1, wherein: the system also comprises an FPGA model selection module, wherein different coding data are sent to the main control FPGA module through the FPGA model selection module, and the main control FPGA module determines the specific model of the FPGA to be tested according to the coding data; the configuration code streams of different FPGA models are programmed in the code stream memory; and the main control FPGA module acquires a corresponding configuration code stream from the code stream memory according to the specific model for configuration.
3. The system according to claim 1, wherein: in the programming stage, after the configuration code stream is programmed into the code stream memory, the upper computer programming module sends back a read-verify command to the main control FPGA module through the communication module, the main control FPGA module reads out the stored configuration code stream data in the code stream memory, the configuration code stream data is sent to the upper computer through the communication module, the upper computer and the pre-stored code stream are verified, and if the verification is qualified, the programming stage is completed, and the system is powered off; otherwise, under the configuration of the current main control FPGA module, the programming operation is carried out again until the verification is qualified.
4. The system according to claim 1, wherein: the code stream memory is a FLASH memory, a FLASH array is formed by a plurality of FLASH, the data signal and the control signal of each FLASH are connected with the data signal and the control signal of the main control FPGA module, and the main control FPGA module finishes the reading, writing and erasing operations of each FLASH.
5. A system according to claim 3, characterized in that:
after the configuration of the main control FPGA module is completed in the programming stage, the main control FPGA module comprises a control module, a FIFO module, an erasing module, a reading module, a writing module, an address conversion module and a communication control module;
the control module realizes the jump of standby state, mode judgment, handshake, erasure, reading and writing states in a state machine mode;
the FIFO module is used for buffering data when the code stream memory is subjected to read-write operation;
the address conversion module is used for determining the starting position and the ending position of the current programming according to the preset configuration code stream storage address;
the erasing module, the reading module and the writing module respectively erase and write the code stream memory under the control of the state machine; in the writing operation process, the data is burnt from the FIFO module according to the starting position and the ending position determined by the address conversion module, and the reading operation process is used for code stream verification.
6. The system according to claim 1 or 5, characterized in that: the erasing module realizes the jump of standby state, unlocking instruction confirmation state, erasing instruction confirmation state and erasing time waiting state in a state machine mode;
when the control module enters a standby state, the erasing module simultaneously enters the standby state; when the control module enters the erasing state, the erasing module enters the unlocking instruction state from the standby state, enters the unlocking instruction confirmation state after a preset time period is delayed, performs unlocking instruction operation on the code stream memory, enters the erasing instruction state after the operation is completed, enters the erasing instruction confirmation state after the preset time period is delayed, performs erasing instruction operation on the code stream memory, enters the erasing time waiting state, and returns to the standby state after the time waiting is completed.
7. The system according to claim 1 or 5, characterized in that: the write module realizes the skip of standby state, write ready state and write operation state by means of a state machine;
when the control module enters a standby state, the writing module is in the standby state at the same time; when the control module enters a writing state, the writing module enters a writing preparation state, and writing preparation operation is carried out on the code stream memory; after the operation is finished, the operation enters a writing operation state, the configuration code stream data of the communication module is received according to the instruction sent by the upper computer, the configuration code stream data is written into the designated area of the code stream memory, and after the operation is finished, the operation is resumed to a standby state.
8. The system according to claim 5, wherein: the reading module realizes a standby state, a reading preparation state and a reading data state in a state machine mode;
when the control module enters a standby state, the reading module is in the standby state at the same time; when the control module enters a reading state, the reading module enters a reading preparation state, and the code stream memory is subjected to reading preparation operation; after the operation is finished, the data reading state is entered, the code stream data of the designated area is read according to the address provided by the address conversion module, and after the operation is finished, the standby state is skipped.
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