CN106843955A - Based on compressing file and contactless FPGA Dynamic Configurations - Google Patents
Based on compressing file and contactless FPGA Dynamic Configurations Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The present invention proposes a kind of based on compressing file and contactless FPGA Dynamic Configurations, and for solving, hardware complexity present in existing dynamic configuration is high, low and very flexible the technical problem of configuration speed, realizes that step is：Building inside solidification has wireless receiving module, data decompression module, in-system programming module and configuration file to insmod the target FPGA of program；The configuration file of target FPGA is carried out Lossless Compression by external processing apparatus；Configuration file after compression is wirelessly sent to target FPGA；Configuration file is stored in internal RAM after the compression that wireless receiving module will be received；Configuration file is read from RAM after data decompression module will compress, and configuration FLASH is write after being decompressed；External processing apparatus send configuration file is loaded into order and thermal starting address；Configuration file insmods and configuration file is loaded into since the thermal starting address of configuration FLASH, completes dynamic configuration.
Description
Technical field
The invention belongs to digital processing field, it is related to a kind of FPGA Dynamic Configurations, more particularly to one kind to be based on
Compressing file and contactless FPGA Dynamic Configurations, can be used to communicating, image procossing, the field such as energy traffic.
Background technology
FPGA (Field Programmable Gate Array) is field programmable gate array, it be PAL, GAL,
The product further developed on the basis of the programming devices such as CPLD.It is as in application specific integrated circuit (ASIC) field
Plant semi-custom circuit and occur, both solved the deficiency of custom circuit, original programming device gate circuit number is overcome again to be had
The shortcoming of limit.
FPGA is a kind of programmable signal processor for using, and user can be carried out by changing configuration information to its function
Definition, to meet design requirement.Compared with conventional digital circuits system, FPGA can with programmable, high integration, high speed and height
The advantages of by property, by the logic function inside configuration device and input, output port, the design of original circuit board level is placed on
Carried out in chip, improve circuit performance, reduce the workload and difficulty of PCB design, effectively increase design
Flexibility and efficiency.Programmable Technology is the core of FPGA, realizes programmable functions to FPGA using different types of memory
The structure and performance of device have tremendous influence, and Programmable Technology is broadly divided into 3 kinds.The first is the programming skill based on SRAM
Art, because SRAM is volatile memory, internal data is lost after power down, must be reconfigured after upper electricity every time, so just
It is especially inconvenient when formula is used, so general only use in debugging；Second is antifuse programming technique, and program is not after power down
Can lose, but antifuse technology can only one-off programming, it is impossible to device yield is low after overprogram, and programming, adds
Cost is very high, so being normally only used for military project space industry；The third is FLASH programming techniques, with both the above programming technique
Compare, FLASH programs the characteristics of combining non-volatile and repeatable programming, and FPGA can be automatically configured after upper electricity, because it is suitable
For majority of case, so as mainstream configuration mode instantly.After static configuration refers to a configuration successful, if wanting to change
Whole circuit function, it is necessary to re-powered after power-off, downloads new configuration file, and function could change.Dynamic configuration refer to
In the case of need not powering off, flexibly change the configuration file of FPGA.Complication and functional diversities with communication system, very
Multisystem needs do not realizing different functions in the same time that static configuration can not meet requirement, and most occasions need FPGA
Online dynamic configuration can be supported, so as to dynamically change the function of whole circuit.
Carrying out dynamic configuration to FPGA mainly has following several method at present：
The first, FPGA modularization designs are simulated with dsp chip, and dynamic configuration is carried out to FPGA.Such as Chinese patent application,
Authorization Notice No. is CN102521065B, a kind of method of FPGA dynamic loads configuration file is disclosed, by FPGA's
The voltages such as Hardwarerst ports and PROG_B ports are connected, and the Hardwarerst ports are an idle I/ of FPGA
O port, the level state of the PROG_B ports determines whether FPGA reloads configuration file；DSP is described by control
The output signal of Hardwarerst ports controls the state of PROG_B ports, on platform during electricity, DSP control FPGA loadings
Configuration file, and control the FPGA to carry out self-inspection, and controlled if FPGA operation irregularities are found according to the self-detection result of FPGA
FPGA reloads configuration file.Although the method can realize the dynamic configuration of FPGA, but need to be made at auxiliary of DSP
Reason, hardware realizes complicated, high cost, and configuration file, without overcompression, configured rate is low.
Second, FPGA modularization designs are simulated with CPLD chips, dynamic configuration is carried out to FPGA.Chen Xi exists within such as 2013
The communication technology 2012 03 interim entitled " a kind of reliable FPGA Dynamic Configurations and realization ", proposes a kind of based on CPU+
The reliable FPGA dynamic loading methods of CPLD, wherein CPU is used to completing the control of configuration process, the encryption and decryption storage of program and
Read, while selecting corresponding FPGA programs according to applied environment.CPLD is used to complete the passive loading interface sequential to FPGA,
The watchdog function to FPGA and DSP is completed simultaneously.Although the method can also realize dynamic configuration, CPLD is needed also exist for
To simulate FPGA loading sequential, hardware realizes complicated, high cost, and needs with CPU to be connected FPGA boards by netting twine, spirit
Poor activity, not also being suitable for equipment where some FPGA needs the occasion of sealing.
It can be seen that existing Dynamic Reconfiguration has the defects such as hardware complexity high, configured rate is low, very flexible, and
Formal when using, many test equipments are all packaged, the cover plate of equipment can not easily be opened or removed, traditional side
Method is switched on equipment or is connected by there is hardware with equipment, thus in the presence of many inconvenience.Therefore, one kind is found to be based on
Compressing file and contactless FPGA Dynamic Configurations are particularly important.
The content of the invention
It is an object of the invention to the defect for overcoming above-mentioned prior art to exist, it is proposed that a kind of based on compressing file and non-
The FPGA Dynamic Configurations of contact, for solving, hardware complexity present in existing dynamic configuration is high, configuration speed is low
With the technical problem of very flexible.
To achieve these goals, the technical scheme taken of the present invention is：
Based on compressing file and contactless FPGA Dynamic Configurations, comprise the following steps：
(1) building includes hanging with configuration FLASH and the wireless communication module corresponding with external processing apparatus on hardware, and
Inside solidification has wireless receiving module, data decompression module, in-system programming module and configuration file to insmod program
Target FPGA；
(2) external processing apparatus are compressed using the target FPGA configuration file that lossless compression algorithm is generated to it, are obtained
Configuration file after to compression, and address is originally written into according to the size and number specified configuration file of configuration file；
(3) external processing apparatus wirelessly send out the address that is originally written into of configuration file after compression and configuration file
It is sent to target FPGA；
(4) target FPGA is write by configuration file after the compression that wireless receiving module will be received and the initial of configuration file
Enter address to store in internal RAM；
(5) data decompression module of target FPGA reads configuration file after the compression in internal RAM, and solution is used to it
Compression algorithm carries out hardware decompression, obtains configuration file, while in-system programming module writes and target configuration file
Memory space in the corresponding configuration FLASH of FPGA since address is originally written into；
(6) dynamic configuration is carried out to target FPGA, realizes that step is：
The function option and installment file that (6a) external processing apparatus need to realize according to target FPGA, and sent out to target FPGA
The thermal starting address and configuration file for sending configuration FLASH corresponding with its selected configuration file are loaded into order；
(6b) target FPGA receives the thermal starting address of configuration FLASH corresponding with configuration file and configuration file is loaded into life
Order, starts configuration file and insmods, and the configuration file insmods and configuration is loaded into since the thermal starting address of configuration FLASH
File.
The present invention compared with prior art, has the following advantages that.
1st, the present invention is transmitted after configuration file is carried out Lossless Compression by external equipment, reduces the big of configuration file
It is small, the transmission time of configuration file is then shortened, and realize that hardware is decompressed with FPGA, improve configured rate.
2nd, configuration file by wireless transmission method is dealt into target FPGA by external processing apparatus in the present invention, it is to avoid showed
There is the defect for needing to need with connections such as downloading wire or netting twines by target FPGA and external processing apparatus in scheme, realize non-connecing
Property is touched, and then is improve and is used flexibility.
3rd, in the present invention in the direct FLASH by configuration file write-in configuration of the mode of target FPGA in-system programmings, no
Need to aid in FPGA to be configured with other CPLD or CPU, compared with prior art, reduce hardware complexity.
Brief description of the drawings
Fig. 1 is composition frame chart of the invention；
Fig. 2 realizes FB(flow block) for of the invention；
Fig. 3 be in the present invention target FPGA by the operational flowchart of configuration file write-in configuration FLASH；
Fig. 4 is the workflow diagram that configuration file insmods in the present invention.
Specific embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail；
Reference picture 1, the present invention is included with lower module：
Module B10, external processing module；
Requirement in the present invention to external processing module is：Computer with wireless files sending function, in this implementation
Using the notebook computer with blue tooth interface in example, bluetooth transceiver module is hung with outside target FPGA.
Module B11, wireless transmission method；
Wireless transmission method refers to any mode that file can be just transmitted without contact, is sent out using bluetooth in the present embodiment
Send；
Module B12, wave point；
Physical layer when wave point is for doing reception of wireless signals, is mainly responsible for being wirelessly transferred and target FPGA between
Level conversion function, wave point uses bluetooth transceiver module in the present embodiment；
Module B13, target FPGA；
Target FPGA refers to the FPGA for receiving dynamic configuration, and the requirement in the present invention to target FPGA has at 2 points, first must
Must be the FPGA based on SRAM structures, secondly internal to have the BRAM for being more than 1MB, target fpga chip is adopted in the present embodiment
With the XC7K325T-FFG900 of Xilinx companies；
Module B14, configures FLASH；
Configuration FLASH is used for storing the configuration file of target FPGA, and the requirement in the present invention to configuration FLASH is held for storage
Amount have to be larger than 128MB, and FLASH model JS28F00AP30 are configured in the present embodiment, and memory capacity is 128MB.
Reference picture 2, the present invention is comprised the following steps：
Step S10, builds inside solidification wireless receiving module, data decompression module, in-system programming module and matches somebody with somebody
File is put to insmod the target FPGA of program；
From the characteristic of FPGA, can all become white tiles after upper electricity every time, it is necessary to which carrying out configuration to it could work.This reality
FPGA in example is applied to be configured using FLASH, i.e., be have cured in FLASH comprising wireless receiving module, data decompression module,
The configurator that System Programming module and configuration file insmod, after the power-up, FPGA can be loaded into configuration file from FLASH
Complete FPGA configurations.
Step S11, external processing apparatus carry out Lossless Compression to the configuration file of target FPGA；
The FLASH configuration files size of XC7K325T is 30MB, the file size after the compression of LZW lossless compression algorithms
It is 32KB.It is clear that being substantially reduced through the configuration file length after overcompression, reduce and sent to mesh from external processing apparatus
Mark the time of FPGA.
In the present embodiment, described configuration file can be that a configuration file can also be the different FPGA of multiple correspondences
The configuration file of function.If a configuration file, then the address that is originally written into for configuring FLASH is 0, if multiple is configured
File, then must carry out specified configuration FLASH according to the size of configuration file is originally written into address, it is to avoid repeat.
In the present embodiment, external processing apparatus must be compressed using lossless compression algorithm to configuration file, compression
It is divided into Lossless Compression and lossy compression method, Lossless Compression refers to that file can be reduced completely after compressing, and does not interfere with file content, is had
Damaging compression can reduce the data volume of original, it is impossible to which full backup goes out original, therefore the present embodiment selection LZW Lossless Compressions are calculated
Method is compressed to FPGA configuration file, and lzw algorithm is to set up dictionary immediately according to the difference of input data, and this strategy can
Ensure that the content in current dictionary can be with maximally effective compression present input data to greatest extent, and lzw algorithm principle is relative
Simply, hardware realization is especially suitable for, this in target FPGA to realizing that decompression lays the foundation later.
Configuration file after compression is sent to target FPGA by step S12, external processing apparatus；
In the present embodiment, external processing apparatus are the notebook computer for possessing blue tooth interface, after being compressed with lzw algorithm
FPGA configuration file the target FPGA for hanging with bluetooth module is sent to by way of Bluetooth transmission where board.
Step S13, target FPGA are in the file storage for receiving to internal RAM；
In the present embodiment, target FPGA have cured program in original state configuration FLASH, this program work(
Can include that wireless receiving module, data decompression module, in-system programming module, configuration file insmod.FPGA inside journey
Sequence real time scan these modules, the data that will then be received when blue tooth interface has data to transmit are stored in RAM, in the present embodiment
FPGA possesses the internal RAM resource of 2000KBytes, and configuration file after the compression of multiple size 32K can be stored completely.
Step S14, target FPGA contract configuration file decompression in write-in configuration FLASH；
Configuration file decompression is referred to by the target FPGA described in the present embodiment, when wireless receiving module will compression
After configuration file is received and writes FPGA internal RAMs afterwards, data decompression module is by the data read-out in RAM and decompresses,
Obtain configuration file, in-system programming module is responsible in configuration file write-in configuration FLASH, the decompression of configuration file and match somebody with somebody
File write-in configuration FLASH is put while carrying out, because there are 30MB sizes after configuration file decompression, FPGA inside is without this
Big memory space, while FPGA both can save setup time if carrying out, again can be without additional DDR chips as number
According to caching, hardware resource is saved.
Target FPGA described in the present embodiment will in configuration file write-in configuration FLASH, refer to target FPGA by
System Programming mode is by configuration file write-in configuration FLASH.Wherein in-system programming (In System Programming) is
Finger is wiped it or reprogram in the case where need not remove device from circuit board.It is this can be to circuit board or whole
Individual electronic system carries out the function of configuration or restructuring at any time, and to designing and developing, circuit board level debugging and system upgrade regenerate and bring
Greatly facilitate so that whole system design, production, safeguard and the link such as update and all there occurs revolutionary change.
Target FPGA is as shown in Figure 3 by the concrete operations flow of configuration file write-in FLASH in the present embodiment.
Step S15, external processing apparatus are loaded into order and thermal starting address to target FPGA send configurations file；
Be sent to for dynamic configuration initiation command and initial address by blue tooth interface by external processing apparatus in the present embodiment
The Bluetooth receptions module of target FPGA, target FPGA is responsible for receiving order and address.
Step S16, target FPGA start configuration file loading after being subject to order and address, complete dynamic configuration；
Target FPGA starts Dynamic Configuration Process in the present embodiment is realized by sending IPROG orders to ICAPE cores,
The effect of IPROG instructions is to carry out reset operation to fpga chip, and reset operation is answered the application program inside FPGA
Position, removes specialized configuration pin and JTAG pins in reseting procedure, other input/output pins are high-impedance state.Complete the behaviour that resets
After work, the load address that will be given tacit consent to is with new in thermal starting address register (Warm Boot Start Address, WBSTAR)
Replace address., it is necessary to be carried out to ICAPE cores pre-configured before IPROG instructions are sent.Heavily loaded control module is receiving triggering letter
After number, the write signal and chip selection signal of ICAPE cores are put height by first clock cycle, and second period sets low write signal, piece
Signal is selected to put height, the 3rd cycle sets low write signal, and chip selection signal also sets low.Then in eight following clock cycle,
Control command in instruction queue is sent one by one.During state machine sends IPROG instructions, in order to ensure ICAPE cores
Correct instruction is received, each order for sending and data must comply with SelectMAP data orders.
SelectMAP data orders are that each instruction is divided by byte, and the data of each byte press bit bit flipping after division.
Specific operating process is as shown in Figure 4.
Reference picture 3, be in the present invention target FPGA by the operational flowchart of configuration file write-in configuration FLASH；
Step S141, external processing apparatus send thermal starting address to target FPGA and configuration file is loaded into order；
In the present embodiment, thermal starting address represents the initial address that configuration file is loaded into, the configuration file size after compression
It is 32K bytes, a width of 16 of the data wire of FLASH, a width of 26 of address wire, two high temporarily take less than, so setting is initial
Address is 24 ' h000000, and end address is 24 ' h004000.If there are two configuration files, second configuration file can be set
Be originally written into address for 24 ' h005000, end address is 24 ' h009000.The specified of initial address is to not allow configuration
File occurs to repeat or covers in write-in.
Step S142, FPGA send unblock unlock orders；
In the present embodiment, FLASH model PC28F00AP30, unlocking command is two orders of clock cycle, first
Clock cycle, 0x60 is sent to block address, second clock cycle, 0x90 is sent, after FLASH receives continuous two byte command
Unblock operation can be performed.
Step S143, judges whether FLASH unlocks；
In the present embodiment, it is the status register that FLASH is read by FPGA to judge whether FLASH unlocks, by state
The value of register come judge whether unblock.FPGA reads the status register of FLASH by sending 0x90 to FLASH, such as
The value of fruit register is 0x80, illustrates that FLASH unblocks are finished, and can carry out next step, is otherwise continued waiting for, until having unlocked
Finish；
Step S144, FPGA send erasing erase orders；
In the present embodiment, configuration FLASH is NOR FLASH, is learnt by the characteristic of FLASH, if wanting to be programmed FLASH
Operation, first must be by its all storage locations 1, i.e. erasing operation.Erasing order is also two orders of clock cycle, first
Clock cycle, 0x20 block erasing orders are sent to FLASH, second clock cycle, send 0xD0 block erase-verifying orders；
Step S145, judges whether FLASH wipes successfully；
It is successfully the status register that FLASH is read by FPGA to judge whether FLASH wipes in the present embodiment, by shape
The value of state register judges whether to wipe what is finished.Target FPGA sends 0x90 orders to FLASH, reads FLASH states and posts
Storage, judges whether status register value is 0x80, if, then it represents that wipe successfully, if it is not, then continuing waiting for.Should be noted
Be FLASH erasing it is slower, the typical erasing time be 800ms；
Step S146, FPGA send programming program orders；
In the present embodiment, program command is two orders of clock cycle, and first clock cycle, FPGA sends out to FLASH
0xE8 is sent, represents that programming starts, second clock cycle order 0xD0 is sent after being finished etc. data write-in, represent that data have write
Into；
Configuration file after compression is read and decompressed by step S147, FPGA from RAM；
In the present embodiment, after FPGA sends 0xE8 to FLASH represents that programming starts, data decompression module starts to press
Configuration file is read and decompresses from RAM after contracting, and decompression is realized by FPGA internal datas decompression module.
Step S148, FPGA are by configuration file write-in configuration FLASH；
In the present embodiment, the buffer programming mode of FLASH programmings, the depth of buffer is set to 512 bytes, that is,
Say that FPGA is continuous and 512 bytes are write into data buffer zone, then this 512 byte is write corresponding block by FLASH, in the present embodiment
Data are write and the data read-out decompression of step 147 is all carried out simultaneously, can so be cached without outside DDR storages
Data after decompression, save hardware cost.
Step S149, judges whether FLASH programs successfully；
In the present embodiment, FPGA judges whether FLASH programs successfully, is to send 0x90 orders by FLASH, reads
FLASH status registers, judge whether status register value is 0x80, if, then it represents that program successfully, if not, then it represents that number
According to being currently written into.
Reference picture 4, target FPGA starts the workflow diagram of dynamic configuration in the present invention；
Step S161, target FPGA receive thermal starting address and configuration file is loaded into order；
In the present embodiment, FPGA internal Bluetooth receiver modules are responsible for receiving thermal starting address and configuration file is loaded into order；
Step S162, height is set to by the write signal and chip selection signal of ICAPE cores；
In the present embodiment, if Bluetooth receptions module receives the dynamic configuration initiation command that external processing apparatus send, will
The write signal and chip selection signal original state of ICAPE cores are set to height.During ICAPE cores are the special composing software ISE of Xilinx
Proprietary IP kernel, needs that peration data bandwidth (X8, X16, X32 Three models), this implementation are determined and adjusted according to design when calling
X32 patterns are used in example；
Step S163, the write signal of ICAPE cores is set low and puts height with chip selection signal；
In the present embodiment, the write signal of ICAPE cores is set low, allow write signal effectively, chip selection signal puts height, i.e., temporarily also not
ICAPE cores are allowed to work；
Step S164, the write signal and chip selection signal of ICAPE cores are all set low；
In the present embodiment, chip selection signal is set low, allow ICAPE cores to start working；
Step S165, sends 8 IPROG instructions in cycle；
In the present embodiment, IPROG instructions are 8 clock cycle instructions, and FFFFFFF is sent first, represent dummy data, then
AA995566 is sent, synchronization character is represented, 20000000 are then sent, represents idle, then send 30020001, represented to starting
Address register writes 1, is opened followed by most important thermal starting address (WBSTSR), that is, the heat that external processing apparatus send
Dynamic address, next sends 30008001, represents that command register writes 1, then sends 0000000F, represents that operation IPROG refers to
Order, finally sends 20000000, represents that order fulfillment returns to the free time.In order to ensure that ICAPE cores are properly received instruction and data, need
Order adjustment is carried out according to bit to the data for operating.Regulation rule is：Data are divided by byte, the data after division are every
Byte is overturn by bit.FPGA specialized configurations logic starts to perform internal reset operation after IPROG instructions are received,
Original program in erasing internal memory, and the thermal starting address in WBSTAR, the heat from FLASH chip pointed by WBSTAR
Start address bit to start to read FPGA configuration bit stream datas, complete FPGA configurations.
The preferred embodiments of the present invention are these are only, is not thereby limited the scope of the invention, it is every to utilize this hair
Equivalent structure and equivalent flow conversion that bright specification and accompanying drawing content are done, or directly or indirectly it is used in other related skills
Art field, similarly includes within the scope of the present invention.
Claims (6)
1. it is a kind of based on compressing file and contactless FPGA Dynamic Configurations, it is characterised in that to comprise the following steps：
(1) building includes hanging with configuration FLASH and the wireless communication module corresponding with external processing apparatus on hardware, and internal
Wireless receiving module, data decompression module, in-system programming module and configuration file is solidified with to insmod the target of program
FPGA；
(2) external processing apparatus are compressed using the target FPGA configuration file that lossless compression algorithm is generated to it, are pressed
Configuration file after contracting, and address is originally written into according to the size and number specified configuration file of configuration file；
(3) wirelessly be sent to for the address that is originally written into of configuration file after compression and configuration file by external processing apparatus
Target FPGA；
(4) target FPGA is originally written into ground by configuration file after the compression that wireless receiving module will be received and configuration file
Location is stored in internal RAM；
(5) data decompression module of target FPGA reads configuration file after the compression in internal RAM, and decompression is used to it
Algorithm carries out hardware decompression, obtains configuration file, while in-system programming module writes and target FPGA pairs configuration file
Memory space in the configuration FLASH for answering since address is originally written into；
(6) dynamic configuration is carried out to target FPGA, realizes that step is：
(6a) external processing apparatus according to target FPGA need realize function option and installment file, and to target FPGA send with
The thermal starting address of the corresponding configuration FLASH of its selected configuration file and configuration file are loaded into order；
(6b) target FPGA receives the thermal starting address of configuration FLASH corresponding with configuration file and configuration file is loaded into order,
Start configuration file to insmod, the configuration file insmods to be loaded into since the thermal starting address of configuration FLASH and configures text
Part.
2. according to claim 1 based on compressing file and contactless FPGA Dynamic Configurations, it is characterised in that
Configuration file described in step (2), its quantity is one or more, and the plurality of configuration file corresponds to different FPGA functions,
If the quantity of configuration file is one, the address that is originally written into of its corresponding configuration FLASH is 0, if the quantity of configuration file
It is multiple, then should specifies configuration FLASH's corresponding with each configuration file to be originally written into address according to the size of configuration file.
3. according to claim 1 based on compressing file and contactless FPGA Dynamic Configurations, it is characterised in that
Decompression algorithm described in step (5), its by FPGA code realize, and with step (2) in use lossless compression algorithm
It is corresponding.
4. according to claim 1 based on compressing file and contactless FPGA Dynamic Configurations, it is characterised in that
In-system programming module described in step (5) realizes step by configuration file write-in configuration FLASH corresponding with target FPGA
It is rapid as follows：
(5a), in-system programming module send unblock unlock orders, erasing successively to configuration FLASH corresponding with target FPGA
Erase orders and programming program orders；
Configuration file after compression is read and decompressed by (5b), data decompression module from RAM, while in-system programming module will
Configuration file after decompression is write in configuration FLASH corresponding with target FPGA.
5. according to claim 1 based on compressing file and contactless FPGA Dynamic Configurations, it is characterised in that
Thermal starting address described in step (6a), its with step (2) configuration file to be originally written into address identical.
6. according to claim 1 a kind of based on compressing file and contactless FPGA Dynamic Configurations, its feature
It is that the startup configuration file described in step (6b) insmods, configuration is loaded into since the thermal starting address of configuration FLASH
File, realizes that step is as follows：
(6b1), configuration file to insmod and be set to height by the write signal and chip selection signal of ICAPE cores；
(6b2), configuration file insmod and set low the write signal of ICAPE cores, and chip selection signal puts height；
(6b3), configuration file insmod and set low the write signal and chip selection signal of ICAPE cores；
(6b4), configuration file to insmod and send 8 IPROG instructions in cycle to ICAPE cores, and the 5th cycle is thermal starting ground
Location, starts file and is loaded into process.
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| CN107450948A (en) * | 2017-07-28 | 2017-12-08 | 西安电子科技大学 | A kind of FPGA adaptive allocation method and system of low-power consumption |
| CN108037695A (en) * | 2017-11-29 | 2018-05-15 | 深圳市紫光同创电子有限公司 | Field programmable gate array and its method of automatic configuration |
| CN110909317A (en) * | 2019-11-19 | 2020-03-24 | 天津津航计算技术研究所 | General encryption method for FPGA storage program |
| CN111158761A (en) * | 2019-11-28 | 2020-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | Method for rapidly loading power-on configuration information of PowerPC processor through FPGA |
| CN111176911A (en) * | 2019-11-18 | 2020-05-19 | 北京时代民芯科技有限公司 | Novel large-storage-capacity high-speed FPGA auxiliary configuration system |
| CN111190855A (en) * | 2019-12-13 | 2020-05-22 | 南京理工大学 | FPGA multiple remote configuration system and method |
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| CN107450948B (en) * | 2017-07-28 | 2019-10-08 | 西安电子科技大学 | A kind of FPGA adaptive allocation method and system of low-power consumption |
| CN107450948A (en) * | 2017-07-28 | 2017-12-08 | 西安电子科技大学 | A kind of FPGA adaptive allocation method and system of low-power consumption |
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| CN108037695A (en) * | 2017-11-29 | 2018-05-15 | 深圳市紫光同创电子有限公司 | Field programmable gate array and its method of automatic configuration |
| CN111176911B (en) * | 2019-11-18 | 2023-08-08 | 北京时代民芯科技有限公司 | Novel high-speed FPGA auxiliary configuration system of large storage capacity |
| CN111176911A (en) * | 2019-11-18 | 2020-05-19 | 北京时代民芯科技有限公司 | Novel large-storage-capacity high-speed FPGA auxiliary configuration system |
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| CN111158761B (en) * | 2019-11-28 | 2022-12-06 | 中国航空工业集团公司西安航空计算技术研究所 | Method for rapidly loading power-on configuration information of PowerPC processor through FPGA |
| CN111158761A (en) * | 2019-11-28 | 2020-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | Method for rapidly loading power-on configuration information of PowerPC processor through FPGA |
| CN111190855A (en) * | 2019-12-13 | 2020-05-22 | 南京理工大学 | FPGA multiple remote configuration system and method |
| CN111857866A (en) * | 2020-06-29 | 2020-10-30 | 浪潮电子信息产业股份有限公司 | Loading method and device of multiple dynamic cores and computer readable storage medium |
| CN111857866B (en) * | 2020-06-29 | 2022-06-17 | 浪潮电子信息产业股份有限公司 | Loading method and device of multiple dynamic cores and computer readable storage medium |
| CN114168085A (en) * | 2021-12-16 | 2022-03-11 | 潍柴动力股份有限公司 | Variable processing method, device, equipment and storage medium |
| CN114168085B (en) * | 2021-12-16 | 2024-02-20 | 潍柴动力股份有限公司 | Variable processing method, device, equipment and storage medium |
| CN114696837A (en) * | 2022-02-18 | 2022-07-01 | 电子科技大学 | Bit stream decompression method for FPGA security analysis |
| CN114696837B (en) * | 2022-02-18 | 2023-03-07 | 电子科技大学 | Bit stream decompression method for FPGA security analysis |
| CN116541898A (en) * | 2023-07-07 | 2023-08-04 | 山东多次方半导体有限公司 | FPGA-based reconfigurable password card design method for realizing multiple algorithms |
| CN116541898B (en) * | 2023-07-07 | 2023-10-13 | 山东多次方半导体有限公司 | FPGA-based reconfigurable password card design method for realizing multiple algorithms |
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