CN115061942B - Downloading verification method and device for configuration code of programmable logic device - Google Patents
Downloading verification method and device for configuration code of programmable logic device Download PDFInfo
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- CN115061942B CN115061942B CN202211002514.1A CN202211002514A CN115061942B CN 115061942 B CN115061942 B CN 115061942B CN 202211002514 A CN202211002514 A CN 202211002514A CN 115061942 B CN115061942 B CN 115061942B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a download verification method and a download verification device for code allocation of a programmable logic device, which are characterized in that a programmable power supply is arranged, all test data are collected together, before a test program sequentially reads each time of test code stream data, the programmable power supply is used for powering off an FPGA and then powering on again to read in the test code stream data, so that the automation of the test process is realized, compared with the prior art that the test is frequently downloaded and programmed many times manually, the technical requirements on testers are reduced, the test efficiency is greatly improved, and the test cost is reduced.
Description
Technical Field
The invention belongs to the field of software testing in the field of programmable logic devices, and particularly relates to a method and a device for downloading verification of configuration codes of a programmable logic device.
Background
The FPGA EDA software generates a binary bit stream file, namely a code stream file, by comprehensively mapping, boxing, arranging, wiring and distributing codes to a hardware circuit, and finally burns the generated code stream file into an FPGA chip, the FPGA EDA burnt code stream can be downloaded through a JTAG, and can also be burnt into Flash through the JTAG, and in the test process, the success rate of JTAG downloading, the success rate of Flash burning and the average duration required by Flash burning can be obtained only by manually downloading and burning tests frequently for many times.
Disclosure of Invention
The invention aims to solve the technical problem of how to automatically carry out code stream downloading programming test without carrying out downloading programming of code streams frequently to complete test work manually, and provides a downloading verification method and a downloading verification device for code allocation of a programmable logic device.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a download verification method for configuration codes of a programmable logic device comprises the following steps:
step 1: writing prepared data information of different test code streams into a test data file together;
and 2, step: setting a program-controlled power supply, configuring the output voltage of the program-controlled power supply, and connecting the program-controlled power supply and the FPGA chip;
and step 3: running a test program, sequentially reading parameter information of the test code stream data according to the sequence of different test code stream data in the test data file, and performing configuration test on the FPGA;
and 4, step 4: after the test of the current test code stream is finished, before the next test code stream is read in, the programmable power supply is controlled to be turned off and then turned on, the test result of the current test code stream data configuration test is recorded, and the parameter information of the next test code stream data is read in;
and 5: and returning to the step 4 until all the test code stream data in the test data file are configured and tested.
Further, the method also comprises the step 6: and (4) counting the test results under each test, and calculating the programming success rate and the programming duration.
Furthermore, the parameter information of the test code stream data sequentially read in step 3 is to download the code stream to the FPGA chip through the JTAG interface.
Furthermore, the parameter information of the test code stream data sequentially read in step 3 is to first write the test code stream data into Flash, and then the FPGA chip loads the code stream information from Flash.
Furthermore, the test data file comprises the serial number of each test code stream, the storage path of each test code stream, the downloading mode of the test code streams, the parameter of Flash programming and the address of the test program.
Further, the test data file also includes whether each test code stream data is an encrypted code stream and a key for encrypting the code stream.
Further, when the configuration test is performed on the FPGA in step 3, it is determined whether the code stream data of this test is an encrypted code stream, if so, the key of the code stream data of this test is read from the test data file, and the encrypted code stream and the key are configured into the FPGA.
The invention also provides a download verification device for the configuration code of the programmable logic device, which comprises the following modules:
the test data file generation module: the device is used for writing prepared data information of different test code streams into a test data file together;
the program-controlled power supply module: the FPGA chip is used for setting a programmable power supply, configuring the output voltage of the programmable power supply and connecting the programmable power supply and the FPGA chip;
configuring a test module: the system comprises a test data file, a FPGA (field programmable gate array) and a test data file, wherein the test data file is used for storing different test code stream data;
a test result generation module: the system is used for controlling the program-controlled power supply to be turned off and then turned on before the next test code stream is read after the test of the current test code stream is finished, recording the test result of the configuration test of the current test code stream data, and reading the parameter information of the next test code stream data;
a circulation module: and the test result generating module is used for returning the test result until all the test code stream data in the test data file are configured and tested.
Further, still include the statistics module: and the test result generation module is used for counting the test results generated by the test result generation module under each test, and calculating the programming success rate and the programming duration.
By adopting the technical scheme, the invention has the following beneficial effects:
according to the download verification method and device for the programmable logic device code allocation, the programmable power supply is arranged, all test data are collected together, before the test program sequentially reads each time of test code stream data, the programmable power supply is used for powering off the FPGA and then powering on again to read in the test code stream data, automation of the test process is achieved, compared with the prior art that frequent manual download programming tests are needed many times, technical requirements on testers are reduced, meanwhile, test efficiency is greatly improved, and test cost is reduced.
Drawings
FIG. 1 is a flow chart of the system of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 shows a specific embodiment of a method for downloading verification of configuration code of a programmable logic device, including the following steps:
step 1: and writing the prepared data information of different test code streams into a test data file together. In this embodiment, the test data file includes the serial number of each test code stream, the storage path of each test code stream, the download mode of the test code stream, the parameter of Flash programming, and the address of the test program.
Step 2: setting a program-controlled power supply, configuring the output voltage of the program-controlled power supply, and connecting the program-controlled power supply and the FPGA chip;
and step 3: and running a test program, sequentially reading parameter information of the test code stream data according to the sequence of different test code stream data in the test data file, and performing configuration test on the FPGA.
In this embodiment, the test code stream data is configured into the FPGA chip for configuration test in two ways, one is to download the code stream into the FPGA chip through the JTAG interface, and the other is to first write the test code stream data into Flash, and then the FPGA chip loads the code stream information from Flash.
In the embodiment, the power-off and power-on of the FPGA are controlled by the programmable power supply, after the FPGA is powered on again, new test code stream data is configured in the FPGA, different test code stream data information can be written into a test data file together due to the programmable power supply, before each time of test code stream data is read in sequence, the FPGA is powered off again by the programmable power supply to enable the test code stream data to be configured, the automation of a test process is realized, compared with the downloading and programming test which needs to be frequently and manually carried out for multiple times in the prior art, the technical requirements on testers are reduced, meanwhile, the test efficiency is greatly improved, and the test cost is reduced. Because FPGA configuration tests require a large amount of data, often tests are verified thousands of times each time, and if verification is performed manually, the test time is long and is almost difficult to complete. By using the embodiment, after the test data file is finished, the test program can be automatically finished, and the test verification work of batch repeatability can be carried out without manual participation, thereby avoiding the error of manual operation.
When the test code stream data is the encrypted code stream, the test code stream data is written into the test data file, and the key for encrypting the code stream is written simultaneously. When the test code stream data are sequentially configured into the FPGA, judging whether the test code stream data are encrypted code streams, if so, reading a secret key of the test code stream data from a test data file, and configuring the encrypted code streams and the secret key into the FPGA.
And 4, step 4: after the test of the current test code stream is finished, before the next test code stream is read in, the program-controlled power supply is controlled to be turned off and then turned on, the test result of the current test code stream data configuration test is recorded, and the parameter information of the next test code stream data is read in;
and 5: returning to the step 4 until all the test code stream data in the test data file are configured and tested;
step 6: and (4) counting the test results under each test, and calculating the programming success rate and the programming duration.
The invention also provides a download verification device for the configuration code of the programmable logic device, which comprises the following modules:
the test data file generation module: the device is used for writing prepared data information of different test code streams into a test data file together;
the program-controlled power supply module: the FPGA chip is used for setting a programmable power supply, configuring the output voltage of the programmable power supply and connecting the programmable power supply and the FPGA chip;
configuring a test module: the system is used for running a test program, sequentially reading parameter information of the test code stream data according to the sequence of different test code stream data in the test data file, and performing configuration test on the FPGA;
a test result generation module: the system is used for controlling the program-controlled power supply to be turned off and then turned on before the next test code stream is read in after the test of the current test code stream is finished, and recording the test result of the data configuration test of the current test code stream;
a circulation module: and the test result generating module is used for returning the test result until all the test code stream data in the test data file are tested.
A statistic module: and the test result generation module is used for counting the test results generated by the test result generation module under each test, and calculating the programming success rate and the programming duration.
The download verification device provided by the invention has the advantages that the problem that the FPGA needs to be powered off and on when parameter information of code stream data is tested each time is read is realized by setting the program-controlled power supply, so that the problem that the download programming test needs to be frequently carried out manually for multiple times in the prior art is solved, the automation of the test process is realized, compared with the download programming test needing to be frequently carried out manually for multiple times in the prior art, the technical requirements on testers are reduced, the test efficiency is greatly improved, and the test cost is reduced. Especially for tests that are to be validated thousands of times, it is almost difficult to do if the validation is done manually.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A download verification method for configuration codes of a programmable logic device is characterized by comprising the following steps:
step 1: writing prepared data information of different test code streams into a test data file together;
step 2: setting a program-controlled power supply, configuring the output voltage of the program-controlled power supply, and connecting the program-controlled power supply and the FPGA chip;
and 3, step 3: running a test program, sequentially reading parameter information of the test code stream data according to the sequence of different test code stream data in the test data file, and performing configuration test on the FPGA;
and 4, step 4: after the test of the current test code stream is finished, before the next test code stream is read in, the programmable power supply is controlled to be turned off and then turned on, the test result of the current test code stream configuration test is recorded, and the parameter information of the next test code stream data is read in;
and 5: and returning to the step 4 until all the test code stream data in the test data file are configured and tested.
2. The download verification method according to claim 1, further comprising the step of 6: and (4) counting the test results under each test, and calculating the programming success rate and the programming duration.
3. The download verification method according to claim 2, wherein the parameter information sequentially read in the test code stream data in step 3 is downloaded to the FPGA chip through a JTAG interface.
4. The download verification method according to claim 2, wherein the step 3 of sequentially reading parameter information of the test code stream data comprises programming the test code stream data into Flash, and then loading the code stream information from Flash by the FPGA chip.
5. The download verification method according to claim 3 or 4, wherein the test data file comprises the serial number of each test code stream, the storage path of each test code stream, the download mode of the test code stream, the parameter of programming Flash, and the address of the test program.
6. The download verification method of claim 5, wherein the test data file further comprises whether each test code stream data is an encrypted code stream and a key for encrypting the code stream.
7. The download verification method according to claim 6, wherein when performing configuration test on the FPGA in step 3, determining whether the code stream data of this test is an encrypted code stream, if so, reading the key of the code stream data of this test from the test data file, and configuring the encrypted code stream and the key into the FPGA.
8. The download verification device for the configuration code of the programmable logic device is characterized by comprising the following modules:
the test data file generation module: the device is used for writing prepared data information of different test code streams into a test data file together;
the program-controlled power supply module: the FPGA chip is used for setting a programmable power supply, configuring the output voltage of the programmable power supply and connecting the programmable power supply and the FPGA chip;
configuring a test module: the system is used for running a test program, sequentially reading parameter information of the test code stream data according to the sequence of different test code stream data in the test data file, and performing configuration test on the FPGA;
a test result generation module: the system is used for controlling the program-controlled power supply to be turned off and then turned on before the next test code stream is read after the test of the current test code stream is finished, recording the test result of the data configuration test of the current test code stream, and reading the parameter information of the next test code stream data;
a circulation module: and the test result generating module is used for returning the test result until all the test code stream data in the test data file are configured and tested.
9. The download verification apparatus of claim 8, further comprising a statistics module: and the test result generation module is used for counting the test results generated by the test result generation module under each test and calculating the programming success rate and the programming duration.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106291336A (en) * | 2016-07-15 | 2017-01-04 | 上海华岭集成电路技术股份有限公司 | A kind of FPGA real-time method for down loading of test configurations code stream and system |
| CN111176911A (en) * | 2019-11-18 | 2020-05-19 | 北京时代民芯科技有限公司 | Novel large-storage-capacity high-speed FPGA auxiliary configuration system |
| CN113485879A (en) * | 2021-07-06 | 2021-10-08 | 中国电子科技集团公司第五十八研究所 | Labview-based automatic testing method for calling vivado-tcl script |
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| CN114895957A (en) * | 2022-04-15 | 2022-08-12 | 西安广和通无线通信有限公司 | Upgrade test system, method and storage medium |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106291336A (en) * | 2016-07-15 | 2017-01-04 | 上海华岭集成电路技术股份有限公司 | A kind of FPGA real-time method for down loading of test configurations code stream and system |
| CN111176911A (en) * | 2019-11-18 | 2020-05-19 | 北京时代民芯科技有限公司 | Novel large-storage-capacity high-speed FPGA auxiliary configuration system |
| CN113485879A (en) * | 2021-07-06 | 2021-10-08 | 中国电子科技集团公司第五十八研究所 | Labview-based automatic testing method for calling vivado-tcl script |
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