CN113485879A

CN113485879A - Labview-based automatic testing method for calling vivado-tcl script

Info

Publication number: CN113485879A
Application number: CN202110763875.7A
Authority: CN
Inventors: 钱宏文; 刘继祥; 刘会; 廖明勋
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2021-07-06
Filing date: 2021-07-06
Publication date: 2021-10-08

Abstract

The invention discloses a method for calling a vivado-tcl script to automatically test based on labview, and belongs to the field of digital circuits and automatic test. Creating a vivado-tcl script; creating a bat script, and calling a vivado-tcl script through the bat script to realize the automatic burning of the FPGA code; the labview completes the realization of the bat- > vivado-tcl function by executing a system command; and the upper computer completes the overall index and function verification of the product. The invention not only solves the function verification of JTAG interface in batch production, but also realizes the automatic downloading of FPGA file and the automatic testing of index; the one-key automatic test saves the test time, improves the test efficiency, reduces the workload of operators and reduces the complexity of the work.

Description

Labview-based automatic testing method for calling vivado-tcl script

Technical Field

The invention relates to the technical field of digital circuits and automatic testing, in particular to an automatic testing method for invoking a vivado-tcl script based on labview.

Background

Communication, consumer electronics and automotive electronics are application scenarios of downstream stock of the FPGA, and the market scale is continuously increased. Due to the three advantages over ASICs: flexibility, time-to-market, cost, and rich downstream application scenarios for FPGAs, including ASIC prototyping, automotive electronics, transceivers, consumer electronics, data centers, high performance computing, industrial, medical, testing/measurement, wired/wireless communications, and the like. Tcl (read as tick) was born in university of california at 80 s, berkeley, and is currently widely used in almost all EDA tools as a simple, efficient and well-portable scripting language. The biggest characteristic of Tcl is that its syntax format is very simple and even rigid, and it is a genuine "Tool Command Language" in the form of pure [ Command option parameter ] (i.e. the full name of Tcl, Tool Command Language).

The downloading of the FPGA program needs to use a special emulator to be interconnected with the JTAG in the hardware circuit to complete the downloading or updating of the program, so the JTAG interface function is particularly important. Usually, the function verification of the JTAG interface is completed by designers, and when a product is produced in batches, the product testing efficiency cannot be improved by manual operation, so that the cost is high.

Disclosure of Invention

The invention aims to provide an automatic testing method for calling a vivado-tcl script based on labview, so as to solve the problems in the background technology.

In order to solve the technical problem, the invention provides an automatic testing method for calling a vivado-tcl script based on labview, which comprises the following steps:

step one, creating a vivado-tcl script;

step two, creating a bat script, and calling a vivado-tcl script through the bat script to realize automatic burning of the FPGA code;

step three, the labview completes the bat- > vivado-tcl function realization by executing the system command;

and step four, the upper computer completes the verification of the overall indexes and functions of the product.

Optionally, the vivado-tcl script supports multi-product sequential testing, the vivado-tcl script includes functions required by the project, and the project completes JTAG interface function testing and FPGA code burning.

Optionally, in the first step, the creation of the vivado-tcl script is completed according to the model of the FPGA and the engineering path; starting- > running, inputting cmd, inputting 'vivado-modematch-source tcl _ sample.tcl' under a Windows interface, and finishing the function verification of a vivado-tcl script and a JTAG interface; and starting the upper computer software to complete the overall index and function test of the product.

Optionally, in the second step, the "vivado-modematch-source tcl _ sample. tcl" is written into an automatic script file, and automatic burning is performed through the bat script file, so that the calling of the upper computer is facilitated.

Optionally, in the third step, labview completes bat- > vivado-tcl call by executing a system command, and realizes one-key download.

Optionally, in the fourth step, the upper computer performs instruction and data interaction with the lower computer through the USB, mainly completes functional tests of SNR, IO, voltage and current, BIT state, and USB rate, and outputs a test conclusion statement.

In the automatic testing method for calling the vivado-tcl script based on labview, which is provided by the invention, the vivado-tcl script is created; creating a bat script, and calling a vivado-tcl script through the bat script to realize the automatic burning of the FPGA code; the labview completes the realization of the bat- > vivado-tcl function by executing a system command; and the upper computer completes the overall index and function verification of the product. The invention not only solves the function verification of JTAG interface in batch production, but also realizes the automatic downloading of FPGA file and the automatic testing of index; the one-key automatic test saves the test time, improves the test efficiency, reduces the workload of operators and reduces the complexity of the work.

Drawings

FIG. 1 is a block diagram of a process sub-assembly test system;

FIG. 2 is a process sub-assembly test flow diagram;

FIG. 3 is a detailed test chart of the process subassembly;

FIG. 4 is a process subassembly test software interface;

FIG. 5 is a batch command;

FIG. 6 is FPGA-tcl code.

Detailed Description

The automated testing method for invoking the vivado-tcl script based on labview provided by the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

FIG. 1 is a block diagram of a test system for a processing subassembly, which includes two parts, hardware and software, wherein the hardware includes a PC, a test box and a product to be tested; the product to be tested mainly comprises an FPGA circuit, an AD sampling circuit, a phase-locked loop circuit, a level conversion circuit, a 422 bus circuit, a discrete signal acquisition circuit, an LVDS output circuit and the like; the host computer passes through the USB HUB and connects 4 products that await measuring, and the test of 4 products can be supported simultaneously to the test box. The software comprises: vivado, labview, matlab (dll library), etc.; wherein labview is a program development environment. The test process is initiated by the test equipment, the test result is judged by the test equipment, the test equipment uploads the test data to the upper computer through the RS485 interface, and finally the test result is displayed by the upper computer.

FIG. 2 is a process subassembly test flow diagram. The testing process is mainly divided into two parts, namely, an upper computer clicks a FPGA one-key burning button, labview calls an automatic script through a system command, a vivado-tcl script command is guided to carry out FPGA code burning, after batch burning is finished, a tested product is electrified again, PID and VID can be correctly identified, the burning is successful, and therefore the function of a JTAG interface is proved to be normal; and secondly, operating an automatic test button by inputting an excitation signal from the outside to complete other function tests, verification and generate a test report.

Fig. 3 is a detailed test chart of the process subassembly. The USB-hub is connected with the PC and the simulator and carries out FPGA code burning; the test box and the test box are interconnected to a port of a PC (personal computer) through a 485 bus, the test box and a slot position of the test box jointly determine a USB VID (video identification) number, each byte is arranged, the test box is provided with a test box number (example h ' 01) through a jumper cap, one test box can test four products, and fixed numbers (respectively representing h ' 01, h ' 02, h ' 03 and h ' 04) are distributed by an FPGA (field programmable gate array). And the upper computer completes the online state detection of the product through the PID VID and completes the subsequent function test.

FIG. 4 is a test software interface for processing the subassembly, the test software being divided into a control area, a display area, and test results according to function; the control area supports two modes of manual testing and automatic testing, has USB speed testing, cyclic power up and down, high and low levels, bias voltage and input amplitude setting, and displays power supply voltage and current and attenuation coefficient in real time; the display area comprises an IO signal state, a BIT/422 state and waveform information; the test result comprises test times, qualification times, abnormal times and specific abnormal information.

FIG. 5 is a batch command. And starting a vivado project in a script batch processing mode through a 'vivado-mode batch-source file.tcl' command, and directly executing a file.tcl file after running.

FIG. 6 is FPGA-tcl code. Adding an equipment burning process according to actual needs to finish the automatic burning of the FPGA codes.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A method for calling a vido-tcl script automatic test based on labview is characterized by comprising the following steps:

step one, creating a vivado-tcl script;

2. The automated labview-based Vivado-tcl script testing method of claim 1, wherein the Vivado-tcl script supports multi-product sequential testing, the Vivado-tcl script comprises functions required by the project, and the project completes JTAG interface function testing and FPGA code burning.

3. The automated testing method for invoking the vido-tcl script based on labview as claimed in claim 2, wherein in the first step, the creation of the vido-tcl script is completed according to the model number of the FPGA and the engineering path; starting- > running, inputting cmd, inputting 'vivado-modematch-source tcl _ sample.tcl' under a Windows interface, and finishing the function verification of a vivado-tcl script and a JTAG interface; and starting the upper computer software to complete the overall index and function test of the product.

4. The automated labview-based Vivado-tcl script testing method of claim 1, wherein in the second step, "vivado-modebratch-source tcl _ sample.tcl" is written into an automated script file, and automatic burning is performed through a bat script file, so that the invocation of an upper computer is facilitated.

5. The automated testing method for a script called a video-tcl based on labview of claim 1, wherein in the third step, labview performs bat- > video-tcl calling by executing system command, and realizes one-key downloading.

6. The labview-based automatic testing method for the vidodo-tcl script, as claimed in claim 1, wherein in the fourth step, the upper computer performs command and data interaction with the lower computer through a USB, mainly completes functional tests of SNR, IO, voltage current, BIT state and USB rate, and outputs a test conclusion and report.