CN116956790A - Simulation verification method, device, equipment and medium - Google Patents
Simulation verification method, device, equipment and medium Download PDFInfo
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- 238000012795 verification Methods 0.000 title claims abstract description 269
- 238000004088 simulation Methods 0.000 title claims abstract description 201
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a simulation verification method, a simulation verification device, simulation verification equipment and simulation verification media, and relates to the technical field of integrated circuits. The simulation verification method is applied to a simulation verification platform provided with an external hardware accelerator, and comprises the following steps: constructing and calling a verification script; loading a tested object by using a hardware accelerator; performing hardware interface driving test according to simulation verification data of the verification script and outputting a simulation verification result, wherein the hardware interface driving test is used for driving a hardware interface of a hardware accelerator for testing a tested object; and finishing simulation verification according to the simulation verification result. Since the hardware interface for calling the hardware accelerator is used, the need for additional steps or processes to drive the hardware interface is avoided, thereby improving the simulation verification rate.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a method, an apparatus, a device, and a medium for simulation verification.
Background
Along with the continuous development of integrated circuit chips, the technology is more and more complex while the integrated circuit chips are miniaturized, and in order to ensure the correct application of the integrated circuit chips, the integrated circuit chips are subjected to simulation verification. When the integrated circuit chip is subjected to simulation verification, an existing simulation verification platform is generally used, and because the existing simulation verification platform is based on event verification, the simulation verification platform is suitable for the integrated circuit chip taking discrete time, state and variable as the tested object, and therefore the verification rate of the existing simulation verification platform is too slow.
In view of the above-mentioned problems, seeking to increase the simulation verification rate is a problem that the skilled person strives to solve.
Disclosure of Invention
The invention aims to provide a simulation verification method, device, equipment and medium, which are used for improving the simulation verification rate.
In order to solve the technical problems, the invention provides a simulation verification method which is applied to a simulation verification platform provided with an external hardware accelerator, and the method comprises the following steps:
constructing and calling a verification script;
loading a tested object by using a hardware accelerator;
performing hardware interface driving test according to simulation verification data of the verification script and outputting a simulation verification result, wherein the hardware interface driving test is used for driving a hardware interface of a hardware accelerator for testing a tested object;
and finishing simulation verification according to the simulation verification result.
On the other hand, performing the hardware interface drive test according to the simulated verification data of the verification script includes:
generating an excitation sequence according to constraint conditions in the verification script;
framing the excitation sequence to obtain a framed excitation sequence;
and transmitting the framing excitation sequence to perform hardware interface driving test.
In another aspect, after the transmitting the framing excitation sequence for the hardware interface driving test, the method further includes:
carrying out frame de-framing on the framing excitation sequence to obtain a de-framing excitation sequence after frame de-framing;
transmitting the de-framing excitation sequence to the tested object according to a preset time sequence.
On the other hand, after outputting the simulation verification result, before completing the simulation verification according to the simulation verification result, further comprising:
receiving a simulation verification result output by a hardware accelerator; the simulation verification result is obtained after framing and de-framing are sequentially carried out.
On the other hand, completing the simulation verification according to the simulation verification result includes:
sampling a simulation verification result and obtaining a reference verification result by using a reference model in a simulation verification platform;
judging whether the simulation verification result is consistent with the reference verification result;
if yes, recording a simulation verification result;
if not, ending.
On the other hand, after recording the simulation verification result, further comprising:
and carrying out coverage rate statistical analysis according to the simulation verification result, and outputting a coverage rate statistical analysis report.
On the other hand, after outputting the coverage statistical analysis report, it further includes:
constructing an operation script, wherein the operation script is used for managing a test database;
and expanding the test database on the condition of coverage rate statistical analysis report.
In order to solve the technical problems, the invention also provides a simulation verification device which is applied to a simulation verification platform provided with an external hardware accelerator; the device comprises:
the first construction module is used for constructing and calling a verification script;
the loading module is used for loading the tested object by utilizing the hardware accelerator;
the first transmission module is used for carrying out hardware interface driving test according to simulation verification data of the verification script and outputting a simulation verification result, wherein the hardware interface driving test is used for driving a hardware interface of a hardware accelerator for testing a tested object;
and the simulation verification module is used for completing simulation verification according to the simulation verification result.
Furthermore, the device comprises the following modules:
on the other hand, performing the hardware interface drive test according to the simulated verification data of the verification script includes:
the generation module is used for generating an excitation sequence according to the constraint conditions in the verification script;
the framing module is used for framing the excitation sequence to obtain a framed excitation sequence;
and the second transmission module is used for transmitting the framing excitation sequence to carry out hardware interface drive test.
In another aspect, after the transmitting the framing excitation sequence for the hardware interface driving test, the method further includes:
the frame-decoding module is used for carrying out frame decoding on the framing excitation sequence to obtain a frame-decoded excitation sequence;
and the third transmission module is used for transmitting the de-framing excitation sequence to the tested object according to a preset time sequence.
On the other hand, after outputting the simulation verification result, before completing the simulation verification according to the simulation verification result, further comprising:
the receiving module is used for receiving the simulation verification result output by the hardware accelerator; the simulation verification result is obtained after framing and de-framing are sequentially carried out.
On the other hand, completing the simulation verification according to the simulation verification result includes:
the sampling module is used for sampling a simulation verification result and obtaining a reference verification result by using a reference model in the simulation verification platform;
the judging module is used for judging whether the simulation verification result is consistent with the reference verification result;
if yes, triggering a recording module for recording a simulation verification result;
if not, ending.
On the other hand, after recording the simulation verification result, further comprising:
and the coverage rate statistical analysis module is used for carrying out coverage rate statistical analysis according to the simulation verification result and outputting a coverage rate statistical analysis report.
On the other hand, after outputting the coverage statistical analysis report, it further includes:
the second construction module is used for constructing an operation script which is used for managing the test database;
and the expansion module is used for expanding the test database under the condition of the coverage rate statistical analysis report.
In order to solve the technical problem, the invention also provides simulation verification equipment, which comprises:
a memory for storing a computer program;
and the processor is used for pointing to the computer program and realizing the steps of the simulation verification method.
In order to solve the technical problem, the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the all simulation verification method are realized.
The invention provides a simulation verification method, which is applied to a simulation verification platform provided with an external hardware accelerator, and comprises the following steps: constructing and calling a verification script; loading a tested object by using a hardware accelerator; performing a hardware interface driving test according to the simulation verification data of the verification script and outputting a simulation verification result, wherein the hardware interface driving test is used for driving and testing a hardware interface of the hardware accelerator of the tested object; and finishing simulation verification according to the simulation verification result. Since the hardware interface for calling the hardware accelerator is used, the need for additional steps or processes to drive the hardware interface is avoided, thereby improving the simulation verification rate.
The invention also provides a simulation verification device, equipment and medium, and the effects are the same as the above.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a simulation verification method provided by an embodiment of the invention;
FIG. 2 is a block diagram of a first simulation verification platform according to an embodiment of the present invention;
FIG. 3 is a block diagram of a second simulation verification platform according to an embodiment of the present invention;
FIG. 4 is a diagram of a simulation verification device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a simulation verification device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The core of the invention is to provide a simulation verification method, a device, equipment and a medium, which can improve the simulation verification rate.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
The universal verification methodology (Universal Verification Methodology, UVM) is a verification platform development framework based on a SystemVerilog class library, and a verification engineer can build a functional verification environment with a standardized hierarchical structure and interfaces using its reusable components. Among them, the SV language (SystemVerilog) is a verification language based on Verilog language, which combines hardware description language (Hardware Description Language, HDL) with modern high-level verification language (Hardware verification language, HVL).
UVM provides a set of authentication criteria libraries, including common base classes and methods, that enable standardization of authentication environment architecture. Due to the complexity of the application specific integrated circuit (Application Specific Integrated Circuit, ASIC) verification work, it is particularly important that numerous verification engineers are involved together, a standardized and well organized verification script (Testbench structure).
The UVM has the idea and the function of object-oriented programming, integrates the advantages of a plurality of verification methodologies, can create a reusable, automatic, easy-to-maintain and interoperable test flow assembly, and improves the verification efficiency to the greatest extent.
The register conversion stage circuit (Register Transfer Level, RTL) verification platform based on UVM can run on a standard server, does not need to customize a specific server, and reduces verification cost investment; in the function verification of the module level, the compiling speed and the simulating speed of the logic simulation tool are very fast, so that the project unit test process is effectively promoted; the verification engineer can well control the logic simulation process, pause or interrupt the operation of the logic simulation tool at any time, and can also use a user-friendly graphical user interface (Graphical User Interface, GUI) mode for verification, so that the debugging efficiency is improved, and the GUI is also called as a graphical user interface; random constraint excitation can be generated, automatic comparison of results and coverage rate statistical analysis are completed, the coverage rate is utilized to drive verification work, completeness of the verification work is guaranteed, and the verification work plays a significant role in the whole ASIC chip development process.
The RTL verification platform based on UVM is a software simulation platform, the Testbench and the DUT are both operated in simulation software, and the algorithm mechanism of the mainstream simulation software is mostly event-based, so that the RTL verification platform based on UVM is more suitable for processing discrete time, state and variable. The simulator firstly builds an event queue when compiling the data structure, the simulation starts from time 0, and after all event queues of time 0 are processed, the simulator can enter the next time period, if the design file is large, the simulation speed becomes slow, and the verification efficiency is greatly reduced.
However, with the increasingly miniaturized process nodes of ASIC using complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), and the increasingly complex technology, the larger the design volume. The logic-based simulation tool is very frustrating for ASIC verification for very often millions of gates.
Fig. 1 is a flowchart of a simulation verification method provided by an embodiment of the present invention, as shown in fig. 1, where the simulation verification method is applied to a simulation verification platform provided with an external hardware accelerator, and includes:
s10: constructing and calling a verification script;
according to the basic class of each verification component provided by UVM, constructing a Testbench, wherein the Testbench does not contain a tested object;
s11: loading a tested object by using a hardware accelerator;
the method comprises the steps of transplanting a tested object to a hardware accelerator, and developing a matched clock generation module, a receiving end control logic, a transmitting end control logic and a related communication interface module; at this time, a data interface passage between the simulation verification platform and the hardware accelerator is opened;
s12: performing hardware interface driving test according to simulation verification data of the verification script and outputting a simulation verification result;
the hardware interface driving test is used for driving a hardware interface of a hardware accelerator for testing the tested object;
s13: and finishing simulation verification according to the simulation verification result.
Since the hardware interface for calling the hardware accelerator is used, the need for additional steps or processes to drive the hardware interface is avoided, thereby improving the simulation verification rate. In addition, simulation acceleration is carried out through the hardware accelerator, so that the verification efficiency of the ASIC is greatly improved, and the development period of products is shortened. Another important role is to provide an early and realistic hardware environment for the firmware and software of the entire system, and to perform overall performance evaluation and bottleneck analysis on the system before streaming.
Fig. 2 is a block diagram of a first simulation verification platform provided by an embodiment of the present invention, where, as shown in fig. 2, the simulation verification platform at least includes an input end and an output end, where the input end includes at least a sequencer, a driver, and a display, and the output end includes at least a display, and in addition, a reference model and a score board are further disposed in the simulation verification platform, and meanwhile, the simulation verification platform is applied to a tested object. In addition, fig. 3 is a block diagram of a second simulation verification platform provided by the embodiment of the present invention, as shown in fig. 3, the simulation verification platform is disposed at a server, and a hardware interface driving module is used for performing a hardware interface driving test, and the hardware interface driving module is at least further used for performing functions of parameter analysis, framing, instruction generation, result reporting, frame de-framing, instruction analysis, etc., where the hardware interface driving module is used for driving a hardware interface, and a hardware accelerator needs to be applied to a tested object according to a receiving end control logic, a clock generation module, and a transmitting end control logic.
On the basis of the above embodiment, as a more preferable embodiment, transmitting the simulation verification data to the hardware interface driver module according to the verification script includes:
generating an excitation sequence according to constraint conditions in the verification script;
framing the excitation sequence to obtain a framed excitation sequence;
and transmitting the framing excitation sequence to perform hardware interface driving test.
For some characteristic specifications, when all excitation attributes are random attributes, it is difficult to randomly cover boundary scenes in a short time, and some constraint conditions, such as upper and lower limits, condition values, weights, data distribution rules and the like, need to be set before random.
After the hardware interface driving test is performed by transmitting the framing excitation sequence, the method further comprises the following steps:
carrying out frame de-framing on the framing excitation sequence to obtain a de-framing excitation sequence after frame de-framing;
transmitting the de-framing excitation sequence to the tested object according to a preset time sequence.
In addition, after outputting the simulation verification result, before completing the simulation verification according to the simulation verification result, the method further comprises:
receiving a simulation verification result output by a hardware accelerator; the simulation verification result is obtained after framing and de-framing are sequentially carried out.
The hardware accelerator transmitting end control logic is used for monitoring and sampling the tested object, obtaining data such as simulation verification results, coverage rate statistics analysis reports and the like, finishing framing, and transmitting the data to the simulation verification platform through the hardware interface.
Meanwhile, completing the simulation verification according to the simulation verification result comprises the following steps:
sampling a simulation verification result and obtaining a reference verification result by using a reference model in a simulation verification platform;
judging whether the simulation verification result is consistent with the reference verification result;
if yes, recording a simulation verification result; if not, ending.
Monitoring the simulation verification result of the output of the tested object transmitted by the hardware accelerator through the display, sampling and transmitting to the score board; meanwhile, the output result of the reference model is monitored and sampled and is sent to a score board; the score board judges the correctness of the tested object by comparing whether the reference model is consistent with the simulation verification result of the output of the tested object, and records the simulation verification result. The tested object can be a design function to be tested.
It can be understood that after recording the simulation verification result, the method further comprises:
and carrying out coverage rate statistical analysis according to the simulation verification result, and outputting a coverage rate statistical analysis report.
Finally, after outputting the coverage rate statistical analysis report, the method further comprises:
constructing an operation script, wherein the operation script is used for managing a test database;
and expanding the test database on the condition of coverage rate statistical analysis report.
Automatically completing code coverage rate statistical analysis through a UVM self-contained analysis tool, and outputting a coverage rate statistical analysis report; the automatic operation script is developed by using a computer programming language Python, so that the management of the test database and the automatic execution of the test database are mainly completed, the execution condition of the test database is recorded, and the problem tracking and positioning are facilitated; and the coverage rate statistical analysis report is used as a drive, a test database is expanded in a targeted manner, and the code coverage rate of the tested object is further improved.
The invention combines the traditional logic simulation of software operation with the hardware simulation acceleration technology, greatly improves the simulation speed through the hardware accelerator, improves the verification efficiency of the ASIC and shortens the development period of the product; meanwhile, an early and real hardware environment is provided for the firmware and the software of the whole system, the front-end development of the software and the verification of the system are powerfully supported, and the whole performance evaluation and bottleneck analysis are carried out on the system before streaming; in addition, a special hardware interface driving module is designed by taking a general high-speed interface of a server side such as Ethernet, PCIe and the like as a carrier, so that the software and hardware collaborative acceleration is realized, and the functions of parameter analysis, framing, instruction generation, instruction analysis, frame decomposition, result reporting and the like between a verification platform and a hardware accelerator are mainly completed.
In the above embodiments, the detailed description is given to the simulation verification method, and the invention also provides a corresponding embodiment of the simulation verification device. It should be noted that the present invention describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Fig. 4 is a structural diagram of a simulation verification device provided by an embodiment of the present invention, and as shown in fig. 4, the present invention further provides a simulation verification device, including:
a first construction module 40 for constructing and invoking a verification script;
according to the basic class of each verification component provided by UVM, constructing a Testbench, wherein the Testbench does not contain a tested object;
a loading module 41, configured to load the object to be tested by using a hardware accelerator;
the method comprises the steps of transplanting a tested object to a hardware accelerator, and developing a matched clock generation module, a receiving end control logic, a transmitting end control logic and a related communication interface module; at this time, a data interface passage between the simulation verification platform and the hardware accelerator is opened;
the first transmission module 42 is configured to perform a hardware interface driving test according to the simulation verification data of the verification script, and output a simulation verification result, where the hardware interface driving test is used to drive a hardware interface of a hardware accelerator for testing the tested object;
the hardware interface driving module is used for driving a hardware interface of a hardware accelerator for testing the tested object;
and the simulation verification module 43 is used for completing simulation verification according to the simulation verification result.
Since the hardware interface for calling the hardware accelerator is used, the need for additional steps or processes to drive the hardware interface is avoided, thereby improving the simulation verification rate. In addition, simulation acceleration is carried out through the hardware accelerator, so that the verification efficiency of the ASIC is greatly improved, and the development period of products is shortened. Another important role is to provide an early and realistic hardware environment for the firmware and software of the entire system, and to perform overall performance evaluation and bottleneck analysis on the system before streaming.
Furthermore, the device comprises the following modules:
in some embodiments, performing the hardware interface driver test in accordance with simulated verification data of the verification script includes:
the generation module is used for generating an excitation sequence according to the constraint conditions in the verification script;
the framing module is used for framing the excitation sequence to obtain a framed excitation sequence;
and the second transmission module is used for transmitting the framing excitation sequence to carry out hardware interface drive test.
For some characteristic specifications, when all excitation attributes are random attributes, it is difficult to randomly cover boundary scenes in a short time, and some constraint conditions, such as upper and lower limits, condition values, weights, data distribution rules and the like, need to be set before random.
In some embodiments, after transmitting the framing excitation sequence to the hardware interface driver module, further comprising:
the frame-decoding module is used for carrying out frame decoding on the framing excitation sequence to obtain a frame-decoded excitation sequence;
and the third transmission module is used for transmitting the de-framing excitation sequence to the tested object according to a preset time sequence.
In some embodiments, after outputting the simulation verification result, before completing the simulation verification according to the simulation verification result, further comprising:
the receiving module is used for receiving the simulation verification result output by the hardware accelerator; the simulation verification result is obtained after framing and de-framing are sequentially carried out.
The hardware accelerator transmitting end control logic is used for monitoring and sampling the tested object, obtaining data such as simulation verification results, coverage rate statistics analysis reports and the like, finishing framing, and transmitting the data to the simulation verification platform through the hardware interface.
In some embodiments, completing the simulation verification based on the simulation verification result includes:
the sampling module is used for sampling a simulation verification result and obtaining a reference verification result by using a reference model in the simulation verification platform;
the judging module is used for judging whether the simulation verification result is consistent with the reference verification result;
if yes, triggering a recording module for recording a simulation verification result; if not, ending.
Monitoring the simulation verification result of the output of the tested object transmitted by the hardware accelerator through the display, sampling and transmitting to the score board; meanwhile, the output result of the reference model is monitored and sampled and is sent to a score board; the score board judges the correctness of the tested object by comparing whether the reference model is consistent with the simulation verification result of the output of the tested object, and records the simulation verification result. The tested object can be a design function to be tested.
In some embodiments, after recording the simulation verification result, further comprising:
and the coverage rate statistical analysis module is used for carrying out coverage rate statistical analysis according to the simulation verification result and outputting a coverage rate statistical analysis report.
In some embodiments, after outputting the coverage statistics analysis report, further comprising:
the second construction module is used for constructing an operation script which is used for managing the test database;
and the expansion module is used for expanding the test database under the condition of the coverage rate statistical analysis report.
Automatically completing code coverage rate statistical analysis through a UVM self-contained analysis tool, and outputting a coverage rate statistical analysis report; the automatic operation script is developed by using a computer programming language Python, so that the management of the test database and the automatic execution of the test database are mainly completed, the execution condition of the test database is recorded, and the problem tracking and positioning are facilitated; and the coverage rate statistical analysis report is used as a drive, a test database is expanded in a targeted manner, and the code coverage rate of the tested object is further improved.
The invention combines the traditional logic simulation of software operation with the hardware simulation acceleration technology, greatly improves the simulation speed through the hardware accelerator, improves the verification efficiency of the ASIC and shortens the development period of the product; meanwhile, an early and real hardware environment is provided for the firmware and the software of the whole system, the front-end development of the software and the verification of the system are powerfully supported, and the whole performance evaluation and bottleneck analysis are carried out on the system before streaming; in addition, a special hardware interface driving module is designed by taking a general high-speed interface of a server side such as Ethernet, PCIe and the like as a carrier, so that the software and hardware collaborative acceleration is realized, and the functions of parameter analysis, framing, instruction generation, instruction analysis, frame decomposition, result reporting and the like between a verification platform and a hardware accelerator are mainly completed.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
Fig. 5 is a structural diagram of a simulation verification device provided by an embodiment of the present invention, where, as shown in fig. 5, the simulation verification device includes:
a memory 50 for storing a computer program;
a processor 51 for implementing the steps of the simulation verification method as mentioned in the above embodiments when executing a computer program.
The simulation verification device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 51 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 51 may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 51 may also include a main processor, which is a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 51 may be integrated with an image processor (Graphics Processing Unit, GPU) for taking care of rendering and rendering of the content that the display screen is required to display. In some embodiments, the processor 51 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.
Memory 50 may include one or more computer-readable storage media, which may be non-transitory. Memory 50 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 50 is at least used for storing a computer program, which, when loaded and executed by the processor 51, is capable of implementing the relevant steps of the simulation verification method disclosed in any one of the foregoing embodiments. In addition, the resources stored in the memory 50 may also include an operating system, data, etc., and the storage manner may be transient storage or permanent storage. The operating system may include Windows, unix, linux, among others. The data may include, but is not limited to, simulated verification methods, and the like.
In some embodiments, the simulation verification device can further comprise a display screen, an input-output interface, a communication interface, a power supply and a communication bus.
Those skilled in the art will appreciate that the structure shown in FIG. 5 is not limiting of the simulated verification device and may include more or fewer components than illustrated.
The simulation verification device provided by the embodiment of the invention comprises the memory 50 and the processor 51, wherein the processor 51 can realize a simulation verification method when executing a program stored in the memory 50.
Finally, the invention also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The simulation verification method, the simulation verification device, the simulation verification equipment and the simulation verification medium provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. The simulation verification method is characterized by being applied to a simulation verification platform provided with an external hardware accelerator, and comprising the following steps of:
constructing and calling a verification script;
loading a tested object by using a hardware accelerator;
performing a hardware interface driving test according to the simulation verification data of the verification script and outputting a simulation verification result, wherein the hardware interface driving test is used for driving and testing a hardware interface of the hardware accelerator of the tested object;
and finishing simulation verification according to the simulation verification result.
2. The emulation verification method of claim 1 wherein the performing a hardware interface driver test in accordance with emulation verification data of the verification script comprises:
generating an excitation sequence according to constraint conditions in the verification script;
framing the excitation sequence to obtain a framed excitation sequence;
and transmitting the framing excitation sequence to perform hardware interface driving test.
3. The emulation verification method of claim 2, further comprising, after the transmitting the framing excitation sequence for hardware interface driver testing:
the framing excitation sequence is subjected to frame de-framing to obtain a de-framing excitation sequence after frame de-framing;
and transmitting the de-framing excitation sequence to the tested object according to a preset time sequence.
4. The simulation verification method according to claim 1, further comprising, after the outputting of the simulation verification result, before the completion of the simulation verification according to the simulation verification result:
receiving the simulation verification result output by the hardware accelerator; the simulation verification result is obtained after framing and de-framing are sequentially carried out.
5. The simulation verification method according to claim 4, wherein the completing the simulation verification according to the simulation verification result comprises:
sampling the simulation verification result and obtaining a reference verification result by using a reference model in a simulation verification platform;
judging whether the simulation verification result is consistent with the reference verification result;
if yes, recording the simulation verification result;
if not, ending.
6. The simulation verification method according to claim 5, further comprising, after the recording of the simulation verification result:
and carrying out coverage rate statistical analysis according to the simulation verification result, and outputting a coverage rate statistical analysis report.
7. The simulation verification method according to claim 6, further comprising, after the output coverage statistical analysis report:
constructing an operation script, wherein the operation script is used for managing a test database;
and expanding the test database on the condition of the coverage rate statistical analysis report.
8. The simulation verification device is characterized by being applied to a simulation verification platform provided with an external hardware accelerator, and comprises:
the first construction module is used for constructing and calling a verification script;
the loading module is used for loading the tested object by utilizing the hardware accelerator;
the first transmission module is used for carrying out hardware interface driving test according to the simulation verification data of the verification script and outputting a simulation verification result, wherein the hardware interface driving test is used for driving and testing a hardware interface of the hardware accelerator of the tested object;
and the simulation verification module is used for completing simulation verification according to the simulation verification result.
9. A simulation verification apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the simulation verification step of any one of claims 1 to 7 when executing said computer program.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the emulation verification step of any one of claims 1 to 7.
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| CN202310901550.XA CN116956790A (en) | 2023-07-21 | 2023-07-21 | Simulation verification method, device, equipment and medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117313649A (en) * | 2023-11-28 | 2023-12-29 | 苏州元脑智能科技有限公司 | Chip simulation verification method and application device thereof |
| CN117313650A (en) * | 2023-11-28 | 2023-12-29 | 苏州元脑智能科技有限公司 | Chip test verification method and application device thereof |
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2023
- 2023-07-21 CN CN202310901550.XA patent/CN116956790A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117313649A (en) * | 2023-11-28 | 2023-12-29 | 苏州元脑智能科技有限公司 | Chip simulation verification method and application device thereof |
| CN117313650A (en) * | 2023-11-28 | 2023-12-29 | 苏州元脑智能科技有限公司 | Chip test verification method and application device thereof |
| CN117313649B (en) * | 2023-11-28 | 2024-02-27 | 苏州元脑智能科技有限公司 | Chip simulation verification method and application device thereof |
| CN117313650B (en) * | 2023-11-28 | 2024-03-01 | 苏州元脑智能科技有限公司 | Chip test verification method and application device thereof |
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