CN102778645B - JTAG (joint test action group) main controller and realization method of JTAG main controller - Google Patents
JTAG (joint test action group) main controller and realization method of JTAG main controller Download PDFInfo
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Abstract
The invention relates to a JTAG (joint test action group) main controller and a realization method of the JTAG main controller. The JTAG main controller comprises a JTAG signal generator. The JTAG signal generator obtains external HOST instructions, in addition, the HOST instructions are analyzed to obtain IR (instruction register) instructions or DR (data register) data, so corresponding JTAG interface signals are generated according to IR instructions or DR data, and a target chip is driven through the JTAG interface signals. The JTAG main controller and the realization method have high execution instruction efficiency, and can be applied into a JTAG device.
Description
Technical field
The present invention relates to electronic applications, relate in particular to JTAG device.
Background technology
Jtag interface is as a kind of interface standard of IEEE, plays an important role at aspects such as the test of integrated circuit, emulation, debugging.Existing most high-grade device is all supported JTAG agreement, as the device such as DSP, FPGA.
The jtag interface of standard comprises test clock input signal TCK, input signal of test data TDI, test mode select signal TMS, test data output port TDO and an optional test reset input signal TRST.
JTAG device inside logic realizes by a TAP state machine, and Fig. 1 shows the state transitions schematic diagram of the TAP state machine of the JTAG device that IEEE1149.1 standard specifies.As shown in Figure 1, TAP state machine comprises Liang Ge branch, is respectively command register access (IR Access) branch and data register access (DR Access) branch.And the state transitions of this TAP state machine is controlled by the test mode select signal in JTAG device (TMS).
IEEE1149.1 standard has specified command register (IR) and the data register (DR) of JTAG device, according to this regulation, at the state of TAP state machine during in IR access tributary, order moves on in IR register under " displacement IR " state by turn by TDI port, IR register is for selecting when TAP state machine is during in DR access tributary, be connected between TDI and TDO by the selected DR register of IR register, and under " displacement DR " state, data are shifted and are entered by the selected register of IR register by TDI.
When Fig. 2 and Fig. 3 show respectively the access command register of JTAG and data register, the sequential chart of jtag interface signal.Fig. 2 completes 4-bit command register by jtag interface in prior art to access the JTAG signal timing diagram producing.Fig. 3 completes 8-bit data register by jtag interface in prior art to access the JTAG signal timing diagram producing.
Traditional JTAG primary controller is all to utilize the processor such as MIPS, ARM to realize, the function of carrying out due to MIPS, ARM system is realized by software, and what adopt is that the instruction of MIPS, ARM self completes specific function, a jtag instruction need to use multiple MIPS instruction simulations, and because completing by scheduling of task in MIPS, ARM system completes, therefore cause its JTAG signal producing (being the signals such as TCK, TMS, TDI) irregular, and the delay between two instructions is larger, this test for chip and unfavorable.Especially in the time that jtag interface control circuit is carried out to performance test, cannot produce the test clock of high frequency by MIPS, arm processor, impact test effect.The problems referred to above are determined by the system such as MIPS, ARM own characteristic.
Summary of the invention
The invention provides a kind of JTAG master controller and its implementation that can overcome the above problems.
In first aspect, the invention provides a kind of JTAG master controller being connected with objective chip.This JTAG master controller comprises JTAG signal generator.This JTAG signal generator is for obtaining outside HOST instruction, and this HOST instruction is resolved to obtain IR instruction or DR data, thereby produce corresponding jtag interface signal according to this IR instruction or DR data, to drive this objective chip by this jtag interface signal.
In second aspect, the invention provides a kind of implementation method of JTAG master controller.First the method obtains HOST instruction, then this HOST instruction is resolved, to obtain IR instruction or DR data.Produce corresponding jtag interface signal according to this IR instruction and/or DR data again.Finally objective chip is tested or emulation or debugging by described jtag interface signal.
JTAG master controller of the present invention no longer adopts the processor such as MIPS, ARM, but realizes by hardware architecture mode.The JTAG master controller of this kind of structure, its inside function completes by hardware mode, therefore it can make the sent signal period isometric, continuous, and between different instruction, postpone little, thereby can complete accurate test, emulation or the debugging to objective chip.
Brief description of the drawings
Below with reference to accompanying drawings specific embodiment of the invention scheme is described in detail, in the accompanying drawings:
Fig. 1 is the state transitions schematic diagram of the TAP state machine of the JTAG device that specifies of IEEE 1149.1 standards;
Fig. 2 completes 4-bit command register by jtag interface in prior art to access the jtag interface sequential chart producing;
Fig. 3 completes 8-bit data register by jtag interface in prior art to access the JTAG signal timing diagram producing;
Fig. 4 is the JTAG master controller principle of work schematic diagram of one embodiment of the invention;
Fig. 5 is the JTAG signal generator inner structure schematic diagram of one embodiment of the invention;
Fig. 6 is the state machine diagram of the HOST instruction parser of one embodiment of the invention.
Embodiment
Fig. 4 is the JTAG master controller principle of work schematic diagram of one embodiment of the invention.
This JTAG master controller comprises outside NVM410, memory control module 420, clock module 430, embedded memory 440, JTAG signal generator 450; Wherein, memory control module 420, clock module 430, embedded memory 440, JTAG signal generator 450 are integrated on a chip, as FPGA or asic chip.
In the time of this JTAG master controller work, it need to be connected with objective chip 460 by JTAG signal generator 450, to realize the operation such as test or debugging or emulation to objective chip 460.The jtag interface that this objective chip 460 comprises standard, it meets IEEE1149.1 standard.
In Fig. 4, outside NVM 410 is for storing from the HOST instruction of main frame 470.This outside NVM 410 can be any one existing nonvolatile memory, as it is EEPROM (EEPROM (Electrically Erasable Programmable Read Only Memo)).
This memory control module 420 is for storing the HOST instruction sending over from main frame 470 into this outside NVM 410, and for the HOST instruction of outside NVM 410 is transported in embedded memory 440.
This embedded memory 440 is for the temporary HOST instruction from main frame 470 or outside NVM 410.
It should be noted that, in the time that this JTAG master controller is used for the first time, this JTAG master controller need to be connected with main frame 470 by its memory control module 420, so that this JTAG master controller is stored to the HOST instruction from external host 470 in the NVM410 of this outside by this memory control module 420.Because this outside NVM 410 is nonvolatile memories, the HOST instruction of its storage inside is difficult for losing, therefore in the time that this JTAG master controller is used again, without being connected on this main frame 470, this JTAG master controller can directly be tested or debugging or emulation etc. objective chip.
This clock module 430 is connected with memory control module 420, JTAG signal generator 450, and it moves needed clock for generation of circuit, and this clock module 430 provides tck signal to the TCK interface of this JTAG master controller.
In an example, this clock module 430 is to be realized by the PLL module of programmable logic device (PLD), carrys out clocking by the PLL module of programmable logic device (PLD).Because this PLL module can produce high frequency clock signal, therefore the present invention can produce the test clock of high frequency.And the system such as MIPS, ARM that prior art adopts is due to its build-in attribute, cannot produce high-frequency test clock.
This JTAG signal generator 450 is for reading the HOST instruction of embedded memory 440, and this HOST instruction is resolved, to obtain corresponding IR instruction length, DR data length, IR instruction, DR data, and according to this IR instruction length, DR data length, IR instruction, DR data and produce corresponding jtag interface signal by TAP state machine (the TAP state machine in Fig. 1), thereby realize test or debugging or the emulation etc. to objective chip 460 according to this jtag interface signal.Wherein, HOST instruction is the custom instruction of the present embodiment, its definition rule will be described in detail in following content, and IR instruction, DR data are to be defined according to IEEE1149.1 prescribed by standard by objective chip deviser, and therefore objective chip 460 can be identified this IR instruction and DR data.
To set forth the principle of work of JTAG signal generator 450 by Fig. 5 and respective description part thereof below.
Fig. 5 is the JTAG signal generator inner structure schematic diagram of one embodiment of the invention.This JTAG signal generator comprises storer Read Controller 510, HOST instruction parser 520, IR instruction length register 530, DR data length register 540, IR order register 550, DR data register 560, jtag interface logic 570.
In Fig. 5, HOST instruction parser 520 is for resolving the HOST instruction from embedded memory 440.This HOST order format is: Header+Data; Wherein, Header obtains the HOST instruction of IR instruction after representing to resolve, and obtains the HOST instruction of DR data after Data represents to resolve.As can be seen here, JTAG signal generator 450 to HOST instruction resolve, can first obtain IR instruction and obtain again DR data.
In an example, Header length is 32 bits, will set forth as 32 bits as example taking Header length below.
Table 1 is that length is the form of the Header of 32 bits.
Table 1
Table 1 is at Header[31:29] meet respectively in 000,001,010,011 situation Header[28:0] implication that referred to respectively.Now with way of example, above-mentioned table 1 is further elaborated.When the instruction receiving when HOST instruction parser 520 is Header=32 ' h0000_0010, it is by Header[28:0] corresponding contents writes IR instruction length register, and the value of writing is 16.When the instruction receiving when HOST instruction parser 520 is Header=32 ' h2000_00FF, it is by Header[28:0] corresponding contents writes DR data length register, and the value of writing is 255, and according to the line number (have below and set forth how obtaining this line number) of this DR data length value calculating DR data.When the instruction receiving when HOST instruction parser 520 is Header=32 ' h4000_3FAF, it is by Header[28:0] corresponding contents writes IR register, and the value of writing is 29 ' h0000_3FAF.In the time of instruction Header=32 ' h6000_0000 that HOST instruction parser 520 receives, HOST instruction parser and storer Read Controller quit work.
These HOST instruction parser 520 inside comprise a counter, and this counter is for counting the line number that DR data read.
This HOST instruction parser 520 also relates to a state machine, and referring to Fig. 6, Fig. 6 is the state machine diagram of the HOST instruction parser of one embodiment of the invention.
In Fig. 6, when system reset, state machine is in Header state (command status); Under Header state, as Header[31:29] when==3 ' b010 (representing that present instruction is for sending IR instruction), and while parsing the non-zero value of DR data length, state machine is transferred to Data state, and the value of counter in HOST instruction parser 520 is set to DR number of data lines+1, to go counting to parsing DR data; Under Data state (data mode), the counter of HOST instruction parser 520 starts to subtract counting, often reads data in a line storage, and this Counter Value subtracts 1, until this Counter Value reduces to 0, now this state machine is transferred to Header state again.
The method that HOST instruction parser obtains DR number of data lines is: in the time that instruction Header meets 3 ' b010, by Header[29:0] divided by 32, the numerical value obtaining is the total line number of DR data.Therefore, counter need to be from Header[29:5]+1 start counting, be read line number to record DR data.
Table 2 is examples storing content format in outside NVM 410 and embedded memory 440.
Table 2
Taking table 2 as example, elaborate the principle of work of HOST instruction parser below.
Instruction 32 ' the h0000_0010 of this HOST instruction parser 520 from table 2 starts to resolve, known according to table 1, and this instruction 32 ' h0000_0010 can be resolved out " IR instruction length is 16 ".
This HOST instruction parser 520 continues the instruction 32 ' h2000_00FF in resolution table 2, this instruction 32 ' h2000_00FF can be resolved out " DR data length is 255 ", because every row DR data are 32 bits, therefore can further parse totally 8 row DR data, thereby the initial value of counter is 8+1=9.Because above-mentioned instruction 32 ' h0000_0010 and 32 ' h2000_00FF all do not meet the jump condition of the Header state of Fig. 6 state machine, all do not meet Header[32:29]==3 ' b010, and DR length is non-zero, therefore, and now still in Header state.
This HOST instruction parser 520 continues the instruction 32 ' h4000_3FAF in resolution table 2, and this instruction 32 ' h4000_3FAF can be resolved out " sending IR instruction 3FAF ".Due to this instruction, 32 ' h4000_3FAF meets Header[32:29]==3 ' b010, and DR data length is non-zero.Therefore, now from Header state transitions to Data state.
This HOST instruction parser 520 continues the instruction 32 ' h1234_5678 in resolution table 2, owing to now having transferred to Data state, therefore now sends data 1234_5678......; By that analogy, until the value of counter is 0,8 row DR data have now been sent.
It should be noted that, this instruction 32 ' h4000_3FAF (being stored in the instruction 32 ' h4000_3FAF in outside NVM 410 and embedded memory 440) is only an example, that is to say, sending IR instruction 3FAF is only an example.In fact, specifically sending which type of IR instruction need to set according to the configuration of objective chip, and the IR instruction sending has many conventionally, and is not limited to 32 ' h4000_3FAF instruction in table 2.Equally, instruction 32 ' h1234_5678 is only also an example, specifically sends which type of DR data, and to send how many DR data be also to set according to the configuration of objective chip.
Above-mentioned table 2 and respective description part are the elaborations that the principle of work of HOST instruction parser 520 is carried out, the storer Read Controller 510 in the Fig. 5 of continuation description below and the principle of work of jtag interface logic 570.
This storer Read Controller 510, after receiving test beginning indicator signal (this signal can produce by button), reads the first row content in embedded memory 440, and is sent to HOST instruction parser 520.This HOST instruction parser 520 is resolved this instruction, and concrete analytic method, referring to table 2, Fig. 6 and respective description part thereof, is being resolved after this instruction, and these HOST instruction parser 520 these storer Read Controllers 510 of instruction read next line data.The like, until this storer Read Controller 510 reads instruction Header==32 ' h6000_0000, and after this HOST instruction parser 520 has been resolved this instruction, this HOST instruction parser 520 and this storer Read Controller 510 quit work.
(this HOST instruction parser 520 is after sending to IR order register or DR data register by the information parsing after the register effective index signal that this HOST instruction parser 520 sends being detected for this jtag interface logic 570, capital sends a register effective index signal to this jtag interface logic), obtain the value in the value in value or the DR data length register in IR instruction length register or value or the DR data register in IR order register, and according to the value of this acquisition, according to TAP state machine and Fig. 2 in Fig. 1, jtag interface sequential chart shown in Fig. 3, drive the jtag interface of objective chip.
Particularly, the value of IR order register is exported from TDI interface under " displacement IR " state at Fig. 1 state machine, and the transfer of the each state of IR is decided by the value in IR instruction length register; The value of DR data register is exported from TDI interface under " displacement DR " state at Fig. 1 state machine, and the transfer of the each state of DR is decided by the value in DR data length register.And the output of TCK interface in Fig. 5 is from the clock signal of clock module 430, the output of TMS interface comes from the control signal that Fig. 1 state machine shifts.
Obviously, do not departing under the prerequisite of true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, all changes that it will be apparent to those skilled in the art that, within all should being included in the scope that these claims contain.The present invention's scope required for protection is only limited by described claims.
Claims (14)
1. the JTAG master controller being connected with objective chip, is characterized in that, comprising:
JTAG signal generator, obtain outside HOST instruction, and this HOST instruction is resolved to obtain IR instruction or DR data, thus corresponding jtag interface signal produced according to this IR instruction or DR data, to drive this objective chip by this jtag interface signal;
Described JTAG signal generator comprises HOST instruction parser, and this HOST instruction parser is for resolving the HOST instruction from embedded memory;
Described HOST instruction parser also comprises a state machine, and this state machine comprises command status (Header) and data mode (Data state);
When system reset, this state machine is in command status (Header state); Meeting the instruction that parses for sending IR instruction, and when the non-zero condition of DR data length, this state machine is transferred to data mode (Data state) by command status (Header state).
2. a kind of JTAG master controller as claimed in claim 1, is characterized in that, comprises the embedded memory being connected with JTAG signal generator, temporary described HOST instruction.
3. a kind of JTAG master controller as claimed in claim 1, is characterized in that, comprises memory control module and external memory storage, for the HOST instruction from main frame is sent to this external memory storage and reads HOST instruction from this external memory storage.
4. a kind of JTAG master controller as claimed in claim 1, is characterized in that, this JTAG master controller also comprises clock module, and this clock module is for providing the tck signal of jtag interface signal.
5. a kind of JTAG master controller as claimed in claim 1, is characterized in that, the part of described HOST instruction definition IR instruction length, DR data length and send one or more in IR instruction.
6. a kind of JTAG master controller as claimed in claim 5, is characterized in that, another part of described HOST instruction represents IR instruction length, DR data length and send one or more in IR instruction.
7. a kind of JTAG master controller as claimed in claim 1, is characterized in that, described HOST instruction parser also comprises a counter, and this counter is for counting DR number of data lines;
At described state machine when data mode (Data state), the initial value of counter is set, and described HOST instruction parser often parses a line DR data, this Counter Value increasing or decreasing, until this Counter Value shows that DR Data Analysis is complete, this state machine is transferred to command status (Header state) by data mode (Data state).
8. a kind of JTAG master controller as claimed in claim 1, is characterized in that, described JTAG signal generator also comprises storer Read Controller; The HOST instruction of this storer Read Controller for reading described embedded memory, and at described HOST instruction parser, it is made after instruction, this storer Read Controller is by next HOST instruction of reading again in described embedded memory.
9. a kind of JTAG master controller as claimed in claim 1, is characterized in that, described JTAG signal generator also comprises IR instruction length register, IR order register, DR data register, DR data length register;
This IR instruction length register resolves for storing by described HOST instruction parser the IR instruction length value obtaining; This IR order register resolves for storing by described HOST instruction parser the IR instruction obtaining; This DR data register resolves for storing by described HOST instruction parser the DR data that obtain; This DR data length register resolves for storing by described HOST instruction parser the DR data length value obtaining.
10. a kind of JTAG master controller as claimed in claim 9, is characterized in that, described JTAG signal generator also comprises jtag interface logic; This jtag interface logic is for obtaining the value in value, the IR order register of described IR instruction length register, and obtain the value in described DR data length register, the value in DR data register, and according to this value getting, and drive objective chip by TAP state machine.
The implementation method of 11. 1 kinds of JTAG master controllers, is characterized in that, comprising:
Obtain HOST instruction;
This HOST instruction is resolved, to obtain IR instruction or DR data;
Produce corresponding jtag interface signal according to this IR instruction and/or DR data;
Objective chip is tested or emulation or debugging by described jtag interface signal;
This JTAG master controller also comprises the state machine that a command status (Header state) and data mode (Data state) shift mutually;
This HOST instruction is resolved, be included in this state machine and resolve and obtain IR instruction when the command status to obtain the step of IR instruction and/or DR data; Meeting the instruction that parses for sending IR instruction, and when the non-zero condition of DR data length, this state machine is transferred to data mode by command status; Under data mode, resolve and obtain DR data.
The implementation method of 12. a kind of JTAG master controllers as claimed in claim 11, is characterized in that, the part of described HOST instruction definition IR instruction length, DR data length and send one or more in IR instruction; The corresponding expression of another part IR instruction length of described HOST instruction, DR data length and send one or more in IR instruction.
The implementation method of 13. a kind of JTAG master controllers as claimed in claim 12, is characterized in that, another part of described HOST instruction represents IR instruction length, DR data length and send one or more in IR instruction.
The implementation method of 14. a kind of JTAG master controllers as claimed in claim 11, it is characterized in that, this JTAG master controller comprises counter, this HOST instruction is resolved, comprise with the step that obtains IR instruction and/or DR data, this JTAG master controller often parses a line DR data, Counter Value increasing or decreasing, when this Counter Value shows that DR Data Analysis is complete, this state machine is transferred to command status by data mode.
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| CN108107351A (en) * | 2017-12-06 | 2018-06-01 | 西安智多晶微电子有限公司 | Adjustment method, debugger and the system of JTAG debuggers |
| CN112596434B (en) * | 2020-12-07 | 2022-11-04 | 天津津航计算技术研究所 | CPLD pin logic state monitoring method |
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| CN1222909C (en) * | 2002-05-30 | 2005-10-12 | 华为技术有限公司 | Loading method of Flash chip and JTAG controller |
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