CN1369714A - Boundary scan and test system for large-scale integrated circuit - Google Patents
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Abstract
The present invention belongs to test technical field of analog circuit in electronic line measurment relates to a boundary scan testing system for large scale integrated circuit, which is realized by two parts of software design and hardware circuit. The software part of system has the regulation similar to C language and complile program applies the design scheme specialy suitable to the object. Its features including one integrated development environmental IDE of chip test and programing realization of programmable analog chip ELEX 10k30. The present system in new design with convenient use has an advanced level as a whole comparing with domestic product.
Description
The invention belongs to logic circuit testing technical field in the electronic circuit measurement, relate to a kind of boundary scan and test system for large-scale integrated circuit, this system realizes by software design and hardware circuit two parts.
The testability problem that is intended to improve maintainability, reliability and productibility and proposes is along with the continuous rising of VLSI (very large scale integrated circuit) chip and printed board complicacy with to its shorter design cycle, more the Testability Design of system convention requires and produces.The company of various countries, the world today more and more clearly realizes that testability institute's role in product, and just pays attention to the test of product when product development.This be a difficulty big and be difficult for fine realization measuring technology, though because promoted the development of modern electronic technology when of the progress of header board level interconnection technique at aspects such as surface encapsulation and large scale integrated circuit IC door density, but the testability to system has very adverse influence, it is more and more difficult to adopt traditional physical means to visit circuit board, even may not.Therefore, no matter be military affairs or commercial field in electronic industry, for the serial test bus is set up a boundary-scan architecture and standard is approved widely.Boundary scan is exactly to introduce a boundary scan chain on the border in large scale integrated chip, the controllability and the observability of scanning are provided by scan operation, under the boundary scan testing state, test for internal logic is by applying test and excitation on the input port, and to obtain on the output port test response finishes, the test of adjacent IC during to chip chamber interconnection line and the assembling of plate level is by the test and excitation that applies on the output port, and the test response that obtains on the input port is finished.1986, JTAG JTAG (Joint Test Action Group) proposed a kind of boundary-scan architecture, so that support chip testing, PCB testing and the system diagnostics of all large scale integrated circuits.1988, IEEE and JTAG formulated the standard of P1149.1 boundary-scan architecture jointly.This standard code boundary-scan architecture one the cover standardized technique.Afterwards, existing many manufacturer production have an assembly of the boundary scan testing function of JTAG agreement defined.In the prior art before the present invention, we are by the retrieval of domestic patent and non-patent literature, 10 pieces of pertinent literatures (seeing search report) have been found altogether, pertinent literature biases toward the analysis of Boundary-scan test technology theory, the test macro function ratio of design is more single, does not see for the integration testing translation and compiling environment and addresses.The technology more close with the present invention is the boundary scan and test system of the large scale integrated circuit developed of nine institutes 771 of company of Aerospace Science and Technology Corporation, this model machine adopts single-chip microcomputer to form test macro, link to each other with PC by serial communication, under the DOS interface, carry out test operation, the difference on having levels with the present invention.In addition, understand, have the Related product of implementing the JTAG agreement to sell abroad, but not relevant therewith technology contents discloses according to us.
At above-mentioned prior art situation, the objective of the invention is to, a kind of boundary scan and test system of large scale integrated circuit is provided, this system is combined with probe station, can carry out middle survey to VLSI (very large scale integrated circuit) chip, combine with corresponding test card, can be carried out to survey, make the testability problem of large scale integrated circuit become simple, easy to use, cheap various large scale integrated chips.
Now design of the present invention and technical solution are described below:
Boundary scan and test system for large-scale integrated circuit of the present invention is made up of software and hardware two parts.
The software section of system has and is similar to the rule of writing general C language and realizes writing of source program, each process of program compiler adopts OO method to design, and it is characterized in that: comprise the Integrated Development Environment IDE of a chip testing and the realization of programmable logic chip FLEX10K30 programming.The Integrated Development Environment IDE of chip testing comprises following a few part:
1, the IDE software platform of chip testing has designed a kind of new JTAG Builder language, has simple syntax rule, data type has four kinds: Int, Hex, Bin, Str, and the rreturn value of function also has a kind of Void type except above four types; For language construction, realize the sequential organization statement, judge structured statement, loop statement; For action scope, each variable all has its action scope, comprises global variable and local variable.The user can equally realize writing of its test source program as the C language of writing according to the various rules or the grammer of this language.
2, this IDE can be compiled into the source program that the user writes according to its syntax rule the test target code, the generation of all object codes depends on the calling of system function WritToObj BINWENCHEN (strcode), and promptly this function writes character string code in the file destination.At last, can test and judged result chip, can select automatic test mode and manual test mode by this IDE.
3, as the part of IDE, collector all adopts OO method to design to each process lexical analysis of program compiler, syntax analysis, syntax and semantics analysis etc.Traditional Compilation Method has many defectives or weak point, has two problems usually as the lexical analysis process: the one, and buffer problems, the 2nd, leading search and backspace character problem; Syntax analysis has several basic problems such as the eliminating of grammatical bloopers, grammatical ambiguousness, grammatical left recusion; In traditional semantic processes, there are the consistency problem on the space and the handling problem of symbol table; Infinite loop in the grammatical analysis process with recall problem, shift-in/stipulations are conflicted and stipulations/stipulations conflict etc.In order to solve these problems in the classic method, Object-oriented Technique is adopted in program compiler design in this project, mainly carried out following design: the lexical analysis process, adopt the stream mechanism in the object-oriented method, designed the input subsystem of lexical analysis, and set up the class of lexical analyzer by the expression formula class libraries, and realized from the regular expression mode-conversion being the simple algorithm of the class the expression formula class libraries, solved buffer problems and leading search and backspace character problem with this.In the syntax analysis process, at first analyzed the relation of traditional syntax and object-oriented feature, OO grammatical notion has been proposed then,, solve left recursion problem, ambiguity problem and the backspace character problem in traditional syntax analysis and recall problem as special processing for list separator with this.Semantic analysis process is based on the object-oriented syntax, transform and realized the statement class libraries, each link (comprising the inspection of expression formula class, statement type inspection) at type checking designs, and carried out the transformation of Object-oriented Technique with regard to declarative statement (comprising the statement of variable and function) with using statement (comprising the use of variable and function) respectively, common sentence structure (comprising order, condition, circulation and return statement etc.) is carried out OO semantic analysis, also carried out specialized designs at action scope simultaneously.It is grammatical that the grammatical analysis process also is based on object-oriented, proposed OO syntax analyzer and realized that at its algorithm a difficult problem of also recovering in this traditional grammar analysis at mistake has been carried out specialized designs simultaneously.Equally, the transformation and the realization of Object-oriented Technique have also been carried out for processes such as generation of the code in the compilation process and optimizations.In a word, technique of compiling is to utilize the object-oriented treatment technology in the system, the various characteristics of whole compilation process has been carried out the realization of system, overcome the major defect of traditional Compilation Method, as do not utilize universalization, processing procedure loaded down with trivial details, be unfavorable for program expansion etc., can handle accordingly each basic sides such as use of the realization of function calls, various statements, various variable and constant at present.
4, utilize WinDriver on the Window98 platform, to realize the operation of PCI plug-in card and it has been carried out The visual design.Generally speaking, under the environment of Windows, all direct controls to hardware under user's attitude all are under an embargo, if think access hardware, must realize by device driver, device driver provides the software interface of the hardware that is connected to computing machine, and it is a trust part of operating system.User application is with a kind of mode access hardware of standard, and how needn't to consider control hardware, therefore as a physical hardware in the computing machine, boundary scan testing interface card in this project also must just can conduct interviews by a driver, but write driver is the process of a complexity, this project is in order to save time and energy, utilized WinDriver software guide to realize visit to border scan test interface card physical hardware in source program.This visit is the visit at the slave unit of PCI in fact, and the operation of pci bus is a loaded down with trivial details and not intelligible process, this project is in order to operate pci bus better, developed the visualization procedure of pci bus, by this program, can know clearly the various configurations of pci bus and the content in each register, and can carry out read-write operation to the expansion card on the pci bus like a cork.
5, the second portion of software section adopts AHDL (Altero Hardnase DeascriptionLanguage), and this language has the technology of the mixing translation of design of supporting layer aggregated(particle) structure and style graphic file, has simplified the design objective to JTAG.According to the IEEE1149.1 test protocol, we adopt the design proposal of memory interface, command set interpreter and protocol signal interface, command history is control, scanning, comparison, shielding, test pattern, transfer, conditional transfer, storage and nine orders of counting, realizes that with correspondingly register and address, program pointer register protocol signal produces logic; Make full use of Maxplus II development platform, FLEX10K30 is optimized configuration to programmable logic chip.
System hardware of the present invention partly is a jtag test card based on pci bus, it is characterized in that:
1, this test card is made up of four parts, i.e. pci interface, test code memory module, JTAG agreement generation module, measurand interface.The groundwork flow process of jtag test card is: host computer downloads to the code storage district by pci interface with test code, start the jtag test agreement then and produce part, this part is by reading the test code of storage, generate corresponding jtag test agreement, be test data input port TDI, test data output port TDO, test mode is selected TMS, test clock TCK, test signals such as test reset input TRST, end of test (EOT) stores test result in the result memory into, the final host computing machine is fetched test result by pci interface again, and judges the state of chip;
2, pci interface adopts the PLX9052 chip to carry out function to realize, promptly comes into contacts with by the bus of it and computing machine host, finishes loaded down with trivial details PCI operation of communicational interface reliably;
3, code storage partly adopts 4 memory chips to realize, test code and test result are for operation and judge use;
4, the jtag test agreement produces part and adopts programmable logic device (PLD) Flex10K30 realization, major function is to generate the test protocol interface according to the test code in the storage code district, by the measurand interface section tested chip is carried out the JTAG functional test; The measurand interface obtains its output and returns to the jtag test agreement producing part in order to handling in order to give measurand with the input of JTAG agreement.
Now that description of drawings of the present invention is as follows:
Fig. 1: the boundary scan and test system structured flowchart of large scale integrated circuit of the present invention
Fig. 2～Fig. 6: hardware design schematic diagram of the present invention, embodied the modular design method when hardware design.
Wherein:
Fig. 2 is PCI slot catenation principle figure, is the slot connection of standard, and it provides the communication port of tester;
Fig. 3 is the SRAM theory diagram, its main components and parts are 4 memory chips, they are connected on the local bus of PLX9052 chip, its function is that storage test code and test result are handled for host and main control chip, when promptly preparing to begin to test, start FPGA (Field Programmable Gate Array) main control chip FLEX10K30 by host, this main control chip reads the test code in the storage and deciphers accordingly, to generate the jtag test agreement, test interface is tested measurand again, and the result deposited in the storer, last, host reads back these test results and handles and display result.
Fig. 4 is test card and measurand catenation principle figure, and the jtag test agreement is provided
Fig. 5 is PLX9052 catenation principle figure.The operation of pci bus is a very loaded down with trivial details process, its agreement is difficult to be realized, and the PLX9052 chip is a special pci interface chip, and portion has realized the pci interface agreement within it, its local bus is just expanded in remaining work, realizes and outside being connected.In this schematic diagram, realized being connected between PLX9052 chip and pci interface, memory interface, the main control chip.
Fig. 6 is the pin configuration figure of FLEX10K30 chip.Utilize the boundary scan testing primary controller of AHDL language compilation promptly to be integrated in this chip.
The boundary scan and test system modern design of integrated circuit of the present invention and super large-scale integration, Easy to use, belong to domestic initiation, integral body reaches leading domestic level. For China relatively fall behind integrated The measuring technology of circuit and super large-scale integration has very important practical significance and popularization Using value. Like product with millions of dollars of the need of external import is compared, system of the present invention corresponding Product has the very high ratio of performance to price, is easy to promote the use of in each integrated circuit manufacturer of the whole nation.
Claims (3)
1, a kind of boundary scan and test system for large-scale integrated circuit is realized by software design and hardware circuit two parts; System software partly has and is similar to the rule of writing general C language and realizes writing of source program, each process of program compiler adopts OO method to design, and it is characterized in that: comprise the Integrated Development Environment IDE of a chip testing and the realization of programmable logic chip FLEX10K30 programming; The IDE of chip testing comprises following a few part:
(1) for the IDE software platform of chip testing has designed JTAG Builder language, its syntax rule has four kinds of data type: Int, Hex, Bin, Str, and the rreturn value of function also has a kind of Void type except above four types; For language construction, realize the sequential organization statement, judge structured statement, loop statement; For action scope, each variable all has its action scope, comprises global variable and local variable;
(2) this IDE source program that the user is write according to its syntax rule is compiled into the test target code, the generation of all object codes depends on the calling of system function WritToObj BINWENCHEN (strcode), and promptly this function writes character string code in the file destination; By this IDE chip is tested and judged result, can be selected automatic test mode and manual test mode.
(3) as the part of IDE, collector all adopts OO method to design to each process lexical analysis of program compiler, syntax analysis, syntax and semantics analysis etc.;
(4) utilize WinDriver on the Window98 platform, to realize the operation of PCI plug-in card and it is carried out The visual design, utilized WinDriver software guide in source program, to realize visit, developed the visualization procedure of pci bus border scan test interface card physical hardware;
The second portion of software section adopts AHDL (Altero Hardnase DeascriptionLanguage), and this language has the technology of the mixing translation of design of supporting layer aggregated(particle) structure and style graphic file, has simplified the design objective to JTAG.According to the IEEE1149.1 test protocol, we adopt the design proposal of memory interface, command set interpreter and protocol signal interface, command history is control, scanning, comparison, shielding, test pattern, transfer, conditional transfer, storage and nine orders of counting, realizes that with correspondingly register and address, program pointer register protocol signal produces logic; Make full use of Maxplus II development platform, FLEX10K30 is optimized configuration to programmable logic chip.
2, a kind of boundary scan and test system for large-scale integrated circuit according to claim 1, system software part is characterised in that: as a part of collector of IDE lexical analysis process to program compiler, adopt the stream mechanism in the object-oriented method, the input subsystem of design lexical analysis, and set up the class of lexical analyzer by the expression formula class libraries, and realize from the regular expression mode-conversion being the simple algorithm of the class the expression formula class libraries, with resolve buffer district problem and leading search and backspace character problem; The syntax analysis process proposes OO grammatical notion, for list separator as special processing, to solve left recursion problem, ambiguity problem and the backspace character problem in traditional syntax analysis and to recall problem; Semantic analysis process, based on the object-oriented syntax, transform and realize the statement class libraries, each link (comprising the inspection of expression formula class, statement type inspection) at type checking designs, and carry out the Object-oriented Technique transformation with regard to declarative statement (comprising the statement of variable and function) with using statement (comprising the use of variable and function) respectively, common sentence structure (comprising order, condition, circulation and return statement etc.) is carried out OO semantic analysis, carry out specialized designs at action scope; The grammatical analysis process proposes OO syntax analyzer and realizes its algorithm based on the object-oriented syntax; Recover to carry out specialized designs at mistake; The code of compilation process generate with optimizing process in carry out the transformation and the realization of Object-oriented Technique.
3, a kind of boundary scan and test system for large-scale integrated circuit according to claim 1, system hardware partly are a boundary scan testing interface card and test accessories based on pci bus, it is characterized in that:
(1) test card is made up of four parts, i.e. pci interface, test code storage, the generation of JTAG agreement, measurand interface;
(2) pci interface adopts the PLX9052 chip to carry out function to realize, promptly comes into contacts with by the pci bus of it and host computer, finishes loaded down with trivial details PCI operation of communicational interface reliably;
(3) code storage partly adopts 4 storage chips to realize, test code and test result are for operation and judge use;
(4) the jtag test agreement produces part and adopts programmable logic device (PLD) Flex10K30 realization, generates the test protocol interface according to the test code in the storage code district, by the measurand interface section tested chip is carried out the JTAG functional test; The measurand interface obtains its output and returns to the jtag test agreement producing part in order to handling in order to give measurand with the input of JTAG agreement.
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| CN1318976C (en) * | 2004-06-16 | 2007-05-30 | 华为技术有限公司 | Software detection method and system |
| CN101030160A (en) * | 2006-03-02 | 2007-09-05 | 鸿富锦精密工业（深圳）有限公司 | Tester and method for testing unified series interface command |
| CN100351638C (en) * | 2003-05-01 | 2007-11-28 | 中兴通讯股份有限公司 | Boundary scan testing device for integrated circuit |
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| CN100419447C (en) * | 2003-02-12 | 2008-09-17 | 夏普株式会社 | Boundary scan controller, semiconductor device, method for identifying semiconductor circuit chip of semiconductor device, and method for controlling semiconductor circuit chip of semiconductor device |
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| CN102778645A (en) * | 2011-05-09 | 2012-11-14 | 京微雅格（北京）科技有限公司 | JTAG (joint test action group) main controller and realization method of JTAG main controller |
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| CN100364010C (en) * | 2003-12-24 | 2008-01-23 | 华为技术有限公司 | A EEPROM on-board programming method |
| CN1318976C (en) * | 2004-06-16 | 2007-05-30 | 华为技术有限公司 | Software detection method and system |
| CN101031809B (en) * | 2004-07-28 | 2012-08-01 | Nxp股份有限公司 | Circuit interconnect testing arrangement and approach therefor |
| CN101030160B (en) * | 2006-03-02 | 2013-03-20 | 鸿富锦精密工业（深圳）有限公司 | Tester and method for testing unified series interface command |
| CN101030160A (en) * | 2006-03-02 | 2007-09-05 | 鸿富锦精密工业（深圳）有限公司 | Tester and method for testing unified series interface command |
| CN101515019B (en) * | 2009-03-17 | 2012-05-09 | Ut斯达康通讯有限公司 | Dynamic boundary scanning chain test method based on programmable devices |
| CN102486939A (en) * | 2010-12-06 | 2012-06-06 | 普天信息技术研究院有限公司 | Method and apparatus for testing joint test action group (JTAG) of memories |
| CN102486939B (en) * | 2010-12-06 | 2014-08-13 | 普天信息技术研究院有限公司 | Method and apparatus for testing joint test action group (JTAG) of memories |
| CN102778645A (en) * | 2011-05-09 | 2012-11-14 | 京微雅格（北京）科技有限公司 | JTAG (joint test action group) main controller and realization method of JTAG main controller |
| CN102902834A (en) * | 2011-07-29 | 2013-01-30 | 炬力集成电路设计有限公司 | Verification method and verification system of SOC (System on Chip) |
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| CN105067991A (en) * | 2015-08-10 | 2015-11-18 | 宁波华远电子科技有限公司 | Circuit board detection device and detection method |
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