CN102902834A - Verification method and verification system of SOC (System on Chip) - Google Patents
Verification method and verification system of SOC (System on Chip) Download PDFInfo
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- CN102902834A CN102902834A CN2011102172297A CN201110217229A CN102902834A CN 102902834 A CN102902834 A CN 102902834A CN 2011102172297 A CN2011102172297 A CN 2011102172297A CN 201110217229 A CN201110217229 A CN 201110217229A CN 102902834 A CN102902834 A CN 102902834A
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- G06F30/32—Circuit design at the digital level
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Abstract
The invention is suitable for the technical field of chips. The embodiment of the invention provides a verification method of SOC (System on Chip). The method comprises the following steps: loading a test program; calling a corresponding system function in a system interface function library according to the test program; generating a random affair according to the system function and a maintenance list corresponding to the system function; and verifying a chip to be tested according to the random affair. According to the verification method and the verification system of the SOC, the test program written by a software engineer can directly run on the existing verifying platform so as to realize co-verification of software and hardware; and simultaneously lower-layer information is packaged so that the verification system is convenient to use and easy for multiplexing.
Description
Technical field
The invention belongs to the chip technology field, relate in particular to a kind of verification method and system of SOC chip.
Background technology
After finishing, chip design needs to verify that the main task of checking is the correctness of checking design, determines whether chip meets all design specificationss.
Traditional verification method is direct vector test (direct vector test), directly vector test is a kind of signal level checking, directly on signal level, communicate with chip to be verified by the excitation of making fixed scene, come the function of proofing chip by value and the variation that checks the chip pin signal.This verification method requires to design in advance the operative scenario of chip, and the checking personnel directly process the very signal level information of low level.Adopt this verification method, identifier person's workload is very large, and some unexpected scenes, mistake process scene and can not consider one by one and authenticate to, and causes checking not comprehensive.When the chip more complicated, when scale is larger, directly the verification method of vector test is not verified ability substantially.Owing to be the checking of signal level, verification platform is directly relevant with the interface protocol of chip, and the verification platform reusability is very poor, and original verification platform cannot be reused substantially when chip was regenerated, and must again build new verification platform.
In order to overcome the shortcoming of traditional verification method, the development trend of chip checking is to improve abstraction hierarchy, carries out the checking of transaction-level.
Representational transaction-level (transaction level) verification method is verification method handbook (Verification Methodology Manual, VMM).The framework of VMM verification system retrains generator by the constraint condition in the checking personnel operative configuration device and produces the test affairs, and realized on-line automatic comparison by automatic comparer as shown in Figure 1.
After adopting the VMM verification method, can realize constrained random checking (constrained random verification), under the constraint condition of setting, carry out at random, to cover normal operation scene and unexpected operative scenario; Coverage rate drives checking (coverage driven verification), stops later on accidental validation when function coverage, code coverage reach desired value; Full-automatic relatively online, run into wrong automatic alarm and stop emulation, saving scene; Assertion-based verification (assertion based verification).
The VMM verification method has been realized the transformation of verification method from signal level to transaction-level, has made things convenient for the checking of data path type chip.But because the data interaction of VMM verification method and control more complicated, concerning multimedia chip, operate the method very complex of chip to be verified, be inconvenient to control simulation flow, ease for use is low, and because it can't add device drives, so can't verify complicated application scenarios and escalate into system-level checking.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of verification method of SOC chip, be intended to solve prior art for existing verification platform, verification operation is complicated, and can't verify complicated application scenarios, can't realize in analogue system the problem of software-hardware synergism checking.
The embodiment of the invention is achieved in that a kind of verification method of SOC chip, and described method comprises the steps:
Load test procedure;
In the system interface function library, call corresponding system function according to described test procedure, according to described system function, and maintenance tabulation corresponding to described system function, generate at random affairs;
According to described at random affairs, treat test chip and verify.
The embodiment of the invention also provides a kind of verification system of SOC chip, and described system comprises:
Loader is used for loading test procedure;
The affairs generator is used for calling corresponding system function according to the test procedure that described loader loads in the system interface function library at random, according to described system function, and maintenance tabulation corresponding to described system function, generate at random affairs;
Authentication unit is used for the at random affairs according to described at random affairs generator generation, treats test chip and verifies.
The embodiment of the invention is called corresponding system function by the test procedure that loads in the system interface function library, according to system function, and maintenance tabulation corresponding to system function, generate at random affairs, according to affairs at random, treats test chip and verifies.So that the test procedure that the software engineer writes can directly move at existing verification platform, verification method is promoted to system-level checking, realized the software-hardware synergism checking, realized the checking of complex application context, simultaneously by low layer information is encapsulated, so that verification system is easy to use, and be easy to multiplexing.
Description of drawings
Fig. 1 is the structural drawing of the VMM verification platform of prior art provided by the invention;
Fig. 2 is the realization flow figure of the verification method of the SOC chip that provides of the embodiment of the invention one.
Fig. 3 is the process flow diagram of the test program development that provides of the embodiment of the invention one;
Fig. 4 is the at random realization flow figure of the method for affairs of the generation that provides of the embodiment of the invention two;
Fig. 5 is the realization flow figure of the realization example of the generation test affairs that provide of the embodiment of the invention two;
Fig. 6 is the at random realization flow figure of the method for affairs of the generation that provides of the embodiment of the invention three;
Fig. 7 is the realization flow figure of the realization example of the generation IO operation affairs that provide of the embodiment of the invention three;
Fig. 8 is the at random realization flow figure of the method for affairs of the generation that provides of the embodiment of the invention four;
Fig. 9 is the generation random number that provides of the embodiment of the invention four or the realization flow figure of random series realization example;
Figure 10 is the checking structural drawing of the SOC chip that provides of the embodiment of the invention five;
Figure 11 is the checking structural drawing of the SOC chip that provides of the embodiment of the invention six;
Figure 12 is the checking structural drawing of the SOC chip that provides of the embodiment of the invention seven;
Figure 13 is the structural drawing of the at random device configuration operation unit that provides of the embodiment of the invention seven;
Figure 14 is the structural drawing of the at random IO operating unit that provides of the embodiment of the invention seven;
Figure 15 is the structural drawing of the random series operating unit that provides of the embodiment of the invention seven;
Figure 16 is the process flow diagram of the proof procedure of the SOC chip that provides of the embodiment of the invention eight.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
The embodiment of the invention is called corresponding system function by the test procedure of above-mentioned loading in the system interface function library, according to the said system function, and maintenance tabulation corresponding to said system function, at random affairs generated, according to above-mentioned at random affairs, treat test chip and verify.
Technical scheme of the present invention for convenience of explanation describes below by specific embodiment:
Embodiment one
Fig. 2 shows the realization flow figure of the verification method of the SOC chip that the embodiment of the invention one provides, and details are as follows:
In step S201, load test procedure.
In embodiments of the present invention, test procedure can be realized following functions:
(1) flow process of control verification system.
(2) obtain and change the state of verification system.
(3) operate, access chip to be measured.
(4) produce the random test affairs and come test chip.
(5) operation that can finish of other standards C/C++.
In embodiments of the present invention, test procedure can be driver or application program, for example, can comprise master routine and interrupt service routine etc., wherein,
1, interrupt service routine can be the function with following form:
Int isr (int pid, int source, int port); All functions with above form all can to system registry, become interrupt service routine.
2, the mode of the registration of interrupt service routine in main test procedure, can call with minor function:
int?register_isr(int?pid，int?port，isr_pt?isr)；
Pid wherein is the test component numbering, and port is the interruptive port numbering, and isr is the function of wish registration.
The form of 3, interrupting can be divided into soft interruption and hard the interruption, be that the interruption that tested device sends is called " the hard interruption " by " hardware ", and test procedure also can send interruption to system, is called " soft interruption ".
Call lower array function and namely send soft interruption:
assert_irq(int?pid，int?source_id，int?port_id)
Wherein, pid is the test component numbering, and source_id is the interrupt source numbering, is used for showing that caller identity, port_id then are the interruptive port numberings.
In embodiments of the present invention, test procedure can have a plurality of, test procedure can be the c/c++ program of standard, at this moment, c/c++ compiler that can Application standard, and test procedure can exist with the form in test procedure storehouse, for example, can be compiled into the test procedure library file by gcc etc., the development process in test procedure storehouse can adopt development process as shown in Figure 3, on stream, according to the c/c++ library file, development and testing master routine and interrupt service routine are tested master routine and interrupt service routine and are compiled into file destination through gcc respectively, and all file destinations generate the test procedure storehouse through packing.
In embodiments of the present invention, can pass through Direct Programming interface (Direct Programming Interface, DPI) load test procedure, by the DPI interface, the C/C++ program can be called the function of EDA (Electronic design automation) language domains, and the EDA language domains also can be called the function of C/C++ language domains, when test procedure comprises master routine and interrupt service routine, the DPI interface also can have two accordingly, respectively corresponding master routine and interrupt service routine.
In step S202, in the system interface function library, call corresponding system function according to test procedure, according to system function, and maintenance tabulation corresponding to system function, generate at random affairs.
In embodiments of the present invention, affairs can comprise the random test affairs at random, IO operates affairs and/or random series operation affairs at random.
In embodiments of the present invention, in the system function storehouse, call corresponding system function, system function specifically can comprise control function, event functions, IO function, semaphore function, share the combination in any in data function, thread function or the randomized function, wherein:
(1) control function
Control function is used for the operation of control verification system, as suspending emulation, continues emulation, obtains simulation time, obtains the analogue system current state, changes system state etc., specifically can adopt:
Sim_finish (); // end emulation
Sim_stop (); The emulation of // time-out
Double get_time (); // obtain current simulation time
(2) event functions
Event functions be used between the test thread synchronously, wherein, the generation of event or can operate corresponding list of thing synchronously,
Int event_create (); // create an event column list item, return Case Number
Void event_trigger (int event_id); // trigger event triggers after certain simulated conditions occurs usually
Void event_sync (int event_id, int sync_type); // be synchronized to event, before occuring, event blocks thread
(3) semaphore function
The semaphore function is used for accessing shielded resource, can the tabulation of operation signal amount during the operation signal amount.
Int semaphore_create (int key_count); // creating a semaphore list item, the return signal amount is numbered
Void semaphore_get (int semaphore_id, int key_count); // application semaphore is if deficiency is then blocked until enough semaphores are arranged during signal.Before access resources, apply for.
Void semaphore_put (int semaphore_id, int key_count); // release semaphore has been accessed and has been answered release semaphore after the resource so that other threads can access resources.
(3) IO function
The IO function is used for directly accessing by the port address of device the function of tested device, when supporting multithreading, also needing to carry out between each IO operation is correct with the execution sequence of guaranteeing them synchronously, this is sequentially tabulated to guarantee by IO, the IO operation that is in the tabulation head is finished first, subsequent operation continue after, below be some IO function handling functions:
Void io_write (int pid, int address, int op_size, int data, int mask); // write device
Int io_read (int pid, int address, int op_size); // read device
Void io_burst_write (int pid, int address, int op_size, int burst_type, int*data, int*mask); // write device in the mode of bursting out
Void io_burst_read (int pid, int address, int op_size, int burst_type, int*data); // read device in the mode of bursting out
Void io_random_transfer (int pid, int start_address, int end_address, intop_size, int op, int burst_type, int ntests); // device is carried out random access
(4) share data function
When needs carried out data sharing between each thread of test procedure, shared data function can be placed in the general data list for each thread use sharing data.
Void scfg_create_reg (char*reg_name, int init_value); List item of // establishment
Void scfg_set_reg (char*reg_name, int value); // arrange one shared
Int scfg_get_reg (char*reg_name); // read one shared
Void scfg_wait_reg (char*reg_name, int exp_value, int mask); // wait for until shared value is designated value
Void scfg_wait_reg_created (char*reg_name); // wait for until shared item is created
Void scfg_wait_reg_write (char*reg_name); // wait for until shared value is set up
Void scfg_wait_reg_read (char*reg_name); // wait for until shared value is read
Void scfg_wait_reg_change (char*reg_name); // wait for until share the value change of item
Void scfg_wait_reg_not (char*reg_name, int exp_value, int mask); // wait for until shared value is not designated value
Void scfg_wait_reg_less (char*reg_name, int exp_value); // wait for until a value of sharing less than designated value
Void scfg_wait_reg_larger (char*reg_name, int exp_value); // wait for until a value of sharing greater than designated value
(5) thread function
Thread function is for generation of multithreading, and can carry out between thread synchronously, the operations such as cancellation, and thread list has been preserved the current thread of carrying out and their state.
Int io_fork (int (* io_func) (), int total_args ...); // carry out function in the parallel thread mode, return thread number
Void io_sync (int schedule_id); // synchronously, block until specify the thread execution of numbering complete
Void io_fiush (int pid); // synchronously, block until the main device of appointment is finished all IO operations
Void io_nop (int pid); // wait for and specify the upper IO operation of main device to finish
Void delay_t (double delay_time); // current thread is blocked one section simulation time
Void delay_clock (int pid, int clock_cycles); // current thread is blocked certain clock period
Void sim_pause (int pause_id); // current thread is suspended
Void sim_resume (int pause_id); The thread that is suspended is carried out in // continuation
(6) randomized function
Randomized function is used for the configuration of randomization tested device, when carrying out randomized function, random function produces a random series and deposits the stochastic ordering tabulation on the one hand, inquire about on the one hand the tested device configured list, find corresponding tested device and corresponding tested device configuration is loaded, random constraints is wherein described for generation of affairs at random.
Int randc (int max, int min); // from scope [min, max], obtain unduplicated random integers
Int randc_array (int*ResultArray, int ArraySize, int max, int min); // from scope [min, max], obtain ArraySize unduplicated random integers
Int randcase (weight_0 ...); // from subsequent branches, to get at random a branch to carry out, the weight of branch is respectively weight_0, weight_1 ... weight_N.
Void cfg_rand_regs (int pid, char*cfg_name ...); // randomization tested device register is to obtain the random arrangement value
Void cfg_set_rand_mask (int pid, char*cfg_name, char*reg_name, intrand_mask); // for the tested device register arranges random mask, do not need to guarantee randomized register to keep original value
Void cfg_flush_regs (int pid, char*cfg_name, char*reg_name...); // will be at random good register value is write tested device (DUT) by system bus
In embodiments of the present invention, safeguard that tabulation can comprise a plurality of different tabulations, being specially different system functions can carry out corresponding from different tabulations, for example, the corresponding list of thing of event functions, the corresponding IO tabulation of IO function, the tabulation of semaphore function respective signal amount, share the corresponding general data list of data function, the corresponding thread list of thread function, the corresponding stochastic ordering tabulation of randomized function and tested device configured list.
1. list of thing (event table)
List of thing represents to have occured when the event that satisfies certain condition, notifies in analogue system with synchronously.When certain event has occured in the somewhere of analogue system, just can state event and event is put into list of thing that other of analogue system is local just can carry out take this event as trigger condition handling procedure.Each thread can pass through the event functions Action Events.
2.IO tabulation (IO table)
Test procedure test tested device is realized by the register of access tested device possibly, the IO tabulation is in chronological sequence sequentially safeguarded these operations, realize the IO operation synchronously, guarantee the legitimacy of operation, also test procedure has been carried out synchronously simultaneously.
Test procedure can visit tested device by the IO function.
3. semaphore tabulation (semaphore table)
When a plurality of threads need to be accessed same resource, need to guarantee the alternative of access.Semaphore (semaphore) is exactly a kind of method that guarantees alternative.Every kind of corresponding several semaphores of resource; Need the first to file semaphore during thread accesses resource, if semaphore is not enough, then thread gets clogged, and just unblocks until obtain enough semaphores, has access to resource, and last release semaphore is so that other threads can access resources.Each thread can pass through semaphore function operation signal amount.
4. general data list (universal data table)
General data list has been preserved the data of general-use, can share for each thread of analogue system, and each thread can be by sharing the data function accessing universal.
5. thread list (scheduled thread table)
Test procedure can operate thread with thread function, test procedure can cause many sub-threads of carrying out simultaneously, safeguard this a little thread by thread list, meet expection with the execution sequence that guarantees thread, also be controllable simultaneously, for example, can finish at other thread waits threads, kill certain thread, cause sub-thread etc.
6. stochastic ordering tabulation (random sequence table)
The stochastic ordering tabulation is for safeguarding random series, so that the random series production process is transparent to test procedure, the programmer needn't be concerned about concrete implementation procedure, and test procedure can obtain random series by randomized function.
7. tested device configured list (device under test configuration table),
The tested device configured list has been preserved the inventory of all tested device configuration files (device under test configuration, dut_cfg) of current system.The corresponding tested device of each dut_cfg file.In operation during device under test, from the tested device configured list, search corresponding tested device and the tested device of correspondence is configured to produce the random test affairs.
In step S103, according to above-mentioned at random affairs, treat test chip and verify.
The embodiment of the invention is called corresponding system function by the test procedure of above-mentioned loading in the system interface function library, according to the said system function, and maintenance tabulation corresponding to said system function, generate at random affairs, according to above-mentioned at random affairs, treating test chip verifies, so that the test procedure that the software engineer writes can directly move at existing verification platform, realized the software-hardware synergism checking, simultaneously by low layer information is encapsulated, so that verification system is easy to use, and be easy to multiplexing.
Embodiment two
Fig. 4 show that the invention process two provides when affairs are the random test affairs at random, according to system function, and maintenance tabulation corresponding to system function, generate the at random process flow diagram of the realization of the method for affairs, details are as follows:
In step S401, in the tested device configured list, search the tested device configuration corresponding with above-mentioned tested device.
In embodiments of the present invention, each tested device has a tested device configuration, the tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, above-mentioned register image specifically comprises title, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values of register, above-mentioned constraint expression formula limits the scope of the stray parameter of tested device, is specially:
1, the register image of device under test comprises the title of register, address, bit wide, default value, a front Configuration Values, current Configuration Values etc.
2, the constraint expression formula of tested device, the constraint expression formula limits the scope of the stray parameter of tested device, and these expression formulas will be satisfied during randomization.Need satisfied logical relation, two logical relations that register need satisfy, the legal range of the value of register etc. such as current configuration and front once configuration.
In step S402, according to above-mentioned tested device configuration, generate the class object corresponding with the test affairs.
In embodiments of the present invention, determine register image and the constraint expression formula of tested device by the tested device configuration, and set up the class object corresponding with testing affairs according to tested device configuration, and with register image and the constraint expression formula member as class object.
In step S403, above-mentioned class object is carried out at random.
In step S404, according to described class object is advanced row stochastic result, generate the test affairs.
For the ease of understanding, below describe with the method for a specific implementation example to the embodiment of the invention, but be not limited with this realization example, specifically see also Fig. 5, when system function calls, search tested device by the tested device configured list, and the tested device that loads correspondence disposes, obtain register image and constraint expression formula by the tested device configuration, register image specifically comprises the title of tested device register, the address, bit wide, default value, currency, parameter and the configuration constraint expression formulas such as last sub-value, the attribute of class object is set simultaneously, with the member of the data in above-mentioned parameter and the stochastic ordering tabulation as the class object of in advance construction, separating the random device of constraint server calls class object carries out at random class object, solve the at random result of class object, finish class object at random after, with the as a result combination producing that solves test affairs, be sent to follow-up transaction processor after the test affairs produce, be driven into tested device by bus driver again.
In the embodiment of the invention, can be according at least 1 tested device configuration of difference setting of the type of formula device to be measured, specifically can comprise tested device configuration 1, tested device configuration 2 ... tested device configuration N, wherein, N is natural number, the value of concrete tested device configured number N can determine according to the actual needs, inferior not in order to limit the present invention.
In embodiments of the present invention, make by tested device configuration to produce at random that affairs become transparent, automatic, needn't consider the coverage rate of test vector when writing test procedure, needn't consider also how test vector produces.By automatically affairs at random being carried out randomization, guarantee that checking at random, comprehensively and robotization.
Embodiment three
Fig. 6 show that the invention process three provides when affairs at random during for IO operation affairs at random, according to system function, and maintenance tabulation corresponding to system function, generate the at random realization flow figure of the method for affairs, details are as follows:
In step S601, determining needs randomized stray parameter in the IO function at random.
In step S602, by the IO tabulation, in chronological sequence order produces the random value of above-mentioned stray parameter.
In step S603, according to the random value of above-mentioned stray parameter, generate at random IO operation affairs.
For the ease of understanding, below describe with the method for a specific implementation example to the embodiment of the invention, but be not limited with this realization example, specifically see also Fig. 7, when affairs at random during for IO operation affairs at random, according to the parameter of IO function at random, determine which parameter can be by at random, which is fixed, wherein, by at random can be operation address, operand, mode bursts out, then modes of operation etc., tabulate by IO, in chronological sequence take out address and address random mask in turn, operand and operand random mask, mode of operation and mode of operation random mask and burst out mode and the mode mask that bursts out, when needs at random the time, calling system random function, address acquisition, operand, the random value of mode of operation and the stray parameters such as mode that burst out, according to the random value of stray parameter, generate at random IO operation affairs.
Embodiment four
Fig. 8 show that the invention process four provides when affairs are random series operation affairs at random, according to system function, and maintenance tabulation corresponding to system function, generate the at random realization flow figure of the method for affairs, details are as follows:
In step S801, determine the random number of test procedure needs or the parameter of random series.
In step S802, according to stochastic ordering tabulation and above-mentioned parameter, calculate random number or random series that test procedure needs.
In step S803, random number or the random series that calculates returned to test procedure, and be kept in the stochastic ordering tabulation.
For the ease of understanding, below describe with the method for a specific implementation example to the embodiment of the invention, but be not limited with this realization example, specifically see also Fig. 9, in this realization example, test procedure need to obtain random number or the random number sequence that satisfies specified conditions.According to the known value in the stochastic ordering tabulation, and above-mentioned parameter, comprise that known value in the system function that calls, weight and scope use the method for mathematical operation to calculate qualified number or array returns to test procedure, and the result is kept in the stochastic ordering tabulation to treat that make next time, can delete simultaneously time item the earliest in the stochastic ordering tabulation, to keep item number that stochastic ordering tabulates as fixed value.
Embodiment five
Figure 10 shows the structure of the verification system of the SOC chip that the embodiment of the invention five provides, and for the ease of understanding, only shows the structure of relevant portion.
The structure of the system of the embodiment of the invention specifically comprises loader 101, at random affairs generator 102 and authentication unit 103, wherein:
In embodiments of the present invention, loader 101 loads test procedure, specifically can load and move the test master routine in the trial function storehouse or test interrupt service routine, when tested device does not interrupt producing, then loads test master routine and operation; And when tested device sends interrupt request, then load interrupt service routine and operation, and at this moment, the test master routine is suspended to suspend and carries out, then carries out interrupt service routine, and after interrupt service routine was complete, the test master routine continued to carry out.
According to the at random affairs that above-mentioned at random affairs generator 102 produces, authentication unit 103 is treated test chip and is verified.
When affairs were the random test affairs at random, described at random affairs generator 102 comprised that device searches unit, class object generation unit, class object random cells and test affairs generation unit, is specially:
Device is searched the unit in the tested device configured list, searches the tested device configuration corresponding with described tested device.
In embodiments of the present invention, described tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, described register image specifically comprises title, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values of register, and described constraint expression formula limits the scope of the stray parameter of tested device
Search the tested device configuration of searching the unit according to described device, the class object generation unit generates the class object corresponding with the test affairs.
The class object random cells is carried out at random the class object that described class object generation unit generates.
According to described class object random cells class object is advanced row stochastic result, test affairs generation unit generates the test affairs.
When affairs at random during for IO operation affairs at random, described at random affairs generator 102 comprises stray parameter determining unit, random value generation unit and IO operation generation unit, is specially:
The stray parameter determining unit is determined to need randomized stray parameter in the IO function at random.
By the IO tabulation, random value generation unit in chronological sequence order produces the random value that described stray parameter determining unit is determined stray parameter.
The random value of the stray parameter that generates according to described random value generation unit, IO operation generation unit generates at random IO operation affairs.
When affairs were random series operation affairs at random, described at random affairs generator 102 comprised random series determining unit, random series determining unit, computing unit and returns the unit, is specially:
The random series determining unit is determined the random number of test procedure needs or the parameter of random series.
According to stochastic ordering tabulation and the definite parameter of described random series determining unit, computing unit calculates random number or the random series that test procedure needs.
Return the unit random number or the random series that described computing unit calculates returned to test procedure, and be kept in the stochastic ordering tabulation.
The embodiment of the invention loads test procedure by loader, and in the system interface function library, call corresponding system function, according to the said system function, and maintenance tabulation corresponding to said system function, generate at random affairs, according to above-mentioned at random affairs, treat test chip and verify, so that the test procedure that the software engineer writes can directly move at existing verification platform, realized the software-hardware synergism checking.
Embodiment six
Figure 11 shows the structure of the SOC chip checking system that the embodiment of the invention six provides, and for the ease of understanding, only shows the structure of relevant portion.
In embodiments of the present invention, can pass through Direct Programming interface (Direct Programming Interface, DPI) start-up loading device, and the test procedure that loads is loaded on analogue system, by the DPI interface, the C/C++ program can be called the function of EDA (Electronic design automation) language domains, and the EDA language domains also can be called the function of C/C++ language domains.
Wherein, test procedure can comprise master routine and interrupt service routine, and the DPI interface of corresponding system can comprise master routine DPI interface 111 and interrupt routine DPI interface 112.
In embodiments of the present invention, when tested device does not interrupt producing, carry out the test master routine, when tested device sends interrupt request, carry out interrupt service routine, when having a plurality of interrupt request to arrive, system can comprise that interrupt manager 114 carries out priority management and interrupt nesting management.
Embodiment seven
Figure 12 shows the structure of the SOC chip checking system that the embodiment of the invention seven provides, and for the ease of understanding, only shows the structure of relevant portion.
The corresponding system function that calls in system interface function library 125 of affairs generator at random, system function specifically comprises: control function, event functions, IO function, semaphore function, share data function, thread function or randomized function.
The corresponding maintenance of system function operation tabulates 126, safeguards that the tabulation kind specifically comprises: list of thing, IO tabulation, semaphore tabulation, general data list, thread list, stochastic ordering tabulation and tested device configured list.
In embodiments of the present invention, affairs generator 128 comprises at random device configuration operation unit 1281, at random IO operating unit 1282 and/or random series operating unit 1283 at random.
Wherein, Figure 13 shows the device that specifically comprises of device configuration operation unit at random and searches module 131, class object generation module 132, class object at random module 133 and test affairs generation module 134, wherein:
Device is searched module 131 in tested device configured list 127, searches the tested device configuration corresponding with above-mentioned tested device, and the loading tested device configuration corresponding with tested device.
In embodiments of the present invention, the tested device configuration can comprise the register image of tested device and the constraint expression formula of tested device, above-mentioned register image specifically comprises title, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values of register, and above-mentioned constraint expression formula limits the scope of the stray parameter of tested device.
Search the tested device configuration that module 131 is searched according to above-mentioned device, class object generation module 132 generates the class object corresponding with the test affairs.
The class object at random class object of 133 pairs of above-mentioned class object generation modules 132 generations of module carries out at random.
In embodiments of the present invention, class object at random module 131 calls the random device of corresponding class object, and class object is carried out at random.
According to above-mentioned class object at random 133 pairs of class objects of module advance row stochastic result, test affairs generation module 134 generates the test affairs.
Figure 14 shows the concrete structure of above-mentioned at random IO operating unit:
Stray parameter determination module 141 is determined to need randomized stray parameter in the IO function at random.
Random value generation module 142 is by safeguarding the IO tabulation in the tabulation 126, and in chronological sequence order produces the random value that the stray parameter determination module is determined stray parameter.
The random value of the stray parameter that generates according to random value generation module 142, IO operation generation module 143 generates at random IO operation affairs.
Figure 15 shows the concrete structure of above-mentioned random series operating unit:
The random number that random series determination module 151 definite test procedures need or the parameter of random series.
According to the parameter that stochastic ordering is tabulated and random series determination module 151 is determined of safeguarding in the tabulation 126, computing module 152 calculates random number or the random series that test procedures need.
Embodiment eight
Figure 16 shows the proof procedure of the SOC chip that the embodiment of the invention eight provides:
(1) Hardware Engineer designs tested device (device under test, DUT), and register-transmitting stage code (Register Transfer Level Code, RTL) is provided
(2) Hardware Engineer or checking slip-stick artist extract the tested device configuration constraint file (device under test configuration, dut_cfg) of outlines device characteristic according to the hardware design specifications.
(3) the checking slip-stick artist is ready to verification system miscellaneous part such as transaction processor, bus driver, monitor, automatic comparer etc. according to the verification methodology (such as VMM) of current popular.
(4) the checking slip-stick artist connects into verification system with above-mentioned DUT, dut_cfg, parts of the present invention and verification platform miscellaneous part.
(5) checking slip-stick artist or software engineer is ready to test procedure with the c/c++ language compilation as test file, and for example, test procedure can be driver or application program.
(6) checking slip-stick artist or software engineer are compiled into the test procedure library file with test file with standard c/c++ compiler.
(7) checking Utility Engineers EDA emulator compiling verification system.
(8) checking slip-stick artist with the time as random seed (random seed) runtime verification system.
(9) after emulation began, master controller was loaded into verification system and operation by loader with the test procedure library file.
(10) the verification system run duration may find that hardware logic behavior, performance etc. define inconsistent defective (bug) with the hardware design specifications, at this moment, automatically comparer suspends verification system, record random seed and derive simulation waveform, transfer to and verify that slip-stick artist, Hardware Engineer debug jointly; Use identical random seed to rerun verification system and can reappear the defective scene, convenient debugging.After the Hardware Engineer changed design, the checking slip-stick artist recompilated verification system.
(11) if the verification system run duration is not found hardware deficiency, verification system moves until current trial function is finished.
(12) after current trial function is finished, check the DUT code coverage.
(13) if do not reach the coverage rate target of setting, then repeated for 8～12 steps to re-start next time random simulation, until code coverage finishes emulation when making it.
To sum up above-mentioned, the embodiment of the invention is called corresponding system function by the test procedure of above-mentioned loading in the system interface function library, according to the said system function, and maintenance tabulation corresponding to said system function, generate at random affairs, according to above-mentioned at random affairs, treat test chip and verify., so that the test procedure that the software engineer writes can directly move at existing verification platform, realized the software-hardware synergism checking, simultaneously by low layer information is encapsulated, so that verification system is easy to use, and be easy to multiplexing.
In addition, make by tested device configuration to produce at random that affairs become transparent, automatic, needn't consider the coverage rate of test vector when writing test procedure, needn't consider also how test vector produces.By automatically affairs at random being carried out randomization, guarantee that checking at random, comprehensively and robotization.
It should be noted that what the included unit of said system was just divided according to function logic, but be not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional unit also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that all or part of step that realizes in above-described embodiment method is to come the relevant hardware of instruction to finish by program, corresponding program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. the verification method of a SOC chip is characterized in that, described method comprises the steps:
Load test procedure;
In the system interface function library, call corresponding system function according to described test procedure, according to described system function, and maintenance tabulation corresponding to described system function, generate at random affairs;
According to described at random affairs, treat test chip and verify.
2. the method for claim 1 is characterized in that, and is described according to described system function when affairs are the random test affairs at random, and maintenance tabulation corresponding to described system function, and generating at random, the step of affairs is specially:
In the tested device configured list, search the tested device configuration corresponding with described tested device;
According to described tested device configuration, generate the class object corresponding with the test affairs;
Described class object is carried out at random;
According to described class object is advanced row stochastic result, generate the test affairs.
3. method as claimed in claim 2, it is characterized in that, described tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, described register image specifically comprises title, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values of register, and described constraint expression formula limits the scope of the stray parameter of tested device.
4. the method for claim 1 is characterized in that, and is described according to described system function when affairs at random during for IO operation affairs at random, and maintenance tabulation corresponding to described system function, and generating at random, the step of affairs is specially:
Determining needs randomized stray parameter in the IO function at random;
By the IO tabulation, in chronological sequence order produces the random value of described stray parameter;
According to the random value of described stray parameter, generate at random IO operation affairs.
5. the method for claim 1 is characterized in that, and is described according to described system function when affairs are random series operation affairs at random, and maintenance tabulation corresponding to described system function, and generating at random, the step of affairs is specially:
Determine the random number of test procedure needs or the parameter of random series;
According to stochastic ordering tabulation and described parameter, calculate random number or random series that test procedure needs;
The described random number that calculates or random series are returned to test procedure, and be kept in the stochastic ordering tabulation.
6. the method for claim 1 is characterized in that, described test procedure comprises test master routine and test interrupt service routine;
When tested device does not interrupt producing, carry out the test master routine;
When tested device sends interrupt request, carry out interrupt service routine.
7. the verification system of a SOC chip is characterized in that, described system comprises:
Loader is used for loading test procedure;
The affairs generator is used for calling corresponding system function according to the test procedure that described loader loads in the system interface function library at random, according to described system function, and maintenance tabulation corresponding to described system function, generate at random affairs;
Authentication unit is used for the at random affairs according to described at random affairs generator generation, treats test chip and verifies.
8. system as claimed in claim 7 is characterized in that, when affairs were the random test affairs at random, described at random affairs generator comprised:
Device is searched the unit, is used at the tested device configured list, searches the tested device configuration corresponding with described tested device;
The class object generation unit is searched the tested device configuration of searching the unit according to described device, generates the class object corresponding with the test affairs;
The class object random cells is used for the class object that described class object generation unit generates is carried out at random;
Test affairs generation unit is used for according to described class object random cells class object being advanced row stochastic result, generates the test affairs.
9. system as claimed in claim 8, it is characterized in that, described tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, described register image specifically comprises title, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values of register, and described constraint expression formula limits the scope of the stray parameter of tested device.
10. system as claimed in claim 7 is characterized in that, when affairs at random during for IO operation affairs at random, described at random affairs generator comprises:
The stray parameter determining unit is used for determining that the IO function needs randomized stray parameter at random;
The random value generation unit is used for the tabulation by IO, and in chronological sequence order produces the random value that described stray parameter determining unit is determined stray parameter;
IO operates generation unit, is used for the random value according to the stray parameter of described random value generation unit generation, generates at random IO operation affairs.
11. system as claimed in claim 7 is characterized in that, when affairs were random series operation affairs at random, described at random affairs generator comprised:
The random series determining unit is used for determining the random number of test procedure needs or the parameter of random series;
Computing unit is used for calculating random number or random series that test procedure needs according to stochastic ordering tabulation and the definite parameter of described random series determining unit;
Return the unit, the random number or the random series that are used for described computing unit is calculated return to test procedure, and are kept in the stochastic ordering tabulation.
12. system as claimed in claim 7 is characterized in that, described test procedure comprises test master routine and test interrupt service routine.
13. system as claimed in claim 7 is characterized in that, described system also comprises interrupt manager, is used for carrying out the management of priority management and interrupt nesting when having a plurality of interrupt request to arrive.
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| PCT/CN2012/076895 WO2013016979A1 (en) | 2011-07-29 | 2012-06-14 | Method and system for verifying soc chip |
| PCT/CN2012/079225 WO2013017037A1 (en) | 2011-07-29 | 2012-07-26 | Method and system for verifying soc chip |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2013017037A1 (en) | 2013-02-07 |
| WO2013016979A1 (en) | 2013-02-07 |
| CN102902834B (en) | 2015-12-09 |
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Effective date of registration: 20150106 Address after: 519085 C District, 1# workshop, No. 1, science and technology No. four road, hi tech Zone, Zhuhai, Guangdong, China Applicant after: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. Address before: 519085 hi tech Zone, Guangdong, Zhuhai science and Technology Innovation Coast Road, No. four, No. 1 Applicant before: Juli Integrated Circuit Design Co., Ltd. |
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Address after: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee after: ACTIONS TECHNOLOGY Co.,Ltd. Address before: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee before: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. |
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