CN112527350A - IP core for configuration and refresh control of satellite-borne SRAM type FPGA - Google Patents

IP core for configuration and refresh control of satellite-borne SRAM type FPGA Download PDF

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CN112527350A
CN112527350A CN202011420884.8A CN202011420884A CN112527350A CN 112527350 A CN112527350 A CN 112527350A CN 202011420884 A CN202011420884 A CN 202011420884A CN 112527350 A CN112527350 A CN 112527350A
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周莉
董文涛
杨根
安军社
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National Space Science Center of CAS
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Abstract

The invention discloses an IP core for satellite-borne SRAM type FPGA configuration and refresh control, which is used for reading FPGA configuration files under the control of an external processor and carrying out on-orbit configuration and refresh control on a single or a plurality of FPGAs, and comprises: the system comprises a configuration file reading and state output module, a data storage and analysis module, an enabling control module and a configuration refreshing top module; the configuration file reading and state output module is used for reading the FPGA configuration file, receiving the processor instruction and outputting the refreshing state of the FPGA; the data storage and analysis module is used for reading the FPGA configuration file, decoding the FPGA configuration file and sending the FPGA configuration file to the configuration refreshing top module; the enabling control module is used for generating a configuration enabling signal and a refreshing enabling signal and sending the configuration enabling signal and the refreshing enabling signal to the configuration refreshing top-layer module; and the configuration refreshing top-layer module is used for generating a configuration control command and a refreshing control command, sending the configuration control command and the refreshing control command to a specified FPGA, and reading the refreshing state of the FPGA.

Description

IP core for configuration and refresh control of satellite-borne SRAM type FPGA
Technical Field
The invention relates to the technical field of aviation and aerospace electronics integration, in particular to an IP core for configuration and refresh control of a satellite-borne SRAM type FPGA.
Background
The FPGA is widely applied to spacecraft electronic systems due to diversity and repeatability during function configuration and flexibility and high efficiency during mass data processing, and undertakes tasks such as digital signal processing, image processing and the like under a space environment, wherein SRAM type Virtex series FPGA of Xilinx company have advantages in performance and capacity, and can be reconfigured according to different functional requirements.
However, the FPGA of the SRAM process is greatly affected by the spatial radiation. The logic state of the internal configuration memory is often flipped by the impact of energetic particles (single event upsets), which may result in loss of spacecraft information or a functional disruption. Due to the particularity of the space environment, the reliability becomes an important index of the spacecraft, and the fault-tolerant design is indispensable in a spacecraft electronic system.
Except for triple modular redundancy design, configuration, refreshing (Scrubbing) and readback are three major technologies commonly used for SRAM type FPGA single event upset in aerospace. Refreshing also belongs to Partial Reconfiguration in theory, and in official documents given by the company Xilinx, refreshing is equivalent to active Reconfiguration. Not all SRAM technology FPGAs support this function and must have a specific technology. At present, each series of FPGA of Virtex of Xilinx company supports refreshing.
The refresh is an operation of directly rewriting configuration data without erasing configured logic in advance after the FPGA is powered on and configured successfully. Refresh is actually a recovery measure after an SEU occurs, so it requires the coordination of TMR, fault-tolerant coding, etc. to achieve good results. The fault tolerant scheme based on "TMR + scattering" promulgated by Xilinx is widely used in many satellites.
Configuration or reloading is an effective measure for recovering functions when the function of the FPGA fails.
The Select MAP configuration mode has 8bits of configuration data and 7 bits of control signals, and specific information is shown in table 1. After the control signal preparation is completed, the configuration bit stream is written with 8bits of configuration data at the same time on each clock rising edge. The D0 pin is the Most Significant Bit (MSB) of each configuration byte; in contrast, the D7 pin is the Least Significant Bit (LSB). In order to perform scrub and read back operations on the FPGA after the power-on configuration process is completed, the D [7:0] eight-bit data interface and the BUSY and INIT _ B, RDWR _ B, CS _ B pins need to be reserved and not used as common I/O interfaces. Fig. 1 shows a timing chart of the arrangement.
Table 1 Virtex-II series FPGA Select MAP mode configuration pin
Figure BDA0002822319590000021
At present, some SRAM FPGA refreshing designs exist in China, and the problems of few types of supported refreshing FPGA chips, few number of supported refreshing FPGA chips, incapability of configuring software, poor expandability and to-be-verified reliability exist.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an IP core for configuring and refreshing a satellite-borne SRAM type FPGA, which has the characteristics of strong expansibility and portability.
In order to achieve the above object, the present invention provides an IP core for configuring and refresh controlling a satellite-borne SRAM-type FPGA, which is configured to read an FPGA configuration file under the control of an external processor, and perform on-track configuration and refresh control on one or more SRAM-type FPGAs, and is characterized in that the IP core includes: the system comprises a configuration file reading and state output module, a data storage and analysis module, an enabling control module and a configuration refreshing top module; the configuration file reading and state output module is connected with an external processor, a control register or a memory, and the configuration refreshing top module is connected with the SRAM type FPGAs through a selectMAP bus interface; wherein the content of the first and second substances,
the configuration file reading and state output module is used for reading the FPGA configuration files, receiving external processor instructions and sending the instructions to the enabling control module, and is also used for outputting the refreshing state of each FPGA to an external processor;
the data storage and analysis module is used for reading the FPGA configuration file from the configuration file reading and state output module, decoding the FPGA configuration file and sending the decoded configuration data to the configuration refreshing top module;
the enabling control module is used for respectively generating a configuration enabling signal and a refreshing enabling signal according to an external processor instruction, an input reset signal and a synchronization signal by combining the type of the FPGA and sending the configuration enabling signal and the refreshing enabling signal to the configuration refreshing top-layer module; the FPGA is also used for receiving the refreshing state of the FPGA for storage and sending the refreshing state to the configuration file reading and state output module;
and the configuration refreshing top module is used for generating a configuration control command according to the configuration enabling signal and the configuration data, sending the configuration control command to the appointed FPGA through the selectMAP bus interface, generating a refreshing control command according to the refreshing enabling signal, sending the refreshing control command to the appointed FPGA through the selectMAP bus interface, reading the refreshing state of the FPGA and sending the refreshing state to the enabling control module.
As an improvement of the above IP core, the FPGA configuration file is hamming encoded by an external processor, and the external processor specifies a storage address and a length and then writes the address and the length into an external memory, and each FPGA corresponds to one FPGA configuration file.
As an improvement of the above IP core, the configuration file reading and status output module includes an APB bus unit, an AXI bus unit, a DMA unit, and an address management unit; wherein the content of the first and second substances,
the APB bus unit is used for reading the FPGA configuration file, receiving an external processor instruction and sending the instruction to the enabling control module, and is also used for outputting the refreshing state of the FPGA to the outside;
the AXI bus unit to control a DMA unit;
the DMA unit is used for reading the FPGA configuration file under the control of the AXI bus unit;
and the address management unit is used for performing address accumulation on the DMA unit according to the read address accumulation enabling signal output by the configuration refreshing top module.
As an improvement of the above IP core, the AXI bus unit operates in master mode, actively initiating read operations according to external processor instructions.
As an improvement of the above IP core, the data storage and analysis module includes a multiplexer, a buffer FIFO, a data signal synchronization unit, and an ECC decoding unit; wherein the content of the first and second substances,
the multiplexer is used for selecting to read the FPGA configuration file from the APB bus unit or the DMA unit and sending the FPGA configuration file to the buffer FIFO;
the buffer FIFO is used for caching the FPGA configuration file;
the data signal synchronization unit is used for reading the FPGA configuration file from the buffer FIFO and sending the FPGA configuration file to the ECC decoding unit;
the ECC decoding unit is used for decoding the FPGA configuration file by adopting a Hamming code, and when no error or one-bit error occurs in decoding, the ECC decoding unit automatically corrects the decoding configuration data and then sends the decoded configuration data to the configuration refreshing top module; when two or more bits of errors occur during decoding, an interrupt notification is sent to an external processor.
As an improvement of the above IP core, the enable control module includes a frequency dividing unit, a reset synchronization unit, and a control register unit; wherein the content of the first and second substances,
the frequency dividing unit is used for setting a distribution coefficient according to the frequency of the input clock to realize the control of the refreshing speed;
the reset synchronization unit is used for receiving a reset signal for synchronization and sending the synchronized reset signal to the configuration file reading and state output module, the data storage and analysis module and the configuration refreshing top module;
the control register unit is used for storing the received processor instruction, the frequency division value, the DMA starting address, the DMA length, the DMA command, the refresh command, the type and the number of the FPGA to be refreshed and the refresh state; and the FPGA is also used for sending the refresh state of the FPGA to the APB bus unit.
As an improvement of the above IP core, the control register unit includes an FIFO input register, a frequency division configuration register, a DMA start address register, a DMA length register, a DMA command register, a refresh configuration register, and a refresh status register; wherein the content of the first and second substances,
the FIFO input register is used for storing the FPGA configuration data received from the APB bus unit;
the frequency division configuration register is used for storing a frequency division value, and the rate of the system clock divided by the 2-time frequency division value is the refresh clock;
the DMA starting address register is used for storing the starting address of DMA starting operation;
the DMA length register is used for storing the length of DMA starting operation;
the DMA command register is used for storing a starting mark, a stopping mark, an ending mark, a clearing mark, a bus idle mark and an FIFO effective mark;
the refresh command register is used for storing configuration enabling and refresh enabling;
the refreshing configuration register is used for storing the type of the FPGA to be refreshed through low 4 bits and storing the chip selection number of the FPGA to be refreshed through high 8bits, and the number of the FPGAs to be refreshed is less than or equal to 24;
and the refresh state register is used for storing the refresh state of the FPGA.
As an improvement of the above IP core, the configuration refresh top module includes a configuration refresh command generation unit and a configuration refresh execution unit; wherein the content of the first and second substances,
the configuration refreshing instruction generating unit is used for acquiring a configuration enabling signal from a refreshing command register of the control register, decoding the configuration enabling signal to generate a configuration instruction, sending the configuration instruction to the configuration refreshing execution unit, acquiring a refreshing enabling signal from a refreshing command register of the control register, decoding the refreshing enabling signal to generate a refreshing instruction, and sending the refreshing instruction to the configuration refreshing execution unit; the refreshing instruction comprises a single refreshing instruction and a circulating refreshing instruction;
the configuration refreshing execution unit is used for generating a configuration control command according to the configuration command and the configuration data decoded by the ECC decoding unit and outputting the configuration control command to the selectMAP bus, generating a refreshing control command according to the refreshing command and the FPGA configuration data decoded by the ECC decoding unit and outputting the refreshing control command to the selectMAP bus, reading the refreshing state of the FPGA and sending the refreshing state to the refreshing state register, and sending a read address accumulation enabling signal to the address management unit;
as an improvement of the above IP core, when the configuration or refresh is not finished and the buffer FIFO is empty, the configuration refresh execution unit stops outputting the refresh clock, and when the buffer FIFO is not empty, the configuration refresh execution unit continues outputting the refresh clock.
Compared with the prior art, the invention has the advantages that:
1. the IP core has the advantages of configurable software and extensible hardware;
2. the IP core has the advantages of strong portability, simple realization and low cost;
3. the IP core can realize the automatic one-correction and two-detection function on the configuration information and has the advantage of high reliability.
Drawings
FIG. 1 is a timing diagram of the configuration of Select MAP;
FIG. 2 is a system component diagram of a configuration and refresh control IP core of a satellite-borne SRAM-type FPGA of the present invention;
FIG. 3 is a schematic diagram of the configuration of the on-board SRAM type FPGA and the peripheral components of the refresh control IP core of the present invention.
Detailed Description
The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and examples.
As shown in fig. 2, the present application provides an IP core for configuration and refresh control of an on-board SRAM-type FPGA, which is used to read an FPGA configuration file under the control of an external processor, perform on-track configuration and refresh control on a single or multiple SRAM-type FPGAs,
1) the IP core is connected with an external processor through an APB bus to realize the control of an internal register of the IP core;
2) the IP core accesses an external memory through an AXI bus and a DMA or an APB bus to read the configuration file;
3) the IP core realizes the configuration and the refreshing of a plurality of external SRAM FPGAs through a selectMAP bus interface;
4) the software is configurable, the hardware is expandable, the portability is strong, and the control and refresh functions of the SRAM type FPGA can be realized by transplanting the software into an FPGA, an ASIC or an SOC chip.
As shown in fig. 3, a schematic diagram of the configuration of the satellite-borne SRAM-type FPGA and the peripheral composition of the refresh control IP core of the present invention is shown, the IP core of the present invention may be deployed in an FPGA, an ASIC, or an SOC, and the modules related to the refresh function in the diagram are a processor (CPU core), an APB bus, an AXI bus, an EMI interface, a Nor flash, and an external SRAM FPGA. The SRAM FPGA is an FPGA to be loaded or refreshed; the Nor flash stores the configuration file of the SRAM FPGA; the CPU core can configure a register in the IP core through an APB bus so as to control the configuration and the refreshing of the SRAM FPGA; the EMI interface mainly realizes the reading of Nor flash data by AXI or APB buses. The configuration files of the FPGAs are written into an external memory after being subjected to Hamming coding by the CPU, the addresses and the lengths of the configuration files of the FPGAs are specified by the CPU, single or multiple FPGAs are supported to be updated on track, and the flexibility is high.
The IP core of the present invention is further described below.
The IP core comprises: the system comprises a configuration file reading and state output module, a data storage and analysis module, an enabling control module and a configuration refreshing top module; the configuration file reading and state output module is connected with an external processor, a control register or a memory, and the configuration refreshing top module is connected with the SRAM type FPGAs through a selectMAP bus interface;
the configuration file reading and state output module comprises an APB bus unit, an AXI bus unit, a DMA unit and an address management unit; wherein the content of the first and second substances,
the APB bus unit is used for reading the FPGA configuration file, receiving an external processor instruction and sending the instruction to the enabling control module, and is also used for outputting the refreshing state of the FPGA to the outside; the APB bus unit is connected with a processor outside the IP core and an internal control register module, so that the control of the external processor on the whole IP core can be realized; the APB bus unit can also directly read an external memory for storing the FPGA configuration file, and the read configuration file data is written into the buffer FIFO through the multiplexer.
The AXI bus unit reads the memory for externally storing the FPGA configuration file by controlling the DMA unit, and the DMA unit writes the read configuration file data into the buffer FIFO through the multiplexer according to the DMA initial address and the length given by the DMA related register. The AXI bus unit works in a master mode, actively initiates read operation according to instructions, and writes read data into a buffer FIFO.
The address management unit is used for performing address accumulation according to the read address accumulation enabling output by the configuration refreshing execution unit, and when the refreshing is finished, the address is clear 0; the next time a new refresh is initiated, a new address is executed.
The data storage and analysis module comprises a multiplexer, a buffer FIFO, a data signal synchronization unit and an ECC decoding unit; wherein the content of the first and second substances,
the multiplexer is used for selecting to read the FPGA configuration file from the APB bus unit or the DMA unit and sending the FPGA configuration file to the buffer FIFO; the multiplexer selects the DMA channel when configured in the DMA access mode.
The buffer FIFO is used for caching the FPGA configuration file;
the data signal synchronization unit is used for reading the FPGA configuration file from the buffer FIFO and sending the FPGA configuration file to the ECC decoding unit;
and the ECC decoding unit is used for reading the data in the buffer FIFO by the data signal synchronization unit, carrying out ECC decoding and sending the decoded data to the configuration refresh execution unit. The ECC decoding adopts (8,6) Hamming codes, can automatically correct one-bit errors in the reading configuration information, and can send out an interrupt to inform a CPU when two or more bits of errors occur.
The enabling control module comprises a frequency division unit, a reset synchronization unit and a control register unit; wherein the content of the first and second substances,
the frequency division unit is used for setting a distribution coefficient according to the frequency of the input clock to realize the control of the refreshing speed;
the reset synchronization unit is used for receiving the reset signal for synchronization and sending the synchronized reset signal to other units in the IP core;
the control register unit composition is shown in table 2, and comprises 8 registers:
1) data _ in is a FIFO input register, and APB writes the register, namely Data is written into a buffer FIFO;
2) div _ cfg is a frequency division configuration register, and the rate of the refresh clock is obtained by dividing the system clock by 2 times the value of the register;
3) dma _ source is a DMA start address register, and the address needs to be configured when starting DMA operation;
4) dma _ cnt is a DMA length register, and the address needs to be configured when the DMA operation is started;
5) dma _ cmd is a Dma command register that includes control and status bits for start, stop, end flag, clear flag, bus idle, FIFO valid, etc., the address needs to be configured when Dma operation is started;
6) smap _ cmd is a refresh command register, comprises configuration enable and refresh enable two bits, and can be configured into single refresh or cycle refresh;
7) smap _ cfg is a refresh configuration register, the lower 4 bits represent the type of the refreshed FPGA (such as XC2V3000, XC4VSX55 and the like), and the upper 8bits represent the chip selection number of the refreshed FPGA and can be expanded into 24 chips.
8) status is a refresh status register, which represents whether the refreshed status is normal or not.
TABLE 2 register List
Figure BDA0002822319590000071
Figure BDA0002822319590000081
The configuration refreshing top-layer module comprises a configuration refreshing instruction generating unit and a configuration refreshing execution unit; wherein the content of the first and second substances,
the configuration refreshing instruction generating unit carries out clock synchronization on the configuration values in the control register, and decodes the synchronized configuration values to generate instructions to the configuration refreshing execution unit, so that the configuration refreshing execution unit can be configured to single refreshing or cycle refreshing.
And the configuration refreshing execution unit generates configuration or refreshing logic of the SRAM FPGA according to the instruction generated by the configuration refreshing instruction generation unit and the data decoded by the ECC decoding unit and outputs the configuration or refreshing logic to the selectMAP bus. The reliability design of the unit is that when the configuration or refresh is not finished and the buffer FIFO is empty, the configuration refresh execution unit does not output the refresh clock, and continues to output the refresh clock when the FIFO is not empty, and continues to refresh.
The IP core can realize time-sharing loading and refreshing of a plurality of pieces of multi-type SRAM FPGAs, the number of refreshed pieces is configurable by the number of chip selection pins of a selectMAP bus and an internal control register, the current design supports 8 SRAM FPGA time-sharing periodic refreshing, and the IP core can be expanded into 24 pieces according to project requirements.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (9)

1. An IP core for on-board SRAM-type FPGA configuration and refresh control for reading FPGA configuration files under the control of an external processor to perform on-track configuration and refresh control of one or more SRAM-type FPGAs, the IP core comprising: the system comprises a configuration file reading and state output module, a data storage and analysis module, an enabling control module and a configuration refreshing top module; the configuration file reading and state output module is connected with an external processor, a control register or a memory, and the configuration refreshing top module is connected with the SRAM type FPGAs through a selectMAP bus interface; wherein the content of the first and second substances,
the configuration file reading and state output module is used for reading the FPGA configuration files, receiving external processor instructions and sending the instructions to the enabling control module, and is also used for outputting the refreshing state of each FPGA to an external processor;
the data storage and analysis module is used for reading the FPGA configuration file from the configuration file reading and state output module, decoding the FPGA configuration file and sending the decoded configuration data to the configuration refreshing top module;
the enabling control module is used for respectively generating a configuration enabling signal and a refreshing enabling signal according to an external processor instruction, an input reset signal and a synchronization signal by combining the type of the FPGA and sending the configuration enabling signal and the refreshing enabling signal to the configuration refreshing top-layer module; the FPGA is also used for receiving the refreshing state of the FPGA for storage and sending the refreshing state to the configuration file reading and state output module;
and the configuration refreshing top module is used for generating a configuration control command according to the configuration enabling signal and the configuration data, sending the configuration control command to the appointed FPGA through the selectMAP bus interface, generating a refreshing control command according to the refreshing enabling signal, sending the refreshing control command to the appointed FPGA through the selectMAP bus interface, reading the refreshing state of the FPGA and sending the refreshing state to the enabling control module.
2. The IP core for configuration and refresh control of the spaceborne SRAM type FPGA as claimed in claim 1, wherein the FPGA configuration file is Hamming encoded by an external processor, and is written into an external memory after a storage address and a length are specified by the external processor, and each FPGA corresponds to one FPGA configuration file.
3. The IP core of claim 1, wherein the configuration file read and status output module comprises an APB bus unit, an AXI bus unit, a DMA unit, and an address management unit; wherein the content of the first and second substances,
the APB bus unit is used for reading the FPGA configuration file, receiving an external processor instruction and sending the instruction to the enabling control module, and is also used for outputting the refreshing state of the FPGA to the outside;
the AXI bus unit to control a DMA unit;
the DMA unit is used for reading the FPGA configuration file under the control of the AXI bus unit;
and the address management unit is used for performing address accumulation on the DMA unit according to the read address accumulation enabling signal output by the configuration refreshing top module.
4. The IP core of claim 3, wherein the AXI bus unit operates in master mode, actively initiating read operations according to external processor instructions.
5. The IP core of claim 3, wherein the data storage and resolution module comprises a multiplexer, a buffer FIFO, a data signal synchronization unit and an ECC decoding unit; wherein the content of the first and second substances,
the multiplexer is used for selecting to read the FPGA configuration file from the APB bus unit or the DMA unit and sending the FPGA configuration file to the buffer FIFO;
the buffer FIFO is used for caching the FPGA configuration file;
the data signal synchronization unit is used for reading the FPGA configuration file from the buffer FIFO and sending the FPGA configuration file to the ECC decoding unit;
the ECC decoding unit is used for decoding the FPGA configuration file by adopting a Hamming code, and when no error or one-bit error occurs in decoding, the ECC decoding unit automatically corrects the decoding configuration data and then sends the decoded configuration data to the configuration refreshing top module; when two or more bits of errors occur during decoding, an interrupt notification is sent to an external processor.
6. The IP core of configuration and refresh control of the on-board SRAM-type FPGA of claim 5, wherein the enable control module comprises a frequency dividing unit, a reset synchronization unit, and a control register unit; wherein the content of the first and second substances,
the frequency dividing unit is used for setting a distribution coefficient according to the frequency of the input clock to realize the control of the refreshing speed;
the reset synchronization unit is used for receiving a reset signal for synchronization and sending the synchronized reset signal to the configuration file reading and state output module, the data storage and analysis module and the configuration refreshing top module;
the control register unit is used for storing the received processor instruction, the frequency division value, the DMA starting address, the DMA length, the DMA command, the refresh command, the type and the number of the FPGA to be refreshed and the refresh state; and the FPGA is also used for sending the refresh state of the FPGA to the APB bus unit.
7. The IP core of claim 6, wherein the control register unit comprises a FIFO input register, a frequency division configuration register, a DMA start address register, a DMA length register, a DMA command register, a refresh configuration register, and a refresh status register; wherein the content of the first and second substances,
the FIFO input register is used for storing the FPGA configuration data received from the APB bus unit;
the frequency division configuration register is used for storing a frequency division value, and the rate of the system clock divided by the 2-time frequency division value is the refresh clock;
the DMA starting address register is used for storing the starting address of DMA starting operation;
the DMA length register is used for storing the length of DMA starting operation;
the DMA command register is used for storing a starting mark, a stopping mark, an ending mark, a clearing mark, a bus idle mark and an FIFO effective mark;
the refresh command register is used for storing configuration enabling and refresh enabling;
the refreshing configuration register is used for storing the type of the FPGA to be refreshed through low 4 bits and storing the chip selection number of the FPGA to be refreshed through high 8bits, and the number of the FPGAs to be refreshed is less than or equal to 24;
and the refresh state register is used for storing the refresh state of the FPGA.
8. The IP core of configuration and refresh control of the on-board SRAM-type FPGA of claim 7, wherein the configuration refresh top-level module comprises a configuration refresh command generation unit and a configuration refresh execution unit; wherein the content of the first and second substances,
the configuration refreshing instruction generating unit is used for acquiring a configuration enabling signal from a refreshing command register of the control register, decoding the configuration enabling signal to generate a configuration instruction, sending the configuration instruction to the configuration refreshing execution unit, acquiring a refreshing enabling signal from a refreshing command register of the control register, decoding the refreshing enabling signal to generate a refreshing instruction, and sending the refreshing instruction to the configuration refreshing execution unit; the refreshing instruction comprises a single refreshing instruction and a circulating refreshing instruction;
the configuration refreshing execution unit is used for generating a configuration control command according to the configuration command and the configuration data decoded by the ECC decoding unit and outputting the configuration control command to the selectMAP bus, generating a refreshing control command according to the refreshing command and the FPGA configuration data decoded by the ECC decoding unit and outputting the refreshing control command to the selectMAP bus, reading the refreshing state of the FPGA and sending the refreshing state to the refreshing state register, and sending a read address accumulation enabling signal to the address management unit.
9. The IP core of claim 8, wherein the configuration refresh execution unit stops outputting the refresh clock when configuration or refresh is not completed and the buffer FIFO is empty, and continues outputting the refresh clock when the buffer FIFO is not empty.
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