RU2769562C1 - Solid-state information storage controller decoder - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention relates to computer technology and is intended to carry out the process of decoding digital information coming from several independent NAND flash memory chips in the controller equipment of non-mechanical storage devices based on NAND flash memory chips. A decoder of a solid-state data storage controller for decoding data from n NAND channels, containing a control unit that monitors the operation of the blocks included in the decoder, a channel controller consisting of n modules, each of which is connected to a specific NAND channel, a memory block for storing sectors containing independent memory modules, a decoder controller containing m decoder modules, where n>m, a decoder block containing m LDPC decoders, a unit for checksum calculation and data transfer to a recording unit and a unit for checksum calculation and data transfer to a host unit.

EFFECT: increase in the efficiency of the technical storage medium due to the uniform distribution of the load of the NAND flash memory included in it during the read operation.

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Description

The invention relates to microelectronics and is intended for use in circuit solutions and topologies of integrated microcircuits of memory controllers designed to control read and write operations of multichannel flash memory microcircuits intended for long-term non-volatile data storage (NAND).

Solid State Drives (SSDs or SSDs) are attracting the attention of developers as memory systems equipped with flash memory (flash EEPROM) as external drives used by computing systems.

Flash memory has advantages such as high data transfer speed, as well as reduced weight compared to magnetic disk.

A typical SSD includes several flash memory chips, a controller that controls the read and write of the respective flash memory chips in response to a request from a host device such as a desktop computer, a buffer memory to handle the data transfer process between the respective flash memory chips, and host device, power management circuits and interface to the host device.

When designing a solid state drive, including drives in which the proposed invention can be used, as a rule, a multilayer implementation is used, in which, to increase the specific memory capacity, several memory chip chips are used, for example, in the form of a multilayer assembly, while while the area of the pads for the controller outputs and for the mounting pads is limited.

When using a synchronous controller, data read from memory can be latched and output in a low load state (with few data buffers); however, in a high load state (with a large number of buffers filled with read data), data read from memory may not be latched or output due to data latency caused by the time spent arbitrating access to chips in assemblies and individual chips ( housings) on ONFI (TOGGLE) buses.

To decode information coming from channels, hardware decoders are used. Modern TNIs use LDPC decoders. Distinctive features of LDPC Decoders are:

- high throughput;

- small area / low power consumption.

In the above multilayer product, dedicated data, address, and control buses, as well as power buses, can be used separately for each module, which are located inside the chip. The load of the respective buses increases with the increase in the number of memory chips, for example, in a multilayer assembly, and as the load of the corresponding signal lines increases, the delay of the I / O signals increases due to the delays caused by the increase in capacitance and resistance of the data lines themselves. In addition, the throughput of the physical interface of the Host-TNI (for example, PCIe 3.0) of modern TNIs significantly exceeds the bandwidth of a separate NAND flash memory chip. In this regard, TNI uses several NAND-flash memory chips combined into so-called channels. The Write and Read procedures, in this case, are performed in parallel on several channels. A single channel usually contains from 1 to 8 NAND flash memory chips. The use of a single data transmission channel is practically impractical, since the data transmission rate is significantly limited.

The disadvantage of the known decoders used in TNI is the lack of optimization of information processing performance, due to the impossibility of evenly distributing the workload of several decoders not tied to LDPC memory chips when working with several NAND flash memory chips.

For example, US Pat.

A significant disadvantage of this solution is the need to use a common address space to store the contents of the cells, as well as the use of one channel and one decoder to transmit data to the host. This configuration can only improve processing speed when multiple controllers are used in parallel.

The use of channels dedicated to groups of cells for processing data increases speed, but can reduce stability when using all channels at the same time, due to increased power consumption and increased capacitive and resistive delays. Increased power consumption can lead to premature failure of storage media.

Thus, in the prior art there is a need to optimize the distribution of channel load when performing write-read operations, taking into account the possibility of errors, as well as the need to erase data in cells before performing write operations, when performing these operations on physical devices. At the same time, several parallel functioning channels of NAND flash memory must be optimized in such a way as to ensure the maximum possible speed of reading and writing information.

Additionally, one TNI controller chip in various TNI versions should provide universal Host interaction with various NAND-flash memory chipsets. Eliminating the shortcomings of the prior art is the object of the present invention.

The technical result achieved in the implementation of the invention is the solution of the above problems, the elimination of the shortcomings of the prior art and the increase in the efficiency of the TNI due to the uniform distribution of the workload of the NAND flash memory included in it during read and write operations, the possibility of parallel execution of the following service operations, including including garbage collection and cell validation, improving the reliability of TNI, which uses the proposed invention.

The claimed result is ensured due to the fact that when performing hardware decoding of the contents of a solid state drive of information containing n> 1 independent memory blocks, n hardware channels for writing and reading data and m < n, independent hardware decoders are allocated that implement the same block decoding process data, where the data value from each of the blocks is transmitted through one of the write-read channels to one of the independent allocated memory blocks, with the formation, before the transfer is completed, of the channel busy signal involved in the process of writing or reading data,

when a request is received from an external system to read data from a logical sector of data, the address of the block corresponding to the logical sector is determined, and, after allocating the address of external memory intended for writing the value of the logical sector, the process of reading data on request is initialized, for which a physical block is determined that stores data of the requested logical data sector, allocate an independent physical block of directly addressable memory to write the value of the block, if there is a free channel, select and occupy a free channel, allocate a free hardware decoder, form a request to transfer data from a specific physical block to the allocated memory using a free channel from a particular physical block, where the data contains the data read from the block and the checksum, and

A. determine the correctness of the checksum using the selected hardware decoder, which has direct access to the allocated memory containing the data value and the checksum,

B. based on the results of the completion of the calculation and verification of the checksum, return the result of reading to the external system and release the dedicated channel.

If the checksum does not match the calculated checksum, before performing operation B, in a particular case, the implementation of the method changes the physical parameters of reading data from the block and re-reads from the block using the channel, after which operation A is repeated, while in the particular case, set in advance a given number of physical parameters of data reading, and if the checksums do not match after enumeration of all the given physical parameters of data reading, they return an error code and mark the side as not valid.

In a particular case, the hardware calculation of the checksum string using a dedicated decoder is used, and the subsequent hardware comparison of the calculated checksum string with the checksum value using the logic of the dedicated decoder is used.

In this case, the hardware method for calculating the checksum can be specified in matrix form using an independent rewritable non-volatile memory. In a particular case, the method is implemented by hardware controllers, in which m is equal to the nearest integer from n multiplied by 0.6 - 0.8.

In another particular case, when there is a free channel and no requests, garbage collection occurs, and the controller can be made to initiate and perform garbage collection when there is no request for a read.

In addition, 11 soft values can be used as physical parameters for reading data, using a soft value generating block containing at least two independent soft value generating modules, each of which is used to change soft values and write them to blocks. external memory allocated to the respective memory blocks, so that the generated soft values can be used by the respective decoder when decoding the data of the respective memory block.

The presence of several modules in the memory block for storing sectors, in the controller of decoders and LDPC decoders, allows the control unit of the decoder of the TNI controller to ensure even distribution of the load of the NAND flash memory included in it during a read operation.

All channel controller modules and memory modules can be made independent, and therefore all n channels can simultaneously transmit data in any chosen direction.

In one embodiment, the decoder of the controller of the solid-state information storage device, further comprising a soft value generation unit having at least two independent soft value generation modules, each of which serves to remember in which three memory modules of the memory unit for storing sectors data is stored sector, can be connected by two-way communication for control commands with the control unit and the decoder controller.

Non-mechanical storage devices based on NAND flash memory chips (hereinafter referred to as a solid state information drive - SIT) use several separate NAND flash memory chips. They are designed to store user data.

Modern TNIs interact with the host through specialized logical and physical interfaces. Modern TNIs use a PCIe 3.0 physical interface and a NVMe logical interface. At the same time, NAND flash memory chips use other physical and logical interfaces, often different from different manufacturers.

The TNI controller, in particular, provides the following operations:

- Write operation. This operation moves user data from the Host through the TNI controller to the NAND flash chipset. At the same time, in the process of data processing by the TNI controller, the data is subjected to the procedure of noise-immune coding. The noise-correcting coding procedure is performed using hardware blocks - encoders. The TNI controller may include several encoders.

- Read operation. In this operation, data is extracted from the elements of the NAND-flash chipset, further processed by the TNI controller and transmitted to the host. When processed by the TNI controller, the data is decoded using hardware units - decoders. The TNI controller may include several Decoders. When decoding data, possible errors that have arisen in the process of recording, storing, reading and transmitting information within the TNI are corrected.

Standard logical interfaces for interaction with NAND flash memory chips are ONFI and Toggle interfaces. In order for the TNI Controller to support work with NAND flash memory chips from various manufacturers, the TNI Controller includes specialized hardware blocks - NAND Channels, which convert various interfaces of NAND flash memory chips to a single Channel logical interface.

Typically, HPS controllers are designed so that on their basis it is possible to manufacture various HPS options that differ in volume and speed. This is often achieved by enabling/disabling some of the Channels.

The figure shows a block diagram of the decoding unit, where the numbers show: 1 - channel controller, 2 - control unit, 3 - memory block or external memory for intermediate storage of sector data, as well as service information related to sectors, for example, soft values, used for decoding. Position 4 denotes a soft value generation unit, 5 is a decoder controller or a central control device designed to coordinate the operation of individual units, including the recording unit, as well as to control data exchange interfaces with the host. Position 6 indicates the decoder block, 7 is the block for calculating the checksum when writing and transmitting data to the recording block, 8 is the block for calculating the checksum of the read data and transmitting the checksum to the host block, 9 is block A or NAND channels, 10 is block B or flash block , 10 is the C block or write block and 11 is the D block or read block.

In the figure, narrow arrows indicate control commands, and wide arrows indicate channels or data transfer processes.

Next, the invention will be described in detail with an example of its implementation. Symbols written in italics in Latin refer to hardware interfaces for data exchange and interpret logical parameters, the values of which are determined by the parameters of the signals generated in the corresponding electrical circuits of the hardware units. The designations made in capital Latin letters characterize the data blocks processed and formed in the process of interaction of the blocks of the device that implements the proposed method.

The operation of the TNI controller decoder can be characterized as the following task: given n - NAND Channels that supply data for decoding, and m - Decoders that decode this data, where n > m . The performance of n Channels is approximately equal to the performance of m Decoders. It is necessary to ensure uninterrupted operation of the Decoders so that all Channels are served evenly.

Block A represents the NAND Controllers. From it, the data enters the decoding unit (TNI controller unit).

Block B governs allnchannels and transmits to the Decoding Unit information about the presence of data on the Channels for decoding. In addition, Block B generates all the necessary commands for the NAND Controllers.

Let's say n = 8. The portion of data intended for decoding is equal to the length of the code word and is called a sector. There are 2 decoding modes: hard and soft. With hard decoding, the sector is read from the NAND controller once, with soft decoding, the sector is read 3 times with different read thresholds, and due to this, soft LLR values are formed. For each of the Channels, block B sends to the Decoding Block information about the sector, consisting of the following fields: a ready_to_decode flag, which says that there is a sector on the Channel to be decoded; psa is the physical address of the sector to be decoded; from_gc - flag indicating that the sector comes from the garbage collector; cur_bit_num - the number that says which time the sector is read, can take the values 0, 1, or 2, depending on whether this sector is read for the first, second or third time; last_bit_num will be 2 if it is a soft decode and 0 if it is a hard decode.

Block C writes back sectors from the garbage collector to the disk.

Block D sends the read sectors to the Host.

In the hard decoding mode, block 3 is used, consisting of k independent memory modules, each of which can store 1 sector. In our case, k = 18. Each memory module can be free or occupied. Each memory module has a mem_free flag, which says that the memory module is free, and exposes it to control block 2.

Block 1 consists of n modules, each serving its own channel. Each of these modules transmits information about its channel to the control unit 2 . If the control block 2 detects the ready_to_decode flags (ready to decode), i.e. if there are channels that want to access the decoder, and if there are free memory modules, then the control unit selects one channel and one memory module in a circle and associates them with each other. The memory module remembers and stores information about the sector from the channel allocated to it. After that, the selected channel module starts transferring data from NAND to the dedicated memory module. Since the width of the memory element is wider than the width of the data coming from the NAND, the Channel module first accumulates the data to the desired width, and only then writes to the memory. All Channel 2 modules and memory modules are independent, so all n Channels can transfer data at the same time. When the sector-to-memory swap is completed, the channel module is freed and information about the completion of the swap is passed to block B, at the same time the memory module raises the ready flag, indicating that the sector is stored in this memory module ready for decoding.

Block 5 contains m decoder modules, each of which serves its own decoder. Block 6 contains m independent decoders, for example, LDPC decoders (decoders with low-density parity-check or low-density parity-check code). In our case m =2. A decoder can be free or busy. The Decoder Module passes the state of its Decoder to the control block via the dec_free flag (free decoder). If the control unit 2 detects a sector in the memory ready for decoding and a free decoder, then it selects in a cycle the ready memory module and the free decoder module and links them to each other. The decoder module stores the sector information from the memory module allocated to it. The selected decoder module starts the decoding process on its decoder. During the decoding process, the Decoder requests the initial values of the LLR (likelihood ratio test) from the decoder module in a convenient order. The decoder module extracts information from the memory module allocated to it, forms LLRs and passes them to the decoder. After loading all the initial LLR values, the decoder reports this to its decoder module, and the decoder module transfers this information to the memory module allocated to it, after which decoding continues, and the corresponding memory module is released with the corresponding flag set.

The response of each decoder is the decoded sector, i.e. sector with corrected errors, and this response is formed in a special response buffer. Each decoder may have two such buffers. If the decoding was unsuccessful, then information about the unsuccessful decoding is transmitted from the decoder module through the control block to the corresponding channel from which the sector arrived. If the decoding is successful and a decoded sector is formed in the first response buffer, the decoder switches to the second response buffer and starts decoding a new sector, generating a response in the second sector. In this case, a flag is set indicating that there is a ready decoded sector in the response buffer and it needs to be processed. If there is a decoded sector from the garbage collector, then this flag is set to block 7, otherwise it is set to block 8.

Block 7 , having found the decoded sector, in the presence of free memory, downloads this sector into memory. Simultaneously with the download, module 7 calculates the checksum. After downloading the information part of the code word, a checksum is formed. The resulting checksum is compared with the checksum contained in the metadata of the given sector (a certain number of the first bits of the codeword). If these checksums match, then it is considered that the word was decoded correctly, and the sector loaded into the memory of block 7 is transferred to the recording block C. Information about successful decoding is sent from the decoder module through the control block to the corresponding channel from which this sector came. After unloading the sector into the memory of block 7, the corresponding decoder response buffer becomes free. If the checksums do not match, then decoding is considered unsuccessful and information about unsuccessful decoding is sent from the decoder module through the control block to the corresponding Channel from which this sector came.

Block 8 , having found the decoded sector, refers to the host block D and asks to allocate memory for downloading the sector. After host block D allocates this memory, block 8 starts pumping this sector from the response buffer into the allocated memory. In this case, only the information part of the code word is downloaded. Simultaneously with the download, module 8 calculates the checksum. After downloading the information part of the code word, the checksum is formed. The resulting checksum is compared with the checksum contained in the sector's metadata. If these checksums match, then the word is considered to be decoded correctly. Information about successful decoding is transmitted from the decoder module through the control block to the corresponding Channel from which this sector came. After the sector has been swapped into the allocated memory of the host block D, the corresponding Decoder response buffer becomes free. If the checksums do not match, then decoding is considered unsuccessful and information about unsuccessful decoding is sent from the decoder module through the control block to the corresponding Channel from which this sector came.

If the Decoder has completed decoding, but sees that the second response buffer has not yet become free, then it enters the idle state, and exits this state only when this response buffer is free. A decoder that is idle is considered busy. Thus, a Decoder is considered free if it is not in the process of decoding and has a free response buffer.

Block 4 is used in soft decoding mode. This block consists of q independent soft value generating modules, each of which is used to remember in which three memory modules the data of its sector was stored. In our case q =2. Each of these modules can be free or busy and reports its status to control block 2 using the soft_free flag.

If the control block 2 sees that there are Channels that have last_bit_num=2 (i.e. this Channel wants to perform soft decoding), there is a free soft value generation module and a free memory module, then the control block selects one of the Channel modules in a circle, which want to perform soft decoding selects one of the free soft value generators and one of the free memory modules, and associates the selected soft value generator with the selected Channel. The soft value generation module remembers information about the sector of the selected Channel and the number of the selected memory module. After that, the process of transferring data from the Channel to the memory module begins. Upon completion of the transfer, the Channel turns to NAND for the next reading of this sector with new threshold values, and after this reading is completed, the ready_to_decode sector flag is raised again, but cur_bit_num = 1. The control block allocates a memory module to this Channel in priority order, which is stored in a dedicated module for the formation of soft values. After that, the sector is again downloaded from the Channel into memory. And upon completion of the download, the next sector value is requested and, when it is ready, the ready_to_decode flag is raised with cur_bit_num = 2. The control block again allocates a memory module to this Channel in priority order, which is stored in the dedicated soft value generation module. After that, the sector is again downloaded from the Channel into memory. And upon completion of the third download, the Channel module is considered free, and the selected soft value generation module raises the ready flag, which is passed to the control block 2.

The control block, seeing the ready flag from the soft value generation module, waits for the Decoder to become free and connects the freed decoder module with the ready soft value generation module.

The decoder module stores the sector information from the soft value generating module allocated to it. The selected Decoder Module starts the decoding process on its Decoder. During the decoding process, the Decoder requests the initial LLR values from the decoder module in the order convenient for it. To form the initial LLR values, the decoder module extracts information from three memory modules at once, corresponding to the selected soft value generation module. After loading all the initial LLR values, the Decoder informs its decoder module about this, and the decoder module passes this information to the soft value generation module allocated to it, after which this memory soft value generation module becomes free and all three memory modules corresponding to this soft value generation module become free. values.

The further decoding process is completely similar to the hard decoding mode.

As the Host mentioned in the description, the control link higher in the hierarchy is meant. It can be a microprocessor, server, etc. device.

The following describes the order of execution of the main operations implemented by the Decoding block.

Operations Implemented by the Decode Block

Inclusion

When the device is turned on, the Decoding Block receives an INIT signal, which brings the module to its initial state. In addition, after turning on the device, the module receives signals

1) WORD_LEN - the number of slices of sector data coming from the channel, minus 1;

2) COL_NUM - equal to the number of columns in the LDPC matrix minus 1;

3) SHORTENNING_SHIFT - equal to the number of padding bits (good zeros) in the first column of the matrix;

4) PUNCTURING_SHIFT - equal to the number of non-punctured bits in the first punctured column of the matrix;

5) BEG_ADR - address in the LDPC command memory of the decoder, where the processing program starts, of the current LDPC matrix; if only one matrix is loaded into the instruction memory, then this signal is equal to 0;

6) BEG2_ADR - address in the LDPC command memory of the decoder, where the program for processing the second or more iterations begins; the fact is that during the second and more iterations, the first few commands are not used; as a rule, the number of unused commands is 7, and accordingly BEG2_ADR = BEG_ADR + 7;

7) LAST_ADR - address of the last instruction in the instruction memory.

8) COL_INFO_BEG_ADR - address of the beginning of the block related to the current LDPC matrix and containing information about non-empty cells of each of their columns; in case the decoder serves only one matrix, COL_INFO_BEG_ADR = 0;

9) LAST_ROW_NUM - number of rows in the current LDPC matrix minus 1;

10) LAST_EDGE_NUM - the number of non-empty cells in the current LDPC matrix minus 1;

11) SECOND_V2C_MEM_COL_BEG - number of columns in the first half of the current LDPC matrix; Since the LDPC decoder uses single-port 1RW memory, which cannot be written and read at the same time, to ensure smooth operation, the matrix is divided into two parts, and each part is serviced by its own calculator;

12) LAST_ITER_NUM - maximum number of iterations minus 1.

All the parameters listed above are automatically calculated from the LDPC matrix using a special initializing program. In particular, a calculation schedule is made during the decoding process, and this schedule is stored in the instruction memory. Therefore, if the instruction memory is not ROM, then the schedule must be loaded into the instruction memory of each of the decoders before the INIT signal is issued.

Shutdown

When the device is turned off, the signal SWITCH_OFF_MODE is received. This signal is held all the time while the device is turned off. During the device shutdown, the following actions are performed:

1) Stop decoding sectors for the host.

2) Memory blocks occupied by sectors for the host are released.

3) Soft value generators are released if they generate a soft value for the sector for the host.

4) After all decoders and all memory modules report that they are free, and if the EVERYTHING_IS_READ signal is raised (this means that there are no pages in the flash block that still need to be decoded), then the module raises the NO_MORE_SECTORS_FROM_GC signal (which means that no more sectors will come from the garbage collector) and passes it to the write block.

Interaction with the flash block

Interaction with channels (or rather with Flash Block) occurs as follows:

1) The Decode Block sends the READY_TO_GET_HARD and READY_TO_GET_SOFT signals to the flash block, indicating that it can accept a sector for decoding using hard values and soft values, respectively. The first signal actually says that the Decoding Block has a place in memory to load one sector, and the second signal says that, in addition, the Decoding Block has a free module for generating soft values.

2) With the SECTOR_READY signal, the channel indicates that it has a sector to decode. Each channel has its own SECTOR_READY signal. Along with this signal come signals

a) HARD - indicator that hard decoding is expected. Actually HARD = (BIT_NUM == 0) && (BIT_NUM_TO_DECODE == 0).

b) BIT_NUM - soft bit number. If 0, then it is a hard beat, 1 is the first soft beat, and so on.

c) BIT_NUM_TO_DECODE - how many soft bits are planned to be loaded minus 1. If BIT_NUM < BIT_NUM_TO_DECODE, then we simply load the page into the module's memory and decode it later. If BIT_NUM = BIT_NUM_TO_DECODE, then after loading the sector, we decode the sector, taking into account all previously loaded bits.

d) FROM_GC - an indicator that the sector is from the garbage collector.

e) PPA - the physical address of the page. Used only if the sector is from a garbage collector.

f) SECTOR_NUM - sector number on the page. Used only if the sector is from a garbage collector.

g) TEMPERATURE - sector temperature. Used only if the sector is from a garbage collector.

h) FROM_REPAIR_TO_DECODE - the channel says that the page being read is from the super-block restorer.

i) REPAIR_PARITY_TO_DECODE - the channel says that the page being read from the super-block restorer belongs to the check way.

3) After receiving the SECTOR_READY signals from the channels, the Decoding Block selects one of the channels in a circle and allows it to transfer data using the READY_TO_RECEIVE_DATA signal. When a READY_TO_RECEIVE_DATA signal is received by one of the channels, the SECTOR_READY signal for this channel is omitted. The READY_TO_RECEIVE_DATA signal is held until the first chunk of data arrives from the NAND controller.

4) The indicator of data receipt from NAND controllers are DATA_IN_PUSH signals. The data itself comes in through the DATA_IN inputs.

5) After receiving the entire sector from the NAND controller, the Decoding Block sends the DATA_TO_DECODE_FINISHED signal to the flash block, which is needed to free the channel for other operations.

6) At the time of the first arrival of the READY_TO_RECEIVE_DATA signal, the flash block may cancel the data transfer to the decoder using the CANCEL_READ signal. It is not enough to simply omit the SECTOR_READY signal, because the response of the Decoding Block module to the signal is delayed by 1 cycle, and the CANCEL_READ signal allows you to remove the contradictions that may arise due to this delay. The CANCEL_READ signal can appear in two cases:

a) when the device is turned off, if the transmitted data is not a re-read of the garbage collector;

b) if, in order to resolve stalemate situations, it is necessary to urgently skip the write operation to this channel, while canceling the read operation.

7) Upon completion of decoding and CRC check, the Decoding Unit sends the flash block, or rather the corresponding channels, information about the success of the decoding using the signals DECODE_SUCCESS (decoding completed successfully) and DECODE_FAIL (decoding completed unsuccessfully). Together with these signals, signals are received:

a) PPA_TO_CHANNEL - physical address of the page;

b) SECTOR_NUM_TO_CHANNEL - number of decoded or undecoded sector on the page.

c) FROM_GC_TO_CHANNEL - an indicator that the decoded or undecoded sector was from the garbage collector.

d) FROM_REPAIR_TO_CHANNEL - says that the decoded or undecoded sector is from the restorer. In case of unsuccessful decoding, this information is used to form a reread, and in case of successful decoding, it reduces the counter of processed sectors of the victim block.

8) If some decoder is idle because it cannot reset the sector from the garbage collector to the write block, then the Decoding Block sends the DECODER_IDLE signal to the flash block, which informs about the occurrence of a stalemate and the need to force the writing of wordlines to NAND controllers.

Interaction with the Recorder

Interaction with the record block is carried out as follows:

1) After the decoders have decoded the sector, it is transmitted to the checksum calculation (CRC) block.

2) At the moment when the checksum is calculated and if the sector is not from the check wave, then the FIND_FOR_GC flag is raised, which asks the write block to find out if there is a sector with the LSA_FOR_GC address in its memory.

3) On the next cycle, the response from the record block comes in the form of a NO_GC_SECTOR_NEEDED signal.

4) If NO_GC_SECTOR_NEEDED = 1, then this means that there is already a sector with the LSA_FOR_GC address in the memory of the write block, and, therefore, it is more up-to-date, and therefore this decoded sector is not needed. The same NO_GC_SECTOR_NEEDED signal is sent to the decoder, and the decoder releases the memory with the given sector data. In this case, the CRC_CALC_FOR_GC_SECTOR module stops processing this sector.

5) If NO_GC_SECTOR_NEEDED = 0 on the next cycle after the FIND_FOR_GC signal, or if the FIND_FOR_GC signal was not sent (the sector was from the check wave), then this means that there is no sector with the LSA_FOR_GC address in the write block memory.

a) Then if the checksum does not agree, then the decoding is considered unsuccessful, which is reported to the corresponding channel using the DECODE_FAIL signal that we described earlier.

b) If the checksum has converged, then the decoding is considered successful, which is reported to the corresponding channel using the DECODE_SUCCESS signal that we described earlier. As a result, the unloading of the sector parity bits continues.

6) In case 5 b), the CRC_CALC_FOR_GC_SECTOR module asks the writer for a place to write the sector using the GET_SECTOR_FOR_GC signal. At the same time, it also transmits the TEMPERATURE_FOR_GC signal, telling what temperature the wordline needs. If the superblock_repair synthesis parameter is enabled, then the following signals are also set:

a) WB_REPAIR_SECTOR - co-interaction with the record block that the sector comes from the super-block restorer;

b) WB_REPAIR_PARITY - co-operation to the record block, that the incoming sector is from the check wave;

c) WB_REPAIR_SEC_NUM - sector number in the incoming sector wordline.

7) In response, the writer issues a SET_SECTOR_FOR_GC signal. As a result, the GET_SECTOR_FOR_GC signal is omitted, and you can start writing a sector from the internal memory of the Decode Unit to the write unit's memory.

8) From this moment, the process of uploading data from the internal memory of the Decoding Block module to the memory of the recording block begins. This writing occurs with the BEFORE_WRITE_FROM_GC, WRITE_ADR_FROM_GC, and WRITE_DATA_FROM_GC signals. Moreover, the BEFORE_WRITE_FROM_GC and WRITE_ADR_FROM_GC signals arrive simultaneously, while the WRITE_DATA_FROM_GC signal appears a clock later. The BEFORE_WRITE_FROM_GC signals must arrive at strictly defined clock cycles, which occur once every 4 clock cycles. Those. WRITE_DATA_FROM_GC must occur on TIME_TO_WRITE_DATA_TO_WRITE_BLOCK clocks.

9) Immediately after the start of recording, the PUSH_INFO_FROM_GC flag is raised in the recording block, which loads the sector information transmitted via the LSA_FROM_GC_OUT, GEN_PPA_OUT, CRC_FROM_GC_OUT, SYNC_PACKAGE_FROM_GC_OUT signals to the registers of the recording block.

10) When the sector is unloaded, along with the last BEFORE_WRITE_FROM_GC signal, the BEFORE_LAST_WRITE_FROM_GC signal arrives, which informs the writer that the sector loading is complete.

Interaction with the Host Block

Interaction with the host block is carried out as follows:

1) The Host Block sends the TIME_TO_WRITE_DATA_ TO_WRITE_BLOCK_3 signal to the Decode Block module, with which the Decode Block generates BEFORE_WRITE_FROM_GC signals.

2) After decoding the sector for the host, the Decode Block sends a GET_SECTOR_FOR_HOST signal, which means a request to allocate memory inside the host block for unloading the decoded sector for the host.

3) In response, the host block sends the SET_SECTOR_FOR_HOST signal, which means that the memory is allocated, and the sector can be unloaded into the host block.

4) From this moment, the process of uploading data from the internal memory of the Decoding Unit module to the memory of the host unit begins. This writing occurs with the WRITE_FOR_HOST, WRITE_ADR_FOR_HOST, and WRITE_DATA_FOR_HOST signals, which arrive at the same time.

5) Simultaneously with the unloading of the sector, the CRC is calculated, and at the moment when the information part is loaded, the HOST_DATA_LOADED signal appears, and simultaneously with this signal, the HOST_CRC_ERROR signal may appear, which means that the checksum did not converge. In this case, the DECODE_FAIL signal is sent to the corresponding channel of the flash block, and the host block deletes the loaded sector from its memory. If, along with the HOST_DATA_LOADED signal, the HOST_CRC_ERROR signal did not come, then the decoding is successful and the DECODE_SUCCESS signal is sent to the corresponding channel of the flash block, and the host block receives the loaded sector and this sector will be transferred to the host in the future.

6) Together with the HOST_DATA_LOADED signal, the host block receives the LSA_FOR_HOST_OUT signals (used to send to the host and SYNC_PACKAGE_ FOR_HOST_OUT (used to decrypt the sector.

Claims (12)

1. A method for hardware acceleration of decoding the contents of a solid state drive of information, which consists in the fact that for a solid state drive of information containing n> 1 independent memory blocks, n hardware channels for writing and reading data and m < n independent hardware decoders are allocated that implement the same the process of decoding data blocks, where the data value from each of the blocks is transmitted through one of the write-read channels to one of the independent allocated memory blocks, with the formation, before the completion of the transfer, of the channel busy signal involved in the process of writing or reading data, upon receipt of a request from an external system to read the data of the logical sector of data, the address of the block corresponding to the logical sector is determined, and after allocating the address of the external memory intended for writing the value of the logical sector, the process of reading data on request is initialized, for which the physical block is determined that stores the data of the requested logical sector of data, allocate an independent physical block of directly addressable memory to write the value of the block, if there is a free channel, select and occupy a free channel, allocate a free hardware decoder, form a request to transfer data from a certain physical block to the allocated memory using a free channel from a certain physical block, where the data contains the data read from the block and the checksum, and A. determine the correctness of the checksum using the selected hardware decoder, which has direct access to the allocated memory containing the data value and the checksum, B. based on the results of the completion of the calculation and verification of the checksum, the result of reading is returned to the external system and the dedicated channel is released. 2. The method according to claim 1, characterized in that if the checksum does not match the calculated checksum, before performing operation B, the physical parameters of reading data from the block are changed and re-read from the block using the channel, after which operation A is repeated. 3. The method according to claim 2, characterized in that a predetermined number of physical parameters of data reading is set, and if the checksums do not match, after enumeration of all the given physical parameters of data reading, an error code is returned and the side is marked as invalid. 4. The method according to claim 1, characterized in that the hardware calculation of the checksum string using a dedicated decoder and the subsequent hardware comparison of the calculated checksum string with the checksum value using the logic of the dedicated decoder are used. 5. The method according to claim 1, characterized in that the hardware method for calculating the checksum is specified in matrix form using an independent rewritable non-volatile memory. 6. The method according to claim 1, characterized in that in the presence of a free channel and no requests, garbage collection is performed. 7. The method according to claim 1, characterized in that the controller is initiating and performing garbage collection in the absence of a read request. 8. The method according to claim 1, characterized in that the hardware channels for writing and reading data are dynamically linked to memory blocks. 9. The method according to claim 2, characterized in that soft values are used as physical parameters for reading data, while using a soft value generating unit containing at least two independent soft value generating modules, each of which serves to change soft values and writing them to external memory blocks allocated to the corresponding memory blocks, with the possibility of using the generated soft values by the corresponding decoder when decoding the data of the corresponding memory block.

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