CN101315812A - FLASH memory on-line programming method based on parallel port - Google Patents
FLASH memory on-line programming method based on parallel port Download PDFInfo
- Publication number
- CN101315812A CN101315812A CNA2008100348599A CN200810034859A CN101315812A CN 101315812 A CN101315812 A CN 101315812A CN A2008100348599 A CNA2008100348599 A CN A2008100348599A CN 200810034859 A CN200810034859 A CN 200810034859A CN 101315812 A CN101315812 A CN 101315812A
- Authority
- CN
- China
- Prior art keywords
- data
- parallel port
- flash
- fifo
- programming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention provides an online programming method for a FLASH memory based on a parallel port in the embedded system application field. In the method, a data communication protocol established based on a special parallel port base pin definition sends data by the parallel port, receives the data sent by a PC end by using asynchronous FIFO, writes in the FLASH memory after format conversion under the control of a state machine, and carries out verification to the data. The method of the invention is characterized by high and adjustable programming speed, can randomly revise the programming content online, does not need the participation of a CPU in work quickly, can select self-matching model with wide application range, and is especially applicable to the development stage of the embedded system.
Description
Technical field
The present invention relates to a kind of online programming method of embedded system application, relate in particular to a kind of FLASH memory on-line programming method that is applicable to embedded system based on the parallel port.
Background technology
Along with the develop rapidly of large scale integrated circuit and semiconductor technology, the appearance of embedded system and development have caused the dramatic change of microelectronic, and have become the main flow and the trend of IC design.Wherein, the kernel of different frameworks such as MIPS or ARM is widely used as the main flow processor of present embedded system.In embedded system is used, often need one or multibank memory to deposit some necessary bootstrap routines, fixed function module and data form commonly used etc.In order to realize and to finish this function, based on the consideration of demands such as capacity and practical application, the outer FLASH storer of present more employing sheet replaces ROM storer in the original sheet.
At present, adopt special-purpose programmable device to carry out off-line programing mostly to the programming of FLASH storer, but the shortcoming of this off-line programing method is very obvious: i.e. programming trouble, it can not carry out online modification arbitrarily to the content of FLASH.Therefore also develop some and be applicable to the method for the online programming of FLASH storer, the online programming method of FLASH storer commonly used, these methods comprise: assist the systems programming (ISP) carried out by CPU; Utilization is such as the assistance programming of carrying out the FLASH storer at board test ICT emulator or the like miscellaneous equipment; By being configured programming such as some standard interface visit FLASH storeies such as JTAG or serial ports.The method of finishing systems programming by CPU assistance is simply suitable, but requires that mature C PU device must be arranged in the system; Adopt the method for emulator then to need additionally to buy emulator, increased cost of development; The JTAG method is a kind of comparatively widely method of current application, but requires all devices between FLASH memory device and the JTAG load ports all to support the boundary scan agreement.
Find through literature search prior art, Chinese patent application number is 02124004.3, patent name is " based on the FLASH device online programming method of boundary scan technique ", this Patent publish a kind of configuration programmed method based on JTAG, its core concept is big non-boundary scanning Logic Cluster of structure, comprise boundary scanning device and non-boundary scanning device, and ignored the influence of non-boundary scanning device, directly set up the annexation of FLASH device and boundary-scan port.Thereby solved the problem of the non-boundary scanning that exists between boundary scanning device and the FLASH device bunch.But this method might exist following point: the primary stage that is difficult to be applied to the processor design; Need the support of JTAG loader to finish the conversion of data layout; Need hardware environment familiar and that grasp on the plate to construct complete JTAG daisy chain; Can't regulate the program speed of FLASH storer.Obviously, this technology is had relatively high expectations in actual applications, uses comparatively trouble.
Summary of the invention
The present invention is directed to the deficiency and the shortcoming of above-mentioned technology, a kind of FLASH memory on-line programming method based on the parallel port has been proposed, it is fast and program speed is adjustable, can be online any modification programming content, do not need CPU to participate in work, can mate model certainly and select advantage of wide range of application that this method has program speed, is specially adapted to the development phase of embedded system.
The present invention is achieved by the following technical solutions:
FLASH memory on-line programming method based on the parallel port involved in the present invention, data communication protocol based on the foundation of special-purpose parallel port pin definitions, send data by the parallel port, utilize asynchronous FIFO to receive the data that transmit from the PC end, and under the control of state machine, write the FLASH storer, the line data verification of going forward side by side through format conversion.
Said method of the present invention comprises three steps, promptly sends and be applied to the Data Receiving of buffer interface part and target devices based on the data of the general parallel port of PC, and for to guarantee the data check that data accuracy carries out, wherein:
Described data sending step based on the general parallel port of PC comprises:
Based on the definition of online programming FLASH dedicated pin, set up new parallel port transmitting-receiving communication protocol;
Visit the general-purpose register of PC parallel port, obtain the state of parallel port signal; And,
Response parallel port signal condition, the adaptive speed adjustment is written to the data that local file read in the data register of general parallel port in good time, and sends with the basic format of 8 bit wides;
The described Data Receiving step that is applied to buffer interface part and target devices comprises:
The status mechanism of response data flow process, the clock on the Target Board is accepted in the self-adaptation adjustment, and adopts the buffering of asynchronous FIFO as high-speed data, receives the data that the parallel port sends in real time; And,
Certainly the coupling model of FLASH storer detects, and realizes the basic conversion of data layout, and the data after the conversion are write the target devices of required programming, i.e. FLASH storer;
Described data check step comprises:
Data in the FLASH storer are read back into PC; And,
The data and the PC local data that read back are compared the data of correcting a mistake.
The objective of the invention is to utilize the PC parallel port to realize the online programming function of FLASH storer, need to determine the definition of general parallel port pin thus.The present invention can adopt the general parallel port that is equal to or greater than 25 pins to realize as the PC parallel port, and each of definite parallel port pin is self-defined, in order to satisfy configuration FLASH storer, to detect the function needs of FLASH memory state and data transmit-receive programming.
The parallel port pin definitions that is exclusively used in PC parallel port online programming FLASH storer comprises:
The data transmit-receive pin is used to realize the link effect of swap data between PC parallel port and the receiving target device (that is FLASH storer); Among the present invention, the parallel port sends data owner and will be used in the process to the FLASH programming, receives the data that data then are used for reading FLASH and carries out in the process of data check; Send The data 8bit width form parallel mode, and receive the quantity that data are subject to pin, adopt the parallel mode of 2bit;
The state-detection pin is used for the state that the PC end detects Target Board; Whether the online programming system detects current operation and is finished, and can enter next operation, and corresponding detection signal is BUSY; In order to realize fast data buffer, avoid data to cover or lose, system has adopted two asynchronous FIFO to be respectively applied in the process of read and write FLASH; Whether asynchronous FIFO is full (FULL) or empty (EMPTY), and these two signals are opportunitys of selecting data to send, the foundation that guarantees that data can correctly be received by FIFO or read from FIFO;
Order control pin is used for the PC end and sends operational order to Target Board, makes it to carry out corresponding operation; Order control pin comprises the control clock signal pin ppCLK of PC end parallel port transceive data, the reset signal pin RESET of total system, and the selection signal pin CMD of system operation order.When system moves, need to select the current operation of carrying out, determine the length of control signal according to the quantity of action type; At least to comprise the system of FLASH online programming read, write, wipe, four kinds of operations such as verification, need at least that the 2bit data identify, so the present invention defines CMD[1..0] be used for the selection operation order.
Concrete pin definitions such as following table:
The forwarding step that the present invention is based on the general parallel port of PC is mainly set up communication protocol based on the definition of the special-purpose parallel port of online programming pin, and realizes the adaptive speed adjustment by the frequency of continuous adjustment ppCLK, thereby data are correctly sent to receiving end.
Based on the special-purpose parallel port of predefined online programming pin, set up the data communication protocol between PC parallel port and the Target Board, data are delivered to receiving end from this locality through the PC parallel port.Concrete data communication protocol has comprised data and has sent agreement and Data Receiving agreement, and data send the online data programming process that agreement is used for the FLASH storer, and the content that the Data Receiving agreement is used for the FLASH storer reads process.After the online programming system reset, judge current which kind of mode of operation that is in according to the CMD control signal.In the Data Receiving agreement, operational order is for reading, and system determines that by detecting the BUSY pin current system is in waiting status and still can carries out next step operation.When the BUSY signal when low, whether the state that system detects relevant FIFO is empty.If FIFO is empty, then idle running is waited for, becomes non-dummy status up to FIFO, reads the 2bit data then in the middle of the data register of parallel port, and corresponding data address adds 1, till reading last address.Data send in the agreement, and operational order is for writing, and system determines that by detecting the BUSY pin current system is in waiting status and still can carries out next step operation.When the BUSY signal when low, whether the state that system detects relevant FIFO is full.If FIFO is for full, then idle running is waited for, up to data from FIFO, take away, FIFO becomes non-full state, reads the 8bit data then from the data register of parallel port in FIFO, data address adds 1, till reading last address.More than be exactly that the online programming system finishes the foundation that PC holds and the Target Board end data is moved.
In order to adapt to the needs of different hardware equipment and practical application, the present invention proposes a kind of adaptive speed and adjust strategy, decide the speed of FLASH memory on-line programming with this.The time of PC end is designated as ppCLK, and the CPU that is held by PC provides; The clock of Target Board end is designated as fCLK, is provided by crystal oscillator on the plate.Adaptive speed adjustment strategy proposed by the invention has comprised two kinds of aggressive mode and Passive Mode: active speed adjustment is independently finished by system, realize the reliable and stable read-write of FLASH memory data content by continuous trial change ppCLK and fCLK, thereby obtain the fastest stable Mbus, and two clock ppCLK and fCLK are fixed.During this method is applicable to that the online programming of quick large batch of FLASH storer is used; The adjustment of passive type speed is then independently set clock speed by the user according to the fundamental characteristics and the performance of FLASH storer.This method can be applicable to generally that program speed is less demanding, the application of the online programming of the FLASH storer of negligible amounts.Adaptive speed is adjusted application of policies in the starting stage of FLASH online programming, in case optimal velocity fixing after, just begin according to the address of appointment and the online programming of content realization FLASH storer.
In FLASH online programming process, obtain the state of each signal by the general-purpose register that detects the parallel port, when BUSY and FULL signal are all invalid, read the data register of an eight bit data to the parallel port from this locality, next rising edge at ppCLK, data are sent to Target Board from the data register of parallel port, thereby finish the function that data send part.
The present invention is applied in the Data Receiving step of buffer interface part and target devices, and data are parallel after the output of PC parallel port with 8bit, need receiving end to handle and write the FLASH storer afterwards.Conflict mutually appears for fear of data, the present invention adopts the speed buffering of two first in first out of input and output (FIFO) storer as data, coordinate data transmit-receive speed difference between transmitting terminal and the receiving end with this, thereby guarantee that data can be received end accurately and obtain.The size of FIFO has certain influence to the speed of FLASH online programming.In general, the degree of depth of FIFO is big more, and then buffer zone is big more, and system can coordinate to send/receive the speed difference between the two ends better, has better system stability.The present invention adopts two asynchronous FIFO to use as Input FIFO (input push-up storage) and Output FIFO (output push-up storage) respectively.For Input FIFO, reading clock is provided by crystal oscillator fCLK on the plate, and writing clock is provided by the ppCLK signal of parallel port.For Output FIFO, reading clock is provided by the ppCLK signal of parallel port, and writing clock is provided by crystal oscillator fCLK on the plate.Input FIFO is used to write the online programming process of FLASH storer, is filled with and OutputFIFO is used to read FLASH, then waits pending data to write FLASH, and it is non-full that state becomes; Otherwise,, the data of current parallel port data register are sent at the rising edge of next ppCLK.FULL signal and BUSY signal have constituted the determinative that data could send immediately jointly.In reading the FLASH process, relate to the use of OutputFIFO.Whether the state that the PC end must detect Output FIFO is empty.If empty, must wait for that FIFO obtains data from FLASH, state becomes non-NULL; Otherwise in next ppCLK rising edge from FIFO reading of data.EMPTY signal and BUSY signal have constituted the determinative that can data receive immediately jointly.FULL passes through the parallel port line with the EMPTY signal and is connected PC end and Target Board, detects the validity that these two signals have guaranteed to read at every turn and write data.
The FLASH storer of different manufacturers different model can adopt different programming modes, and for the FLASH storer of different model, the cycle and the fix command word of read-write process have nothing in common with each other.Therefore, in receiving course, must at first determine the model of FLASH.The present invention proposes a kind of from mating the model choice mechanism, is used to address this problem.Certainly coupling model choice mechanism proposed by the invention comprises two major parts: the selection of model and the control of state.After system powers on, at first automatically, detect FLASH ID number, obtain the concrete model of the current FLASH to be programmed of system, determine to be applied to the fix command word that FLASH programmes by comparing, and then realize the read-write operation of FLASH storer with the FLASH component library of setting up in advance.The scope of building the FLASH component library in advance directly has influence on the general degree of this method.
The PC parallel port sends data with eight bit wide forms, and the form that FLASH can receive is the sixteen bit wide format.Therefore, the process of a format conversion must be arranged between said two devices, be used for eight bit wide data splicings are become the sixteen bit width, become the data layout that the FLASH storer can be supported.To the control that depends on state machine of finishing of the read-write operation of FLASH storer, State Control flow process of the present invention is a kind of method in common, contained system idle, reset, reading and writing, wipe, redirect between the state such as wait.Under the control of state machine, finish corresponding data manipulation at the corresponding address of FLASH storer.
Data check step of the present invention is actual to be that the process that will read process and contrast correction combines.Reading is the inverse process of above-mentioned ablation process.Difference is, is subject to the quantity of pin, and what read employing is the mode of two bit wide data parallels.Process of reading equally will be under the control of state machine, and dependence parallel port communication protocol is finished the data transfer from FIFO to the parallel port.Comparison process then is that data of reading back from FLASH and the data that are placed on buffer area compare, and runs into inconsistent numerical value and then revises and count; When wrong number accumulative total reached some, the programming by prompting failure required to write again.The process of revising is the process that individual data is write.In the actual application, therefore most the because hardware design problem of the situation of program fail is often omitted checking procedure and is carried out overprogram twice, also can improve the success ratio of FLASH memory on-line programming.
Whole implementation procedure of the present invention is: by detecting the control signal of control register, comprise: commencing signal START, clear flag CLEAR and reading and writing, command word such as wipe, be used for the current state of indication mechanism and the operation that will carry out, and set start address and end address at FLASH storage operation scope.Obtain after current action type and the address realm to be operated by control register, detect the state (full or empty) of FIFO in the hopping edge of clock, finish moving of data, and under the effective situation of the gating signal CE of FLASH memory interface, enable WE and finish respective operations according to reading to enable OE or writing, data are write the FLASH storer or from the FLASH storer, read.
The contrast prior art, the present invention possesses following advantage: (1) speed is fast and can adjust.What adopted the parallel port is the parallel data of 8bit, and speed generally about 1M, satisfies the needs of the fast programming of FLASH storer.Method provided by the invention not only speed is fast, and can regulate automatically, can satisfy the needs of different practical applications.(2) compatible good.The present invention has realized that by adopting from mating the model choice mechanism compatibility of the FLASH storer of different vendor's unlike signal is possessed very strong transfer ability.Further, can also pass through self-defined FLASH component library, enlarge the direct usable range of this method.(3) applied widely.Realize that by the parallel port method of FLASH online programming possesses the advantage of the quick online programming of FLASH.For JTAG, this method can be used for again in the middle of the CPU design process, does not need the CPU cooperating fully.This advantage has been expanded the application of FLASH online programming, has very big marketable value.
The present invention utilizes that existing resource realizes on the Target Board.Under the situation that has programmable logic device (PLD) on the development board, the present invention is except that PC end software section, and all functions can realize on programmable logic device (PLD) by hardware description language.
Do not having on the Target Board under the programmable logical device situation, can realize the function of interface circuit yet by simple gate circuit.Constitute asynchronous FIFO and simple register by SRAM, just can realize corresponding functional modules.
But, also can utilize ASIC to realize the present invention as a kind of online programming FLASH storer side method of large-scale application.Function involved in the present invention is generated IP core, realize, become the FLASH online programming device of a special use by ASIC.
Description of drawings
Fig. 1 is the process flow diagram of realizing according to the present invention by the FLASH online programming method of parallel port;
Fig. 2 is the system construction drawing of the FLASH online programming method implement device according to the present invention;
Fig. 3 is the system signal structural drawing of the FLASH online programming method implement device according to the present invention;
Fig. 4 is based on the HDTV system for decoding audiovisual frequency application system structural representation that the present invention adopts parallel port online programming FLASH method; And,
Fig. 5 is a process flow diagram of realizing the defined parallel port of FLASH online programming method of the present invention communication protocol.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention; provided detailed embodiment and concrete operating process, but protection scope of the present invention includes but not limited to following embodiment.
Fig. 4 is based on the present invention and adopts the parallel port to realize the method for FLASH online programming, has realized the structural representation to FLASH Configuration Online on the exploitation plate.It is the part of digital TV in high resolution decode system.
In this system, the SoC chip internal embeds the MIPS processor, needs the support of (SuSE) Linux OS.Thereby the boot program of operating system and system code all need be kept in the middle of the outer FLASH of sheet.The hardware environment that system provided comprises: ordinary PC, the development board that has FLASH on the sheet and data bus connection.Parallel port function pin that redefines and parallel port communication protocol all realizes by PC, then realizes that by FPGA on the plate Pi Pei model choice mechanism is also finished by FPGA certainly as the FIFO of speed buffering.The adjustment that the adaptive speed adjustment has then comprised two part: ppCLK is realized by PC end software, and in addition, the clock of read-write FLASH is then obtained by crystal oscillator on the FPGA frequency division plate.More than constituted the basis of a concrete embodiment of the present invention.
Fig. 4 has shown the relevant portion of system and FLASH memory on-line programming.Wherein, the AM29LV641 that FLASH adopts AMD to produce, the content of being stored comprises: the operating system of SoC innernal CPU, the code of audio decoder and the data form that some are commonly used.In this example, the buffer interface part is finished by programmable logic device (PLD) (FPGA), realizes the function of asynchronous FIFO and register, state machine, as shown in Figure 2, total system is made up of PC interface, control register, asynchronous FIFO and FLASH interface section, and detailed data flow diagram is with reference to Fig. 3.
The online programming specific implementation process of FLASH storer as shown in Figure 1.After system reset, carry out data sending step 101, at this moment, the PC end at first reads file to be programmed from this locality, and sets the start address and the end address of program segments, finishes the preliminary work of FLASH memory on-line programming.In case when PC end detection system state and affirmation system are ready, just can begin the online programming process.According to the data communication protocol of setting up, the opportunity of data is selected to send by checking the value of parallel port status register by system, and sends control command to receiving end by control register.
The ready condition of system is currently FLASH not to be carried out any operation, and system is not in the BUSY state.And the BUSY signal of system obtains from FPGA.System powers on and has loaded after the FPGA code, and BUSY position (the 11st pin of parallel port) is changed to 0.System is ready, can carry out next step operation.
After system is ready, then can begin to send or receive data step 102, otherwise the wait of dallying; Simultaneously, the speed of automatic adjustment system programming FLASH.By continuous trial read-write FLASH, finish the adjustment of speed.Guaranteeing under the correct situation of data programming, improving the frequency of ppCLK and fCLK (clock of FLASH end read-write FIFO) as far as possible.This method is applicable in the process of programming in enormous quantities FLASH, under the constant situation of hardware environment, obtains after the maximum reliable speed of programming two clock frequencies to be fixed, and finishes the programming to same model FLASH in enormous quantities.For monolithic FLASH, can skip this part of self-adapted adjustment system clock.
Before each read-write, all to judge the state of current FIFO.The state of FIFO is divided into full or non-full, sky etc.Write in the process, if FIFO is full, it is invalid that enable signal will be write by system, and PC end software sends part and enters the idle running waiting status, and the state of FIFO becomes non-full, and system will write enable signal and activate, and system enters the state of writing.In the read procedure, if FIFO is empty, it is invalid that enable signal will be read by system, and PC end software section enters the idle running waiting status, becomes non-NULL up to the state of FIFO, and system will read enable signal and activate, and system enters the state of writing, and the PC end can be from the FIFO reading of data.
Wherein, the realization of Data Receiving step 102 can have multiple mode, as long as can satisfy the functional requirement of Data Receiving buffering, State Control and Data Format Transform.In the middle of example system, adopt hardware logic descriptive language verilog HDL to realize by FPGA.This part mainly is divided into four modules: data fifo buffering, state machine control, Data Format Transform, writing module.
Wherein, FIFO is divided into input FIFO and output FIFO, as the buffering of data, is used in respectively in the process that reads or writes the FLASH storer.The design of FIFO is in order to guarantee the continuity of system data, can to increase the stability and the speed of system by the degree of depth that improves FIFO, but will expend more FPGA resource.
System detects ID number of the FLASH storer of acquisition on header board, by comparing with the component inventory of setting up in advance, obtains the concrete model of FLASH storer.At the AM29LV032 FLASH storer that this example adopted, under the control of state machine, finished function to its online programming.The data-switching that last data conversion module takes out FIFO becomes the parallel mode of 16bit, gives FLASH storer, finishes the programming to FLASH.
Fig. 5 has specifically shown the flow process that realizes the defined parallel port of FLASH online programming method of the present invention communication protocol.Online programming FLASH accumulator system resets after 500, and (Idle) state 501 that enters the free time is waited for next step operational order.At this moment, by the CMD[1..0 of parallel port] receive operational order from the PC termination, if current be write operation 501, then system enters the process 506 that writes data to the FLASH storer; If current is read operation 502, system enters the process that the data of reading the FLASH storer arrive the PC end.
Write in the process, whether system detects current operation and finishes, if do not finish, then enters waiting state, till finishing 506.After current operation was finished, system can carry out new operation, and the parallel port data register of holding from PC reads the 8bit data, gives FLASH storer 507.If FIFO is full in input, then enter waiting status 508, taken away by FLASH up to the data of FIFO; When FIFO becomes vacant state again, then new data can be write among the input FIFO.At this moment, PC memory cyclic address change 509, and judge the current last address 510 that whether arrived.If arrived last address, EO 512; Otherwise, continue the process 506 of next write data.
After entering read procedure, whether system need detect current operation equally and finish, if do not finish, then enters waiting state, till operation is finished 502.After operation was finished, system read the parallel port data register of 2bit data to the PC end from output FIFO.If export FIFO this moment for empty, then enter waiting status, up to there being data to move output FIFO 503 from FLASH, FIFO becomes non-dummy status, and data can be read from FIFO, and are written to the data register 504 of parallel port, and with the PC memory cyclic address change.Subsequently, judge the current last address 505 that whether arrived.If arrived last address, EO; Otherwise, continue next reading data course 503.Repeat said process till whole operation finishes.
The aspect that above example is only used for the present invention.All have possessed the system of the hardware environment that the present invention mentioned, and can adopt method provided by the invention to realize the online programming of FLASH, and the speed of programming and efficient can both be guaranteed.
Native system is provided with that the crystal oscillator clock is 4M on the plate, and the actual program velocity ratio is faster stable.This invention also can be used for large batch of programming FLASH storer, has sizable practical value.
Claims (10)
1, a kind of FLASH memory on-line programming method based on the parallel port, it is characterized in that, data communication protocol based on the foundation of special-purpose parallel port pin definitions, send data by the parallel port, utilize asynchronous FIFO to receive the data that transmit from the PC end, and under the control of state machine, write the FLASH storer, the line data verification of going forward side by side through format conversion.
2, the FLASH memory on-line programming method based on the parallel port according to claim 1 is characterized in that, comprises three steps, promptly the data based on the general parallel port of PC send, be applied to the Data Receiving of buffer interface part and target devices, and data check, wherein:
Described data sending step based on the general parallel port of PC comprises:
Based on the definition of online programming FLASH dedicated pin, set up new parallel port transmitting-receiving communication protocol;
Visit the general-purpose register of PC parallel port, obtain the state of parallel port signal; With,
Response parallel port signal condition, the adaptive speed adjustment is written to the data that local file read in the data register of general parallel port in good time, and sends with the basic format of 8 bit wides;
The described Data Receiving step that is applied to buffer interface part and target devices comprises:
The status mechanism of response data flow process, the clock on the Target Board is accepted in the self-adaptation adjustment, and adopts the buffering of asynchronous FIFO as high-speed data, receives the data that the parallel port sends in real time; With,
The FLASH model from matching detection, finish the basic conversion of data layout, the data after the conversion are write the target devices of required programming, i.e. FLASH storer;
Described data check step comprises:
Data in the FLASH storer are read back into PC; With,
The data and the PC local data that read back are compared the data of correcting a mistake.
3, the FLASH memory on-line programming method based on the parallel port according to claim 2 is characterized in that, described definition comprises based on online programming FLASH dedicated pin:
The data transmit-receive pin, be used to realize the link effect of swap data between PC parallel port and the receiving target device, parallel port transmission data owner will be used in the FLASH storer is carried out in the process of online programming, receiving the data that data then are used for reading FLASH carries out in the process of data check, send The data 8bit width form parallel mode, receive the parallel mode of The data 2bit;
The state-detection pin, be used for the state that the PC end detects Target Board, whether the online programming system detects current operation and is finished, can enter next operation, corresponding detection signal is BUSY, and system adopts two asynchronous FIFO to be respectively applied in the process of read and write FLASH, and whether asynchronous FIFO is full or empty, these two signals are opportunitys of selecting data to send, the foundation that guarantees that data can correctly be received by FIFO or read from FIFO;
Order control pin is used for the PC end and sends operational order to Target Board, makes it to carry out corresponding operation; Order control pin comprises that the PC end draws together the control clock signal pin ppCLK of parallel port transceive data, the reset signal pin RESET of total system, and the selection signal pin CMD of system operation order, when system moves, need to select the current operation of carrying out, determine the length of control signal according to the quantity of action type, at least to comprise the system of FLASH online programming read, write, wipe, four kinds of operations of verification, need at least that the 2bit data identify, definition CMD[1..0] be used for the selection operation order.
4, FLASH memory on-line programming method based on the parallel port according to claim 2, it is characterized in that, described data sending step based on the general parallel port of PC further comprises: set up data communication protocol between PC parallel port and the Target Board based on the definition of the special-purpose parallel port of online programming pin, data are delivered to receiving end from this locality through the PC parallel port, described data communication protocol comprises data and sends agreement and Data Receiving agreement, wherein, described data send the online programming process that agreement is used for the FLASH storer, described Data Receiving agreement is used to read the process of FLASH memory content, after the online programming system reset, judge current which kind of mode of operation that is in according to the CMD control signal.
5, the FLASH memory on-line programming method based on the parallel port according to claim 4, it is characterized in that, in the described Data Receiving agreement, operational order is for reading, system is by detecting the BUSY pin, determine that current system is in waiting status and still can carries out next step operation, when the BUSY signal when low, whether the state that system detects relevant FIFO is empty, if FIFO is empty, then idle running is waited for, become non-dummy status up to FIFO, read the 2bit data then in the middle of the data register of parallel port, corresponding data address adds 1, till reading last address;
Described data send in the agreement, operational order is for writing, and system determines that by detecting the BUSY pin current system is in waiting status and still can carries out next step operation, when the BUSY signal when low, whether the state that system detects relevant FIFO is full, if FIFO is for full, then idle running is waited for, up to data from FIFO, take away, FIFO becomes non-full state, read the 8bit data then from the data register of parallel port in FIFO, data address adds 1, till reading last address.
6, according to claim 2 or 4 described FLASH memory on-line programming methods based on the parallel port, it is characterized in that, described data sending step based on the general parallel port of PC also further comprises: adopt adaptive speed adjustment strategy to determine the speed of FLASH memory on-line programming, wherein, the time of PC end is designated as ppCLK, and the CPU that is held by PC provides; The clock of Target Board end is designated as fCLK, is provided by crystal oscillator on the plate;
Described adaptive speed adjustment strategy comprises aggressive mode and Passive Mode: active speed adjustment is independently finished by system, realize the reliable and stable read-write of FLASH memory data content by continuous trial change ppCLK and fCLK, thereby obtain the fastest stable Mbus, and two clock ppCLK and fCLK are fixed; The adjustment of passive type speed is then independently set clock speed by the user according to the fundamental characteristics and the performance of FLASH storer, adaptive speed is adjusted application of policies in the starting stage of FLASH online programming system, in case after optimal velocity is fixing, just begin according to the address of appointment and the online programming of content realization FLASH storer.
7, according to claim 2 or 4 described FLASH memory on-line programming methods based on the parallel port, it is characterized in that, described data sending step based on the general parallel port of PC also further comprises: in FLASH programming process, obtain the state of each signal by the general-purpose register that detects the parallel port, when BUSY and FULL signal are all invalid, read the data register of an eight bit data to the parallel port from this locality, next rising edge at ppCLK, send the data to Target Board and deliver to Target Board, finish the function that data send part from the data register of parallel port.
8, the FLASH memory on-line programming method based on the parallel port according to claim 2, it is characterized in that, the described Data Receiving step that is applied to buffer interface part and target devices further comprises: employing InputFIFO and two asynchronous FIFO of Output FIFO coordinate the data transmit-receive speed difference between transmitting terminal and the receiving end, for Input FIFO, reading clock is provided by crystal oscillator fCLK on the plate, and writing clock is provided by the ppCLK signal of parallel port; For Output FIFO, reading clock is provided by the ppCLK signal of parallel port, and writing clock is provided by crystal oscillator fCLK on the plate; Input FIFO is used to write FLASH storer process, is filled with and Output FIFO is used to read FLASH, then waits pending data to write FLASH, and it is non-full that state becomes; Otherwise,, the data of current parallel port data register are sent at the rising edge of next ppCLK; FULL signal and BUSY signal have constituted the determinative that data could send immediately jointly, in reading the FLASH process, relate to the use of Output FIFO, whether the state that the PC end must detect Output FIFO is empty, if it is empty, must wait for that FIFO obtains data from FLASH, state becomes non-NULL; Otherwise in next ppCLK rising edge from FIFO reading of data; EMPTY signal and BUSY signal have constituted the determinative that can data receive immediately jointly, and FULL passes through the parallel port line with the EMPTY signal and is connected PC end and Target Board, detects the validity that these two signals have guaranteed to read at every turn and write data.
9, according to claim 2 or 8 described FLASH memory on-line programming methods based on the parallel port, it is characterized in that, the described Data Receiving step that is applied to buffer interface part and target devices also further comprises: adopt from mating the model choice mechanism, described mating the model choice mechanism comprises two parts certainly: the selection of model and the control of state, automatic ID number of detecting FLASH of meeting after system powers on, obtain the concrete model of FLASH that current system adopts, compare the fix command word that adopts in definite FLASH programming process by FLASH component library, and then finish read-write operation the FLASH storer with foundation in advance; The State Control that adopts is a kind of method in common, contain system idle, reset, reading and writing, wipe, redirect between the waiting status, under the control of state machine, finish corresponding data manipulation at the corresponding address of FLASH storer.
10, the FLASH memory on-line programming method based on the parallel port according to claim 1 and 2, it is characterized in that, the process that described data check step will read process and contrast correction combines, wherein: reading is the inverse process of ablation process, adopt the mode of two bit wide data parallels, under the control of state machine, dependence parallel port communication protocol is finished the data transfer from FIFO to the parallel port; Comparison process then is the data of reading back from FLASH, according to comparing with the data that are placed on buffer area, runs into inconsistent numerical value and then revises and count, and when wrong number accumulative total reached some, the programming by prompting failure required to write again; The process of revising is the process that individual data is write.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100348599A CN101315812A (en) | 2008-03-20 | 2008-03-20 | FLASH memory on-line programming method based on parallel port |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100348599A CN101315812A (en) | 2008-03-20 | 2008-03-20 | FLASH memory on-line programming method based on parallel port |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101315812A true CN101315812A (en) | 2008-12-03 |
Family
ID=40106772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008100348599A Pending CN101315812A (en) | 2008-03-20 | 2008-03-20 | FLASH memory on-line programming method based on parallel port |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101315812A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103544079A (en) * | 2013-10-28 | 2014-01-29 | 公安部第三研究所 | Flash memory chip data recovery achieving system and method based on programmable logic controller |
| CN103885850A (en) * | 2013-03-01 | 2014-06-25 | 上海富欣智能交通控制有限公司 | Online inspection system and online inspection method for memorizer |
| CN105487890A (en) * | 2015-11-25 | 2016-04-13 | 天津航空机电有限公司 | Firmware downloading method based on C51 series single chip microcomputer kernel |
| CN105515568A (en) * | 2015-12-04 | 2016-04-20 | 深圳市同创国芯电子有限公司 | FPGA (Field-Programmable Gate Array) configuration control method and device based on FLASH, FLASH and FPGA |
| CN105575426A (en) * | 2014-10-08 | 2016-05-11 | 无锡华润矽科微电子有限公司 | On-line programming circuit of embedded memory, and control method thereof |
| CN105869677A (en) * | 2015-02-06 | 2016-08-17 | 三星电子株式会社 | Memory device for internally performing read-verify operation, method of operating the same, and memory system including the same |
| CN105930186A (en) * | 2016-04-20 | 2016-09-07 | 中车株洲电力机车研究所有限公司 | Multi-CPU (Central Processing Unit) software loading method and multi-CPU-based software loading device |
| CN108092921A (en) * | 2017-12-14 | 2018-05-29 | 浪潮软件集团有限公司 | Data exchange system and method |
| CN114035472A (en) * | 2021-11-09 | 2022-02-11 | 阳光学院 | Method and terminal for on-line programming of embedded programmable controller by CAN bus |
| CN114327298A (en) * | 2022-01-28 | 2022-04-12 | 中科亿海微电子科技（苏州）有限公司 | FPGA (field programmable Gate array) -based method for simulating SSM (System management Module) configuration interface and SSM configuration interface |
| CN115269017A (en) * | 2022-09-29 | 2022-11-01 | 天津讯联科技有限公司 | Satellite-borne measurement and control data transmission NANDFlash parallel read-write control method |
-
2008
- 2008-03-20 CN CNA2008100348599A patent/CN101315812A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103885850A (en) * | 2013-03-01 | 2014-06-25 | 上海富欣智能交通控制有限公司 | Online inspection system and online inspection method for memorizer |
| CN103885850B (en) * | 2013-03-01 | 2016-12-28 | 上海富欣智能交通控制有限公司 | Memorizer On line inspection system and method |
| CN103544079A (en) * | 2013-10-28 | 2014-01-29 | 公安部第三研究所 | Flash memory chip data recovery achieving system and method based on programmable logic controller |
| CN103544079B (en) * | 2013-10-28 | 2017-02-01 | 公安部第三研究所 | Flash memory chip data recovery achieving system and method based on programmable logic controller |
| CN105575426A (en) * | 2014-10-08 | 2016-05-11 | 无锡华润矽科微电子有限公司 | On-line programming circuit of embedded memory, and control method thereof |
| CN105575426B (en) * | 2014-10-08 | 2019-07-12 | 无锡华润矽科微电子有限公司 | A kind of the online programming circuit and its control method of embedded flash memory |
| CN105869677A (en) * | 2015-02-06 | 2016-08-17 | 三星电子株式会社 | Memory device for internally performing read-verify operation, method of operating the same, and memory system including the same |
| CN105869677B (en) * | 2015-02-06 | 2021-05-11 | 三星电子株式会社 | Memory device for internally performing read-verify operation, operating method thereof, and memory system |
| CN105487890A (en) * | 2015-11-25 | 2016-04-13 | 天津航空机电有限公司 | Firmware downloading method based on C51 series single chip microcomputer kernel |
| CN105515568A (en) * | 2015-12-04 | 2016-04-20 | 深圳市同创国芯电子有限公司 | FPGA (Field-Programmable Gate Array) configuration control method and device based on FLASH, FLASH and FPGA |
| CN105930186A (en) * | 2016-04-20 | 2016-09-07 | 中车株洲电力机车研究所有限公司 | Multi-CPU (Central Processing Unit) software loading method and multi-CPU-based software loading device |
| CN105930186B (en) * | 2016-04-20 | 2019-03-08 | 中车株洲电力机车研究所有限公司 | The method for loading software of multi -CPU and software loading apparatus based on multi -CPU |
| CN108092921A (en) * | 2017-12-14 | 2018-05-29 | 浪潮软件集团有限公司 | Data exchange system and method |
| CN114035472A (en) * | 2021-11-09 | 2022-02-11 | 阳光学院 | Method and terminal for on-line programming of embedded programmable controller by CAN bus |
| CN114327298A (en) * | 2022-01-28 | 2022-04-12 | 中科亿海微电子科技（苏州）有限公司 | FPGA (field programmable Gate array) -based method for simulating SSM (System management Module) configuration interface and SSM configuration interface |
| CN115269017A (en) * | 2022-09-29 | 2022-11-01 | 天津讯联科技有限公司 | Satellite-borne measurement and control data transmission NANDFlash parallel read-write control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101315812A (en) | FLASH memory on-line programming method based on parallel port | |
| US8639852B2 (en) | Burst access protocol | |
| US7363396B2 (en) | Supercharge message exchanger | |
| JP5186548B2 (en) | Interface device for host device, interface device for slave device, host device, slave device, communication system, and interface voltage switching method | |
| CN107656773A (en) | Multi-core DSP starting method | |
| WO2001090900A1 (en) | The method of emulating different protocol of flash memory | |
| CN105808396A (en) | Chip debugging device, debugging method and SOC (System of Chip) chip system | |
| CN111190842B (en) | Direct memory access, processor, electronic device, and data transfer method | |
| CN100370409C (en) | Method and apparatus for calibrating random access memory | |
| US7035956B2 (en) | Transmission control circuit, reception control circuit, communications control circuit, and communications control unit | |
| CN114490460A (en) | FLASH controller for ASIC and control method thereof | |
| US20040153582A1 (en) | Data processor and memory card | |
| CN100459612C (en) | A communication transmission control device and method for implementing communication protocol control | |
| US8176209B2 (en) | Data communication system | |
| CN100498753C (en) | Method for accessing on-site programmable gate array internal memory through I2C interface | |
| US20120221825A1 (en) | Nonvolatile memory system and feature information setting method | |
| CN102385912B (en) | Host controller for setting sampling phase, semiconductor device and method | |
| CN115016352A (en) | Instruction reading structure and reading method of MCU | |
| CN108228517A (en) | I3C circuit arrangements, system and communication means | |
| CN214751393U (en) | Microcontroller and computing system | |
| CN112463172A (en) | Data burning method and system | |
| CN109726149B (en) | Method and device for accessing NAND FLASH through AXI bus | |
| CN111198837A (en) | SDIO interface system based on FPGA and controller bridging method | |
| CN101097555B (en) | Method and system for processing data on chip | |
| CN101145797A (en) | FPGA and DSP communication structure and method for radio data transmission broadcasting station digital signal processing module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20081203 |