CN115016352A - Instruction reading structure and reading method of MCU - Google Patents

Instruction reading structure and reading method of MCU Download PDF

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Publication number
CN115016352A
CN115016352A CN202210687779.3A CN202210687779A CN115016352A CN 115016352 A CN115016352 A CN 115016352A CN 202210687779 A CN202210687779 A CN 202210687779A CN 115016352 A CN115016352 A CN 115016352A
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China
Prior art keywords
mcu
control unit
instruction
clock signal
unit
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CN202210687779.3A
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Chinese (zh)
Inventor
李明
郭晓旭
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Jiangsu Jicui Intelligent Integrated Circuit Design Technology Research Institute Co ltd
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Jiangsu Jicui Intelligent Integrated Circuit Design Technology Research Institute Co ltd
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Priority to CN202210687779.3A priority Critical patent/CN115016352A/en
Publication of CN115016352A publication Critical patent/CN115016352A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24215—Scada supervisory control and data acquisition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to the technical field of MCU (microprogrammed control unit), and discloses an instruction reading structure and an instruction reading method of an MCU (microprogrammed control Unit), wherein the instruction reading structure comprises a cache storage unit, a storage control unit, a nonvolatile storage unit and a clock control unit.

Description

Instruction reading structure and reading method of MCU
Technical Field
The invention relates to the technical field of MCU, in particular to an instruction reading structure and an instruction reading method of the MCU.
Background
8051 is an 8-bit microcontroller, belongs to a single chip of MCS-51, and is widely applied to the development of various single chips. The operation of the singlechip is realized by reading and executing instructions by the microcontroller, the instructions are mostly stored in a nonvolatile memory device, such as mtp, flash or eeprom, and the execution of the instructions comprises the processing of data.
For the 8051MCU, the instruction bus and the data bus are independent and are both RAM-like buses, and no waiting mechanism exists. Taking the 8051MCU as an example, the instruction reading has the following two modes:
the first method is as follows: as shown in fig. 1, the reading mode is a copy mode, that is, an instruction is first copied from the nonvolatile memory cell to the instruction memory cell by the automatic loading unit, and then the MCU is started, and the MCU starts to execute from the 0 address in the instruction memory cell; although the processing speed of the method is high, the MCU can quickly execute the instruction, the method has larger circuit area because of additionally increasing the instruction storage unit;
the second method comprises the following steps: as shown in fig. 2, the method is direct reading, that is, the MCU directly reads instructions from the nonvolatile memory unit, but because there is a great difference between the bus speed of the MCU and the reading speed of the memory control unit and the nonvolatile memory unit, the reading structure of the MCU needs to be adjusted, for example, a cache memory unit and a RAM type instruction bus for receiving instructions by the MCU are added to be an interactive instruction bus based on handshaking, and the latter adjustment needs to change the internal architecture of the MCU, where the MCU architecture is divided into components of fetching, decoding, executing, and reading and writing of the memory, for the MCU of class 8051, the operations of all components are performed based on fixed beats, once the fetching waits, all the components wait, that is, all the components are modified, for the application side of the MCU, it only uses the microcontroller of the MCU, and the adjustment of the internal architecture of the MCU needs to be completely clear details of the internal implementation of the MCU, after the modification, detailed verification work is performed, which increases development cost and development period.
Disclosure of Invention
In view of the defects of the background art, the invention provides an instruction reading structure and an instruction reading method of an MCU (microprogrammed control unit), which are used for solving the defects of the existing MCU in a direct reading mode when reading an instruction.
In order to solve the above technical problems, in a first aspect, the present invention provides an instruction reading structure of an MCU, including an MCU, a cache memory unit, a memory control unit, a nonvolatile memory unit and a clock control unit, wherein the MCU is electrically connected to the cache memory unit, the cache memory unit is electrically connected to a clock stop signal input terminal of the clock control unit and the memory control unit, the memory control unit is electrically connected to the nonvolatile memory unit, and a clock signal output terminal of the clock control unit is electrically connected to the MCU;
when the cache storage unit receives an instruction fetching command sent by the MCU, the cache storage unit firstly inquires whether an instruction requested by the MCU is stored in the cache storage unit, and if the requested instruction is stored in the cache storage unit, the cache storage unit sends the requested instruction to the MCU; if the requested instruction is not stored in the cache memory unit, the cache memory unit firstly sends a clock signal for stopping outputting to a control terminal of the clock control unit, then the requested instruction is read from the nonvolatile memory unit through the memory control unit, the cache memory unit reads the requested instruction from the nonvolatile memory unit and then sends the requested instruction to the MCU, and stops sending a clock signal for stopping outputting to the clock control unit, the clock control unit stops providing the clock signal to the MCU after receiving the clock signal for stopping outputting, and the clock control unit provides the clock signal to the MCU when not receiving the clock signal for stopping outputting.
In practical use, the clock control unit is added to provide a clock signal for the MCU, when the high-speed buffer storage unit does not have an instruction requested by the MCU, the clock control unit stops providing the clock signal for the MCU to stop running, after the high-speed buffer storage unit acquires the instruction requested by the MCU from the nonvolatile storage unit, the clock control unit continues providing the clock signal for the MCU when the acquired instruction requested by the MCU is sent to the MCU, and the MCU can acquire the instruction from the high-speed buffer storage unit in a direct reading mode without largely adjusting the internal framework of the MCU.
When the instruction reading structure is adopted, circuits related to timing in the MCU are required to be adjusted, and the circuits comprise a timer and a UART circuit (serial port circuit). The timer is also suspended in a mode of stopping inputting the clock to the MCU, so that the accuracy of timing is influenced; the UART circuit needs to communicate with the outside and also needs an accurate clock for counting. Therefore, the functions of the clock circuit can be ensured to be correct only by separating the clocks of the timer and the UART circuit from the clocks of other parts of the MCU to ensure that the clocks of the timer and the UART circuit are continuous and can be accurately timed and counted, and other parts do not need to be modified.
In a certain implementation manner of the first aspect, the clock control unit includes a latch and an and gate, an input end of the latch is electrically connected to the cache memory unit, an output end of the latch is electrically connected to a first input end of the and gate, an enable end of the latch is electrically connected to a second input end of the and gate, and an output end of the and gate is connected to the MCU.
In a certain embodiment of the first aspect, the MCU is further electrically connected with a data storage unit.
In one embodiment of the first aspect, the nonvolatile memory cell is FLASH, MTP, or EEPROM.
In a second aspect, the present invention further provides a method for reading an MCU instruction, including the following steps:
s1: when the MCU transmits an instruction fetch command to the cache memory unit, if the instruction requested by the MCU is in the cache memory unit, the cache memory unit transmits the requested instruction to the MCU, and if the instruction requested by the MCU is not in the cache memory unit, the step S2 is performed;
s2: stopping inputting the clock signal to the MCU;
s3: and the cache storage unit acquires the requested instruction from the nonvolatile storage unit for storing the instruction, sends the requested instruction to the MCU after acquiring the requested instruction, and provides a clock signal for the MCU again.
In practical use, the invention stops inputting the clock signal to the MCU when the cache storage unit has no instruction requested by the MCU, so that the MCU stops running, and provides the clock signal to the MCU again when the cache storage unit sends the requested instruction acquired from the nonvolatile storage unit to the MCU, so that the MCU continues running, and the MCU can acquire the instruction from the cache storage unit in a direct reading mode without largely adjusting the internal framework of the MCU.
In one embodiment of the second aspect, the clock signal is input to the MCU through a clock control unit, and in step S2, the cache memory unit sends a stop output clock signal to the clock control unit, and the clock control unit stops inputting the clock signal to the MCU after receiving the stop output clock signal; in step S3, the cache memory unit stops sending the stop output clock signal to the clock control unit, which provides the clock signal to the MCU.
In a certain embodiment of the second aspect, the clock control unit includes a latch and an and gate, the external clock is simultaneously input to the enable terminal of the latch and the second input terminal of the and gate, the output of the latch is electrically connected to the first input terminal of the and gate, and the output of the and gate is electrically connected to the clock signal input terminal of the MCU.
Compared with the prior art, the invention has the beneficial effects that: the invention stops inputting the clock signal to the MCU when the high-speed buffer storage unit has no instruction requested by the MCU, so that the MCU stops running, and provides the clock signal to the MCU again when the high-speed buffer storage unit sends the requested instruction acquired from the nonvolatile storage unit to the MCU, so that the MCU continues running, and the MCU can acquire the instruction from the high-speed buffer storage unit in a direct reading mode without largely adjusting the internal framework of the MCU.
Drawings
FIG. 1 is a schematic structural diagram of an existing MCU reading an instruction by a copy method; (ii) a
FIG. 2 is a schematic diagram of a conventional MCU reading an instruction in a direct reading manner;
FIG. 3 is a block diagram illustrating an exemplary instruction fetch architecture;
FIG. 4 is a schematic structural diagram of a clock control unit according to the present invention in an embodiment;
FIG. 5 is a timing diagram of the use of the clock control unit of the present invention in an embodiment;
FIG. 6 is a flowchart illustrating an instruction fetch method according to an embodiment of the present invention.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
As shown in fig. 1 and 2, the instruction reading structure of the existing MCU has the defects of large circuit area, and the need to adjust the internal architecture of the MCU in a large amount. In order to obtain an instruction from a cache memory unit in a direct reading mode without largely adjusting the internal architecture of the MCU, as shown in fig. 3, the present invention provides an instruction reading structure of the MCU, which includes an MCU1, a cache memory unit 2, a memory control unit 3, a nonvolatile memory unit 4 and a clock control unit 5, wherein the MCU1 is electrically connected to the cache memory unit 2, the cache memory unit 2 is electrically connected to a clock stop signal input terminal of the clock control unit 5 and the memory control unit 3, the memory control unit 3 is electrically connected to the nonvolatile memory unit 4, and a clock signal output terminal of the clock control unit 5 is electrically connected to the MCU 1;
when receiving a command fetching command sent by the MCU1, the cache unit 2 firstly queries whether the command requested by the MCU1 is already stored in the cache unit 2, and if the requested command is already stored in the cache unit 2, the cache unit 2 sends the requested command to the MCU 1; if the requested instruction is not stored in the cache memory unit 2, the cache memory unit 2 first sends a stop output clock signal to the control terminal of the clock control unit 5, and then reads the requested instruction from the nonvolatile memory unit 4 through the memory control unit 3, the cache memory unit 2 sends the requested instruction to the MCU1 after reading the requested instruction from the nonvolatile memory unit 4, and stops sending the stop output clock signal to the clock control unit 5, the clock control unit 5 stops supplying the clock signal to the MCU1 after receiving the stop output clock signal, and the clock control unit 5 supplies the clock signal to the MCU1 when not receiving the stop output clock signal.
In practical use, the clock control unit 5 is added to provide a clock signal to the MCU, when there is no MCU-requested instruction in the cache unit 2, the clock control unit 5 stops providing the clock signal to the MCU to stop the MCU, and after the cache unit 2 obtains the MCU 1-requested instruction from the nonvolatile memory unit 4, the clock control unit 5 continues providing the clock signal to the MCU1 when sending the obtained requested instruction to the MCU1, so that the MCU1 can obtain the instruction from the cache unit 2 by direct reading without making a large amount of adjustment on the internal architecture of the MCU 1.
As shown in fig. 4, the clock control unit 5 comprises a LATCH AND an AND gate AND, an input terminal of the LATCH is electrically connected to the cache memory unit 2, an output terminal of the LATCH is electrically connected to a first input terminal of the AND gate AND, an enable terminal of the LATCH is electrically connected to a second input terminal of the AND gate AND, AND an output terminal of the AND gate AND is connected to the MCU 1. In actual use, the enable terminal of the LATCH is configured to receive the input clock signal Sys _ Clk, the input terminal of the LATCH is configured to receive the stop output clock signal Clk _ en, AND the output terminal of the AND gate provides the clock signal Mcu _ Clk to the MCU 1.
As shown in fig. 5, the operation timing diagram of the clock control unit 5 can be obtained from fig. 5, since the LATCH is active low, when the clock signal sys _ Clk is low, the change of the stop output clock signal Clk _ en at the D port of the LATCH will be transmitted to the Q port, even if there is a glitch transmitted in, the low level of the clock signal sys _ Clk controls the transmission of the AND gate AND, AND the glitch cannot reach the MCU1 through the AND gate AND; when the clock signal sys _ clk is high, the value at the Q port of the LATCH latches, and the value at the D port of the LATCH is always kept before the rising edge of the clock signal sys _ clk. Therefore, the clock control unit 5 of the present invention can ensure that the clock signal input to the MCU1 has no glitch and will not affect the normal use of the MCU 1.
Specifically, in the present embodiment, the MCU1 is also electrically connected to a data storage unit 6.
Specifically, in this embodiment, the nonvolatile memory unit 4 is FLASH, MTP or EEPROM.
As shown in fig. 6, the present invention further provides a method for reading an MCU command, including the following steps:
s1: when the MCU1 sends an instruction fetch command to the cache unit 2, if the instruction requested by the MCU1 is within the cache unit 2, the cache unit 2 sends the requested instruction to the MCU1, and if the instruction requested by the MCU1 is not within the cache unit 2, step S2 is performed;
s2: stopping the input of the clock signal to the MCU 1;
s3: the cache unit 2 acquires a requested instruction from the nonvolatile storage unit 4 that stores the instruction, and transmits the requested instruction to the MCU1 after acquiring the requested instruction, while resupplying the clock signal to the MCU 1.
In practical use, the invention stops inputting the clock signal to the MCU when the cache storage unit has no instruction requested by the MCU, so that the MCU stops running, and provides the clock signal to the MCU again when the cache storage unit sends the requested instruction acquired from the nonvolatile storage unit to the MCU, so that the MCU continues running, and the MCU can acquire the instruction from the cache storage unit in a direct reading mode without largely adjusting the internal framework of the MCU.
Specifically, in this embodiment, the clock signal is input to the MCU1 through the clock control unit 5, in step S2, the cache unit 2 sends the output stop clock signal to the clock control unit 1, and the clock control unit 5 stops inputting the clock signal to the MCU1 after receiving the output stop clock signal; in step S3, the cache unit 2 stops transmitting the stop output clock signal to the clock control unit 5, and the clock control unit 5 supplies the clock signal to the MCU 1.
Specifically, in this embodiment, the clock control unit 5 includes a LATCH AND an AND gate AND, an external clock is simultaneously input to an enable terminal of the LATCH AND a second input terminal of the AND gate AND, an output terminal of the LATCH is electrically connected to a first input terminal of the AND gate AND, AND an output terminal of the AND gate AND is electrically connected to a clock signal input terminal of the MCU 1. Referring to fig. 5, in practical use, the clock control unit 5 can ensure that the clock signal input to the MCU1 has no glitch, and the normal use of the MCU1 is not affected.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims (7)

1. An instruction reading structure of an MCU (microprogrammed control Unit), which comprises the MCU and is characterized by further comprising a high-speed buffer storage unit, a storage control unit, a nonvolatile storage unit and a clock control unit, wherein the MCU is electrically connected with the high-speed buffer storage unit, the high-speed buffer storage unit is respectively electrically connected with a clock stop signal input end of the clock control unit and the storage control unit, the storage control unit is electrically connected with the nonvolatile storage unit, and a clock signal output end of the clock control unit is electrically connected with the MCU;
when the cache storage unit receives an instruction fetching command sent by the MCU, the cache storage unit firstly inquires whether an instruction requested by the MCU is stored in the cache storage unit, and if the requested instruction is stored in the cache storage unit, the cache storage unit sends the requested instruction to the MCU; if the requested instruction is not stored in the cache memory unit, the cache memory unit firstly sends a clock signal for stopping outputting to a control terminal of the clock control unit, then the requested instruction is read from the nonvolatile memory unit through the memory control unit, the cache memory unit reads the requested instruction from the nonvolatile memory unit and then sends the requested instruction to the MCU, and stops sending a clock signal for stopping outputting to the clock control unit, the clock control unit stops providing the clock signal to the MCU after receiving the clock signal for stopping outputting, and the clock control unit provides the clock signal to the MCU when not receiving the clock signal for stopping outputting.
2. The structure of claim 1, wherein the clock control unit comprises a latch and an and gate, an input terminal of the latch is electrically connected to the cache unit, an output terminal of the latch is electrically connected to a first input terminal of the and gate, an enable terminal of the latch is electrically connected to a second input terminal of the and gate, and an output terminal of the and gate is connected to the MCU.
3. The structure of claim 1, wherein the MCU is further electrically connected to a data storage unit.
4. The structure of claim 1, wherein the non-volatile memory unit is FLASH, MTP or EEPROM.
5. An instruction reading method of an MCU (microprogrammed control Unit), comprising the steps of:
s1: when the MCU transmits an instruction fetch command to the cache unit, if the instruction requested by the MCU is in the cache unit, the cache unit transmits the requested instruction to the MCU, and if the instruction requested by the MCU is not in the cache unit, step S2 is performed;
s2: stopping inputting the clock signal to the MCU;
s3: and the cache storage unit acquires the requested instruction from the nonvolatile storage unit for storing the instruction, sends the requested instruction to the MCU after acquiring the requested instruction, and provides a clock signal for the MCU again.
6. The method according to claim 5, wherein the clock signal is input to the MCU through a clock control unit, and in step S2, the cache memory unit sends a stop output clock signal to the clock control unit, and the clock control unit stops inputting the clock signal to the MCU after receiving the stop output clock signal; in step S3, the cache memory unit stops sending the stop output clock signal to the clock control unit, which provides the clock signal to the MCU.
7. The method of claim 5, wherein the clock control unit comprises a latch and an AND gate, the external clock is simultaneously inputted to the enable terminal of the latch and the second input terminal of the AND gate, the clock signal is stopped from being inputted to the input terminal of the latch, the output terminal of the latch is electrically connected to the first input terminal of the AND gate, and the output terminal of the AND gate is electrically connected to the clock signal input terminal of the MCU.
CN202210687779.3A 2022-06-17 2022-06-17 Instruction reading structure and reading method of MCU Pending CN115016352A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115686635A (en) * 2023-01-03 2023-02-03 杭州米芯微电子有限公司 MCU structure without clock circuit and corresponding electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115686635A (en) * 2023-01-03 2023-02-03 杭州米芯微电子有限公司 MCU structure without clock circuit and corresponding electronic equipment

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