CN1924758A - Multi-clock domain system reset circuit - Google Patents
Multi-clock domain system reset circuit Download PDFInfo
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- CN1924758A CN1924758A CN 200510098560 CN200510098560A CN1924758A CN 1924758 A CN1924758 A CN 1924758A CN 200510098560 CN200510098560 CN 200510098560 CN 200510098560 A CN200510098560 A CN 200510098560A CN 1924758 A CN1924758 A CN 1924758A
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Abstract
This invention discloses one multi-clock zone system reset circuit, which comprises the following parts: signal lag parts; double input and single output gate one; asynchronous reset type main controller clock trigger one and two; asynchronous reset type pair control clock trigger one and two; asynchronous reset type controlled time trigger one and two. The invention circuit is not sensitive to the reset signal fuzzy without stable and normal situation.
Description
Technical field
The present invention relates to the ASIC circuit field, relate in particular to the realization circuit of clock zone system reset circuit.
Background technology
In the ASIC circuit design, the reset circuit mode is divided into two kinds of synchronous reset (Fig. 1) and asynchronous resets (Fig. 2).
Fig. 1 is typical synchronous reset circuit.The input of the reset signal of synchronous reset circuit and data with after act on the data input pin of trigger.The reset condition of circuit is effectively along reset signal is effective constantly at clock.
Fig. 2 is typical asynchronous reset circuit.The reset signal of asynchronous reset circuit acts on the asynchronous reset end of trigger.The reset condition of circuit is that reset signal is effective.
This reset circuit of two types respectively has relative merits.
The synchronous reset circuit has the following advantages:
Trigger only to clock effectively along the time the signal sensitivity of data input pin, reset signal acts on the data terminal of trigger, so effectively insensitive along outer burr to clock.
The synchronous reset circuit has following shortcoming:
1, the emulation initial stage, uncertain value can appear in the data output end of trigger, can cause simulation result and actual result inconsistent;
2, owing to the data input pin at trigger has increased a logic gate, data path sequential meeting variation;
3, synchronous reset signal moment of losing efficacy not controlled for circuit, the time that arrives different triggers sometimes is inconsistent, can cause the trigger reset time in the circuit inconsistent, causes the uncertain of circuit reset state.
Asynchronous reset circuit has the following advantages:
1, the clock of asynchronous reset signal and circuit is irrelevant, and transmission path can be very long;
2, during emulation, the data output end of trigger uncertain value can not occur;
3, reset signal is not introduced data path, the data path sequential is better than synchronous reset circuit.
Asynchronous reset circuit has following shortcoming:
1, asynchronous reset circuit does not allow any burr to the stability requirement height of reset signal;
2, asynchronous reset signal moment of losing efficacy not controlled for circuit, the time that arrives different triggers sometimes is inconsistent, can cause the trigger reset time in the circuit inconsistent, causes the uncertain of circuit reset state.
As shown in Figure 1 and Figure 2, reason owing to transmission line, the moment that reset signal arrives the asynchronous reset end of trigger 1, trigger 2 has small difference, if reset signal clock effectively along near inefficacy, may cause reset signal in the different clock period, to arrive trigger 1, trigger 2, so, the original state of these two triggers will be inconsistent with expecting state.So simply same, asynchronous reset mode may cause the original state of circuit incorrect.
In some bigger ASIC Circuits System, a plurality of clock zones are often arranged and have exchanges data between the different clock-domains.In normal operation, the exchanges data between different clock-domains has multiple exchanged form according to data characteristic, can solve by dissimilar switched circuits.But if reset mode is single, the generation that resets is constantly unpredictable, and the inefficacy that resets is constantly uncontrollable, and the exchanges data of circuit when resetting loss of data may take place, and causes system's operation disorder.
In multi-clock zone system (supposing the system exists A clock, B clock), whether the data output A that the A clock zone produces has used B clock zone back-signalling to be divided into two kinds of handshaking type and direct-type according to passing through the B clock zone.
The handshaking type index is crossing to the B clock zone according to output A from the A clock zone, when data output A need change, whether judge effectively by detecting B clock zone back-signalling whether the B clock zone has successfully received data, if B clock zone back-signalling is effective, then can export A by transform data, if B clock zone back-signalling is invalid, then keep data output A until B clock zone back-signalling is effective.
This mode transfer efficiency is slow, and circuit complexity but security is good is applicable to the circuit of data output A change frequency greater than B clock frequency or bus-type data transmission.
The direct-type index, when data output A need change, does not need to detect the B clock zone and whether has successfully received data output A, Direct Transform data output A when the A clock zone is crossing to the B clock zone according to output A.
This mode transfer efficiency height, circuit is simple, is applicable to that data output A change frequency is the circuit of non-bus-type signal less than B clock frequency and data output A.
When system reset, especially the multi-clock zone asynchronous reset because resetting of each clock zone is constantly inconsistent, can cause the mistake of direct-type data transmission.
As shown in Figure 3, the A clock frequency is greater than the B clock frequency, and data output A is non-bus-type signal, and change frequency is less than the B clock frequency, and data output A passes through the B clock zone by the A clock zone, is suitable for the direct-type data transmission.The reset values of data output A is 0, and the 1st A that resetted after losing efficacy at A becomes 1 after the clock period, effectively becomes 0 in the edge at the 3rd the A clock that resetted after losing efficacy then.
The original intention of circuit design be A clock zone, B clock zone circuit working just often, no matter when data output A changes (change frequency is less than the B clock frequency), all the time can correctly be sampled by the B clock zone (dotted line waveform of data output B among Fig. 3), but, if resetting to lose efficacy, the B in the B clock zone lags behind the variation moment of data output A constantly, can cause B clock zone circuit can't correctly sample data output A at reset period, thus obliterated data (solid line waveform of data output B among Fig. 3).
This situation is uncontrollable causing constantly because the reset signal of each clock zone lost efficacy.
In sum, general reset circuit has following problem:
When 1, there is burr in reset signal, can cause resetting that system do not expect;
When 2, reset signal is present in data path, can make data path sequential variation;
3, at the emulation initial stage, uncertain value may appear in trigger;
4, when reset signal at clock effectively when annex lost efficacy, can cause that the output of trigger is metastable state;
5, reset signal moment of losing efficacy uncontrollable, the time that arrives different triggers sometimes is inconsistent, can cause the trigger reset time in the circuit inconsistent;
6, during clock zone system reset, may have data transmission fault.
Summary of the invention
Technical matters to be solved by this invention be the reset signal that exists of prior art when burr system do not expect reset, the data path sequential deterioration when reset signal is present in data path, the uncertain value of trigger that the emulation initial stage exists, moment that reset signal lost efficacy are uncontrollable, the shortcomings such as data transmission fault during clock zone system reset, in the hope of proposing a kind of multi-clock domain system reset circuit that can overcome the prior art shortcoming.
Multi-clock domain system reset circuit proposed by the invention comprises:
Signal lag part;
The single output of dual input with door 1;
The main controller clock trigger 1 of asynchronous reset type, the main controller clock trigger 2 of asynchronous reset type;
The pair control clock trigger 1 of asynchronous reset type, the pair control clock trigger 2 of asynchronous reset type;
The controlled time trigger 1 of asynchronous reset type, the controlled time trigger 2 of asynchronous reset type;
The input of signal lag part connects external reset signal; Be connected external reset signal with an input end of door 1, another input end connects the output terminal of signal lag part;
The clock end of controlled time trigger 1 connects the Be Controlled clock signal, and signal input part connects high level, and the asynchronous reset end connects the output terminal with door 1; The clock end of controlled time trigger 2 connects the Be Controlled clock signal, and signal input part connects the output terminal of controlled time trigger 1, and the asynchronous reset end connects the output terminal with door 1, and signal output part is as the Be Controlled clock zone reset signal of circuit;
The clock end auxiliary connection control clock signal of pair control clock trigger 1, signal input part connect Be Controlled clock zone reset signal, and the asynchronous reset end connects the output terminal with door 1; The clock end auxiliary connection control clock signal of pair control clock trigger 2, signal input part connects the output terminal of pair control clock trigger 1, and the asynchronous reset end connects the output terminal with door 1, and signal output part is as the sub-control clock zone reset signal of circuit;
The clock end of main controller clock trigger 1 connects the main control clock signal, signal input part auxiliary connection control clock zone reset signal, and the asynchronous reset end connects the output terminal with door 1; The clock end of main controller clock trigger 2 connects the main control clock signal, and signal input part connects the output terminal of main controller clock trigger 1, and the asynchronous reset end connects the output terminal with door 1, and signal output part is as the main control clock zone reset signal of circuit.
Described delay unit comprises the impact damper of some, and described impact damper is by the sequence number serial arrangement, and the output that forms the low impact damper of sequence number connects the input of the high impact damper of sequence number;
The burr width of external reset signal and the transmission speed of impact damper have determined the number of impact damper.
Described reset circuit is applicable to the system that multi-clock zone is worked simultaneously.
Described reset circuit is applicable to the SOC chip.
Asynchronous reset signal synchronization function of the present invention combines the advantage of synchronous reset and asynchronous reset, has eliminated both shortcomings, simultaneously, has solved the multi-clock zone system: the disorderly possibility of reseting stage data transmission possibility:
1, adopted burr to suppress circuit, made system insensitive to the burr of external reset signal, system can improperly not reset;
2, systematic reset signal belongs to the asynchronous reset type, and irrelevant with data path, the transmission path of data path can be long in the system;
3, systematic reset signal belongs to the asynchronous reset type, and at the emulation initial stage, trigger output uncertain value can not occur;
4, systematic reset signal is exported behind two triggers, can not be metastable state;
5, systematic reset signal is handled through clock synchronisation, effective edge at clock changes, and therefore, the reset signal transmission path can be long, the reset signal path transmission time under the prerequisite of 1 clock period, each trigger resetted in the same clock period;
Data transmission disorder when 6, the reseting sequence function of different clock-domains is eliminated multi-clock domain system reset, the correctness of reseting stage data transmission is guaranteed that by reset circuit modular circuit deviser only need consider the correctness that normal working hours are reportedly defeated and needn't be concerned about the data transmission correctness that how to guarantee reseting stage.
Description of drawings
Fig. 1 is typical synchronous reset circuit diagram;
Fig. 2 is typical asynchronous reset circuit figure;
Fig. 3 is multi-clock zone exchanges data circuit and system reset stage signal oscillogram;
Fig. 4 is a single clock domain system reset circuit;
Fig. 5 is a multi-clock domain system reset circuit.
Embodiment
This reset circuit is divided into 3 parts:
1, reset signal deburring part;
2, asynchronous reset synchronization part;
3, reset signal is changed part in proper order.
Below in conjunction with accompanying drawing, the present invention done describing in further detail.
Fig. 4 is a single clock domain system reset circuit.
Device in Fig. 4 circuit comprise some impact damper (impact damper 1, impact damper 2 ..., impact damper N), number of buffers is according to the transmission speed decision of the impact damper that adopts among the burr width of external reset signal in the practical application and the ASIC), the single output type of dual input with the trigger 1 of door 1, asynchronous reset type, the trigger 2 of asynchronous reset type.
All impact dampers (impact damper 1, impact damper 2 ..., impact damper N) by the sequence number serial arrangement, the output of the impact damper that sequence number is low connects the input of the high buffering of sequence number, form one by importing connection impact damper 1, by the signal lag part that list import, list export of impact damper N as output.
The external signal of entire circuit is high level (input), clock signal (input), external reset signal (input), systematic reset signal (output).
The input of signal lag part connects external reset signal; Be connected external reset signal with an input end of door 1, another input end connects the output terminal of signal lag part; The clock end of trigger 1 connects clock signal, and signal input part connects high level, and the asynchronous reset end connects the output terminal with door 1; The clock end of trigger 2 connects clock signal, and signal input part connects the output terminal of trigger 1, and the asynchronous reset end connects the output terminal with door 1, and signal output part is as the systematic reset signal of circuit.
The multi-clock domain system reset circuit of Fig. 5 circuit on the basis of single clock domain system reset circuit, making up.
The device of Fig. 5 circuit comprises the impact damper (impact damper 1 of some, impact damper 2, impact damper N), number of buffers is according to the transmission speed decision of the impact damper that adopts among the burr width of external reset signal in the practical application and the ASIC), the single output of dual input with door 1, the A clock zone trigger 1 of asynchronous reset type, the A clock zone trigger 2 of asynchronous reset type, the B clock zone trigger 1 of asynchronous reset type, the B clock zone trigger 2 of asynchronous reset type, the C clock zone trigger 1 of asynchronous reset type, the C clock zone trigger 2 of asynchronous reset type.
All impact dampers (impact damper 1, impact damper 2 ..., impact damper N) by the sequence number serial arrangement, the output of the impact damper that sequence number is low connects the input of the high buffering of sequence number, form one by importing connection impact damper 1, by the signal lag part that list import, list export of impact damper N as output.
The external signal of entire circuit is high level (input), A clock signal (input), B clock signal (input), C clock signal (input), external reset signal (input), A clock zone reset signal (output), B clock zone reset signal (output), C clock zone reset signal (output).
The input of signal lag part connects external reset signal; Be connected external reset signal with an input end of door 1, another input end connects the output terminal of signal lag part; The clock end of C clock zone trigger 1 connects the C clock signal, and signal input part connects high level, and the asynchronous reset end connects the output terminal with door 1; The clock end of C clock zone trigger 2 connects the C clock signal, and signal input part connects the output terminal of C clock zone trigger 1, and the asynchronous reset end connects the output terminal with door 1, and signal output part is as the C clock zone reset signal of circuit;
The clock end of B clock zone trigger 1 connects the B clock signal, and signal input part connects C clock zone reset signal, and the asynchronous reset end connects the output terminal with door 1; The clock end of B clock zone trigger 2 connects the B clock signal, and signal input part connects the output terminal of B clock zone trigger 1, and the asynchronous reset end connects the output terminal with door 1, and signal output part is as the B clock zone reset signal of circuit;
The clock end of A clock zone trigger 1 connects the A clock signal, and signal input part connects B clock zone reset signal, and the asynchronous reset end connects the output terminal with door 1; The clock end of A clock zone trigger 2 connects the A clock signal, and signal input part connects the output terminal of A clock zone trigger 1, and the asynchronous reset end connects the output terminal with door 1, and signal output part is as the A clock zone reset signal of circuit;
In Fig. 4 circuit, act on the asynchronous reset end of trigger 1, trigger 2 by the external reset _ no burr signal of external reset signal generation, the reset values of systematic reset signal is 0, external reset signal lost efficacy after (drawing high), through two clock period, in rising edge of clock signal, systematic reset signal is drawn high.
Systematic reset signal is exported behind two triggers by high level signal, can remove metastable state like this.
External reset _ no burr signal is produced by external reset signal, and postpone certain hour (the concrete time is according to the lag characteristic of used impact damper, the decision of used quantity), even there is tiny shake in external signal like this, but external reset signal and external reset _ inhibit signal with after output external reset _ no burr signal stable, no burr.
The multi-clock domain system reset circuit of Fig. 5 on the basis of single clock domain system reset circuit, constructing, in this circuit, secondly the pull-up at first of C clock zone reset signal is B clock zone reset signal, be A clock zone reset signal once more, like this can the strict reseting sequence of controlling each clock zone.
The B clock zone resets when finishing, and C clock zone circuit is operate as normal; The A clock zone resets when finishing, and B clock zone, C clock zone circuit be operate as normal, so just needn't worry when total system resets C clock zone circuit sampling less than the signal of B clock zone, and C clock zone, B clock zone circuit sampling are less than the signal of A clock zone.
This mode is applicable to when resetting, the system that multi-clock zone is worked simultaneously, and wherein the A clock zone is as the clock of master control system, and B is as the clock of secondary control system, and C is as the clock of Be Controlled system.
This repositioning method is applied in the SOC chip.
Total uart_clk, spi_clk, 32k_clk, engine_clk, a h_clk6 clock in the SOC chip system belong to typical multi-clock zone system.
Comprehensive above to synchronous reset, asynchronous reset strengths and weaknesses analysis, the reset circuit in the system adopts external reset signal as asynchronous reset, produces the reset signal of each clock zone synchronously.
Data transmission between each clock zone of each SOC system can be made handshake method in theory, but because total system is too big, divide many people's exploitations, and the location of SOC system is to accelerate the design cycle by the mode that increases module, can not get rid of in the module of exploitation and the module of increase to exist data directly to transmit the mode of (slow clock zone data do not need to shake hands to fast clock zone data transmission).Based on this reason, reset mode is fit to adopt sequential system.
In conjunction with the characteristics of SOC system, in each clock zone, h_clk clock zone circuit belongs to master control system, and other clock zone circuit belongs to controlled system, as long as guarantee the last generation of the reset signal of h_clk clock zone.So, adopt each clock zone reset signal to produce separately separately, the last mode that produces of h_clk clock zone reset signal.
Claims (4)
1, a kind of multi-clock domain system reset circuit is characterized in that, comprising:
Signal lag part;
The single output of dual input with door (1);
The main controller clock trigger (2) of the main controller clock trigger of asynchronous reset type (1), asynchronous reset type;
The pair control clock trigger (2) of the pair control clock trigger of asynchronous reset type (1), asynchronous reset type;
The controlled time trigger (2) of the controlled time trigger of asynchronous reset type (1), asynchronous reset type;
The input of signal lag part connects external reset signal; Be connected external reset signal with an input end of door (1), another input end connects the output terminal of signal lag part;
The clock end of controlled time trigger (1) connects the Be Controlled clock signal, and signal input part connects high level, and the asynchronous reset end connects the output terminal with door (1); The clock end of controlled time trigger (2) connects the Be Controlled clock signal, signal input part connects the output terminal of controlled time trigger (1), the asynchronous reset end connects the output terminal with door (1), and signal output part is as the Be Controlled clock zone reset signal of circuit;
The clock end auxiliary connection control clock signal of pair control clock trigger (1), signal input part connect Be Controlled clock zone reset signal, and the asynchronous reset end connects the output terminal with door (1); The clock end auxiliary connection control clock signal of pair control clock trigger (2), signal input part connects the output terminal of pair control clock trigger (1), the asynchronous reset end connects the output terminal with door (1), and signal output part is as the sub-control clock zone reset signal of circuit;
The clock end of main controller clock trigger (1) connects the main control clock signal, signal input part auxiliary connection control clock zone reset signal, and the asynchronous reset end connects the output terminal with door (1); The clock end of main controller clock trigger (2) connects the main control clock signal, signal input part connects the output terminal of main controller clock trigger (1), the asynchronous reset end connects the output terminal with door (1), and signal output part is as the main control clock zone reset signal of circuit.
2, multi-clock domain system reset circuit as claimed in claim 1 is characterized in that:
Described delay unit comprises the impact damper of some, and described impact damper is by the sequence number serial arrangement, and the output that forms the low impact damper of sequence number connects the input of the high impact damper of sequence number;
The burr width of external reset signal and the transmission speed of impact damper have determined the number of impact damper.
3, multi-clock domain system reset circuit as claimed in claim 1 or 2 is characterized in that:
Described reset circuit is applicable to the system that multi-clock zone is worked simultaneously.
4, multi-clock domain system reset circuit as claimed in claim 3 is characterized in that:
Described reset circuit is applicable to the SOC chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100985606A CN100392560C (en) | 2005-09-02 | 2005-09-02 | Multi-clock domain system reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100985606A CN100392560C (en) | 2005-09-02 | 2005-09-02 | Multi-clock domain system reset circuit |
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| CN1924758A true CN1924758A (en) | 2007-03-07 |
| CN100392560C CN100392560C (en) | 2008-06-04 |
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| CNB2005100985606A Expired - Fee Related CN100392560C (en) | 2005-09-02 | 2005-09-02 | Multi-clock domain system reset circuit |
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| CN101359904B (en) * | 2008-07-25 | 2010-06-02 | 北京航空航天大学 | Multipath insulated resetting circuit preventing constant reset |
| CN102347748A (en) * | 2011-06-01 | 2012-02-08 | 杭州万工科技有限公司 | Reset signal processing method for system on-chip |
| CN102487273A (en) * | 2010-12-01 | 2012-06-06 | 航天科工惯性技术有限公司 | Reset circuit of anti-fuse type FPGA (Field Programmable Gate Array) system |
| CN102571050A (en) * | 2010-12-31 | 2012-07-11 | 中国航空工业集团公司第六三一研究所 | Reset circuit for multi-clock domains |
| CN104143974A (en) * | 2013-05-08 | 2014-11-12 | 博通集成电路（上海）有限公司 | Phase-locked loop circuit and method for phase-locked loop circuit |
| CN104345849A (en) * | 2013-08-07 | 2015-02-11 | 京微雅格（北京）科技有限公司 | Method and circuit for generating power-on reset signal |
| CN104516997A (en) * | 2013-09-30 | 2015-04-15 | 瑞昱半导体股份有限公司 | Time sequence analyzing method and machine redable medium |
| CN111478685A (en) * | 2020-03-17 | 2020-07-31 | 普联技术有限公司 | Power-on anti-shake circuit and electronic equipment |
| CN111857304A (en) * | 2020-07-28 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip reset control method, device, equipment and storage medium |
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| FI104858B (en) * | 1995-05-29 | 2000-04-14 | Nokia Networks Oy | Method and apparatus for adapting an asynchronous bus to a synchronous circuit |
| KR100562496B1 (en) * | 2002-12-16 | 2006-03-21 | 삼성전자주식회사 | Semiconductor device with reset and clock regenerating circuit, high-speed digital system incorporating the same, and method of regenerating reset and clock signals |
| KR20050115227A (en) * | 2003-01-23 | 2005-12-07 | 유니버시티 오브 로체스터 | Multiple clock domain microprocessor |
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- 2005-09-02 CN CNB2005100985606A patent/CN100392560C/en not_active Expired - Fee Related
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| CN101359904B (en) * | 2008-07-25 | 2010-06-02 | 北京航空航天大学 | Multipath insulated resetting circuit preventing constant reset |
| CN102487273A (en) * | 2010-12-01 | 2012-06-06 | 航天科工惯性技术有限公司 | Reset circuit of anti-fuse type FPGA (Field Programmable Gate Array) system |
| CN102487273B (en) * | 2010-12-01 | 2014-06-18 | 航天科工惯性技术有限公司 | Reset circuit of anti-fuse type FPGA (Field Programmable Gate Array) system |
| CN102571050A (en) * | 2010-12-31 | 2012-07-11 | 中国航空工业集团公司第六三一研究所 | Reset circuit for multi-clock domains |
| CN102571050B (en) * | 2010-12-31 | 2014-08-20 | 中国航空工业集团公司第六三一研究所 | Reset circuit for multi-clock domains |
| CN102347748A (en) * | 2011-06-01 | 2012-02-08 | 杭州万工科技有限公司 | Reset signal processing method for system on-chip |
| CN104143974A (en) * | 2013-05-08 | 2014-11-12 | 博通集成电路（上海）有限公司 | Phase-locked loop circuit and method for phase-locked loop circuit |
| CN104345849B (en) * | 2013-08-07 | 2018-01-09 | 京微雅格（北京）科技有限公司 | A kind of method and its circuit for generating power-on reset signal |
| CN104345849A (en) * | 2013-08-07 | 2015-02-11 | 京微雅格（北京）科技有限公司 | Method and circuit for generating power-on reset signal |
| CN104516997A (en) * | 2013-09-30 | 2015-04-15 | 瑞昱半导体股份有限公司 | Time sequence analyzing method and machine redable medium |
| CN111478685A (en) * | 2020-03-17 | 2020-07-31 | 普联技术有限公司 | Power-on anti-shake circuit and electronic equipment |
| CN111478685B (en) * | 2020-03-17 | 2024-04-02 | 上海联虹技术有限公司 | Power-on anti-shake circuit and electronic equipment |
| CN111857304A (en) * | 2020-07-28 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip reset control method, device, equipment and storage medium |
| CN111857304B (en) * | 2020-07-28 | 2022-03-22 | 山东云海国创云计算装备产业创新中心有限公司 | Chip reset control method, device, equipment and storage medium |
| CN112035385A (en) * | 2020-08-04 | 2020-12-04 | 广东安朴电力技术有限公司 | Method for reestablishing link of SRIO communication system, storage medium and SRIO communication system |
| CN114942687A (en) * | 2022-05-17 | 2022-08-26 | 上海芯钛信息科技有限公司 | Reset safety mechanism based on monitoring, realization method and reset circuit |
| CN114942687B (en) * | 2022-05-17 | 2024-04-05 | 上海芯钛信息科技有限公司 | Reset safety mechanism based on monitoring, implementation method and reset circuit |
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