CN102495818A

CN102495818A - Method for improving communication speed rate of software-mode serial peripheral interface (SPI)

Info

Publication number: CN102495818A
Application number: CN2011104071591A
Authority: CN
Inventors: 陈诚; 陈玲
Original assignee: SHANGHAI AISINO CHIP ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: SHANGHAI AISINO CHIP ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2011-12-09
Filing date: 2011-12-09
Publication date: 2012-06-13

Abstract

The invention discloses a method for improving the communication speed rate of a software-mode serial peripheral interface (SPI). Based on the operation of a direct memory access (DMA), data are directly input from a memory to a general purpose input output (GPIO) data register in a mode of non-interference of a central processing unit (CPU). The communication speed rate depends on the data transportation data of the DMA and the overturning speed of the GPIO instead of the performance of the CPU. Therefore, the communication speed rate of the software-mode SPI can be greatly improved, and the working efficiency of a system is improved.

Description

A kind of method that improves software mode SPI traffic rate

Technical field

The present invention relates to a kind of method that improves software mode SPI traffic rate, being particularly useful for clock rate has the upper limit or product chips selected, and circuit structure is the system of malleable not.

Background technology

The full name of SPI interface is " Serial Peripheral Interface ", means SPI, be a kind of high speed, full duplex, synchronous communication bus, and line is simple, saves circuit space, has obtained in recent years using very widely.

In the SPI communication at present, it is that mode (promptly producing high-low level through GPIO (general input and output) port) simulation SPI communication protocol and the slave unit that main frame adopts software communicates that application is greatly arranged.Especially some usually not integrated SPI modules among the general single chip controller chip MCU of low sides relatively, main frame is just more general with the application mode of software mode simulation SPI port.

Fig. 1 is the synoptic diagram of the present software mode SPI method that generally adopts; The software mode SPI communication of generally adopting at present is that the mode that at first SPI communication data to be sent is compared through CPU by turn converts serial data (0/1) to; Drive and data-driven (upset of GPIO port) at the clock that the GPIO port produces SPI communication needs according to serial data then; This whole process need is accomplished under CPU control, has taken a large amount of cpu resources.

This method is convenient feasible, and the requirement of having saved the integrated SPI module of controller has also reduced hardware cost, has shortened the construction cycle.But need a large amount of CPU processing time of cost owing on the GPIO port, produce upset through software mode simulation SPI communication; The fastest traffic rate of system is subject to system works frequency and CPU handling property; Communication speed is difficult to improve, and becomes the bottleneck of this application mode.

Summary of the invention

The invention provides a kind of method that improves software mode SPI traffic rate, improved the work efficiency of software mode SPI traffic rate and system greatly.

In order to achieve the above object, the present invention provides a kind of method that improves software mode SPI traffic rate, comprises following steps:

Step 1, the single-chip microprocessor MCU system is carried out initialization;

Step 2, setting SPI communications protocol;

Step 3, foundation are used for SPI data parsing to be sent is become the parsing array [0-f] of GPIO port driver data;

Step 4, SPI data to be sent are resolved to the driving array that is used to drive the GPIO port through the parsing array in the step 3;

Step 5, be that the DMA transmission creates continuous memory block;

Step 6, dma module is correctly disposed, for the SPI data are sent ready;

Step 7, startup DMA transmission, the SPI data communication waveform of generation software simulation on the GPIO port;

Whether step 8, inspection data to be sent have all been sent and have been accomplished, and accomplish then program withdraws from if send, and begin data transmission next time otherwise return step 4 preparation.

In the described step 1, initialization comprises configuration preloading, configurable clock generator frequency, interrupts being provided with, disposing Peripheral Interface GPIO and dma module.

In the described step 2, the rising edge or the negative edge that are set at system clock CLK read the data on the SPI data line MOSI line, the data of set sending be the LSB low level formerly or the MSB uimsbf unsigned integer most significant bit first.

In the described step 3, resolve array [0-f] and be specifically designed to a mapping method that SPI data conversion to be sent is become GPIO port driver data.

In the described step 5, the memory block is created among the SRAM SRAM.

In the described step 6, enable dma module and DMA and interrupt, byte of every transmission can produce one and accomplish interruption, and then sends another byte through the parsing array list of looking in the step 3.

The present invention has improved the work efficiency of software mode SPI traffic rate and system greatly.

Description of drawings

Fig. 1 is the synoptic diagram of software mode SPI method in the background technology;

Fig. 2 is the module frame chart of general single chip controller chip MCU;

Fig. 3 is a functional schematic of the present invention;

Fig. 4 is a process flow diagram of the present invention;

Fig. 5 is the oscillogram that the present invention is verified.

Embodiment

Following according to Fig. 2～Fig. 5, specify preferred embodiment of the present invention.Wherein Fig. 2 has provided the module frame chart of a general MCU, comprises CPU, read only memory ROM, SRAM SRAM, flash memory Flash, universal input/output interface GPIO, UART Universal Asynchronous Receiver Transmitter UART, SPI SPI, DASD DMA, timer TIMER and watchdog circuit Watchdog etc.In plurality of applications, except the SPI interface module of using single-chip microprocessor MCU to carry, also can simulate other universal serial bus through GPIO, realize some function like the SPI interface.

Simulation universal serial bus among the common MCU; Like SPI, adopt CPU control GPIO mode, efficient and performance are lower; The present invention proposes a kind of method that improves software mode SPI traffic rate; Based on dma operation, under the mode of not intervening through CPU, with data directly from memory write to the GPIO data register.

Direct Memory Access (DASD) is a kind of high-speed data transmission operation; Allow direct read data between external apparatus and the storer; Neither pass through CPU; Also do not need CPU to intervene, whole data transfer operation carries out under a module controls that is called " dma controller ".CPU is except doing some work of treatment when data transmission begins and finish, CPU can proceed other work in communication process.Like this, in the most of the time, CPU and DMA, GPIO module are in parallel work-flow, and traffic rate no longer depends on the system works frequency, but by the speed of DMA carrying data and the reversal rate decision of GPIO.Therefore, the traffic rate of software SPI can improve greatly, and system works efficient also is improved.

Fig. 3 is the present invention residing position in the SPI communications applications; Be that the present invention is the improvement to software mode simulation SPI method; Can replace the SPI sending module to realize that the high speed SPI data send, and can under the constant situation of system clock, improve the traffic rate that software mode SPI sends.

As shown in Figure 4, the present invention provides a kind of method that improves software mode SPI traffic rate, comprises following steps:

Usually the MCU system initialization comprises configuration preloading, configurable clock generator frequency (like 48MHz), interrupts being provided with, and the initialization of part Peripheral Interface;

Among the present invention, Peripheral Interface has used GPIO and DMA, so need GP configuring IO and dma module;

Step 2, setting SPI communications protocol;

The rising edge of system clock CLK reads the data on the SPI data line MOSI line, and low level formerly;

The present invention is modeled as example with SPI; The SPI interface has 4 signal: MOSI (master goes out from going into); MISO (master goes into from going out), CLK (SPI clock), SS (slave unit selection); May be prescribed as in the SPI agreement at CLK rising edge or negative edge and read the data on the MOSI line, the data that also can select to send be LSB (low level) formerly or MSB (high position) formerly;

This is resolved array [0-f] and is specifically designed to a mapping method that SPI data conversion to be sent is become GPIO port driver data, is that the DMA carrying is carried out a pretreated committed step to data to be sent before, and the step of setting up this array is following:

Simulation SPI sends 4bit data 0000b, and the GPIO data register (is supposed GPIO totally 8 pins, used the 3rd, No. 4 pin of GPIO in the embodiments of the invention, be respectively clock line CCK, data line MOSI; If 0x00 representes 8 pins outputs of GPIO, can see and have only the 3rd, No. 4 signal in the present embodiment in upset) data that should write in proper order are: 0x00,0x04; 0x00,0x04,0x00; 0x04,0x00,0x04; For small end MCU, the source data that DMA source data district store when using the word mode to visit is 0x04000400,0x04000400; And for big end MCU, the source data that DMA source data district store when using the word mode to visit is 0x00040004,0x00040004.Sending 1-f can analogize, and creates parsing array that DMA simulation SPI sends 4bit (0-f) table look-up as follows (0x00-0xff can be combined by following table, and following table is an example with small end MCU):

DMA transmits data	The SPI output data
		0x04000400,0x04000400	0x0
0x04000400,0x0c080400	0x1
		0x04000400,0x04000c08	0x2
0x04000400,0x0c080c08	0x3
		0x0c080400,0x04000400	0x4
0x0c080400,0x0c080400	0x5
		0x0c080400,0x04000c08	0x6
0x0c080400,0x0c080c08	0x7
		0x04000c08,0x04000400	0x8
0x04000c08,0x0c080400	0x9
		0x04000c08,0x04000c08	0xa
0x04000c08,0x0c080c08	0xb
		0x0c080c08,0x04000400	0xc
0x0c080c08,0x0c080400	0xd
		0x0c080c08,0x04000c08	0xe
0x0c080c08,0x0c080c08	0xf

Utilize the parsing array in the step 3; The resolution table that data to be sent (0x00-0xff) are obtained with step 3 converts the data (can adopt lookup table mode) of actual transmission to, is exactly [0x0c080400,0x0c080c08 such as the driving data of sending 0x78; 0x7; 0x04000c08,0x04000400,0x8].0x00-0xff is splitted into the combination of 0x0-0xf, and purpose is the size for the parsing array that reduces storage.

Step 5, be that the DMA transmission creates continuous memory block;

This memory block is created among the SRAM SRAM (memory module that MCU has), and data (being the form in the step 3) after the storing and resolving continuously in SRAM SRAM are for the DMA carrying is prepared;

Step 6, dma module is correctly disposed, for the SPI data are sent ready:

Enable dma module and DMA and interrupt, byte of every transmission can produce one and accomplish interruption, and then sends another byte through the table of looking in the step 3;

The technical scheme that the present invention adopts is based on built-in DMA controller (DMAC) and the GPIO module that general MCU provides, under not through the mode of CPU intervention with data directly from memory write to the GPIO data register.Pass through analysis protocol efficiently simultaneously, the assurance communication data can be simulated SPI communication protocol thereby can produce correct port driver through dma mode by fast resolving and correct tissue.

Fig. 5 is the GPIO port upset waveform that this method is verified, can know that by waveform the drive waveforms that the GPIO port produces meets the requirement of SPI communication protocol fully, can realize software SPI communication function.

By A-T in Fig. 5 frame; The A-B chronometric data can be known; The byte transmission speed that produces software simulation SPI waveform through hardware resource combination in the chip of this paper proposition is about 1us/byte; Be 8M bps, and the transmission speed that produces software simulation SPI waveform by MCU under the identical systems clock condition is about 1M bps, traffic rate improves more than 8 times.

The invention solves the technological difficulties that run in software simulation SPI communication at present, provide and utilize in the chip hardware resource combination under the constant condition of system clock and then realize more high-performance and more the SPI delivery plan of rapid rate.Can solve the application bottleneck of software simulation SPI mode.Through above technology, can under the constant situation of system clock, promote more than 8 times the transmission rate of software simulation SPI.

Although content of the present invention has been done detailed introduction through above-mentioned preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be conspicuous.Therefore, protection scope of the present invention should be limited appended claim.

Claims

1. method that improves software mode SPI traffic rate is characterized in that the method includes the steps of:

Step 2, setting SPI communications protocol;

Step 5, be that the DMA transmission creates continuous memory block;

Step 6, dma module is correctly disposed, for the SPI data are sent ready;

2. the method for raising software mode SPI traffic rate as claimed in claim 1 is characterized in that, in the described step 1, initialization comprises configuration preloading, configurable clock generator frequency, interrupts being provided with, disposing Peripheral Interface GPIO and dma module.

3. the method for raising software mode SPI traffic rate as claimed in claim 1; It is characterized in that; In the described step 2; The rising edge or the negative edge that are set at system clock CLK read the data on the SPI data line MOSI line, the data of set sending be the LSB low level formerly or the MSB uimsbf unsigned integer most significant bit first.

4. the method for raising software mode SPI traffic rate as claimed in claim 1 is characterized in that, in the described step 3, resolves array [0-f] and is specifically designed to a mapping method that SPI data conversion to be sent is become GPIO port driver data.

5. the method for raising software mode SPI traffic rate as claimed in claim 1 is characterized in that in the described step 5, the memory block is created among the SRAM SRAM.

6. the method for raising software mode SPI traffic rate as claimed in claim 1; It is characterized in that, in the described step 6, enable dma module and DMA and interrupt; Byte of every transmission can produce one and accomplish interruption, and then sends another byte through the parsing array list of looking in the step 3.