CN101359904B - Multipath insulated resetting circuit preventing constant reset - Google Patents
Multipath insulated resetting circuit preventing constant reset Download PDFInfo
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- CN101359904B CN101359904B CN2008101172230A CN200810117223A CN101359904B CN 101359904 B CN101359904 B CN 101359904B CN 2008101172230 A CN2008101172230 A CN 2008101172230A CN 200810117223 A CN200810117223 A CN 200810117223A CN 101359904 B CN101359904 B CN 101359904B
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Abstract
The invention discloses a multi-channel isolating reset circuit for preventing constant resetting, and the reset circuit is connected between an upper computer and a lower computer for implementing the system resetting to the lower computer; the reset circuit is composed of a power-on-reset branch circuit, a first external reset branch circuit, a second external reset branch circuit and a three value and gate; and the power-on-reset branch circuit is composed of an RC circuit, an inverter A and an inverter B, the first external reset branch circuit consists of a negative pulse sensitive circuit A and an inverter C, and the second external reset branch circuit consists of a negative pulse sensitive circuit B and an inverter D. The three value and gate operates a system power-on-reset signalA0, an output signal A1 of the first external reset branch circuit and an output signal A2 of the second external reset branch circuit that are received and outputs a reset signal f3 with low level and effective properties to a lower circuit. The multi-channel external reset signal can independently realize the resetting of the lower computer system through the designed reset circuit, and can still ensure the normal resetting of the lower computer when the constant resetting takes place on the external reset signal of a certain channel.
Description
Technical field
The present invention relates to a kind of reset circuit, more particularly says, is meant a kind ofly can isolate reset circuit mutually to a kind of multichannel that prevents that perseverance from resetting that the multichannel reset signal is handled.
Background technology
In the digital application system,, make system's cisco unity malfunction because program " race flies " or " deadlock " phenomenon usually can appear in the factor of disturbing or the fault of hardware device.In order to address this problem, generally in digital system, adopt external reset (as house dog) means.
The integrated monitoring and reset chip of many employings is monitored the power supply of digital system and is finished and resets in the practical application, and this monitoring and reset chip can only guarantee that generally the interference of digital system power supply does not produce the digital system mistake and resets.Another kind is to introduce external reset by the series connection control mode of watchdog circuit control electrify restoration circuit.When house dog perseverance occurs and resets, will cause the digital system perseverance to reset and cisco unity malfunction.
In the middle of spacecraft field and part civil area, because some digital system that relates to significant components re-powers number of times and is subjected to strict restriction, so except needs digital system possesses power-on reset signal, also to introduce reseting controling signal, thereby digital system is resetted under the prerequisite of not cutting off the power supply in the digital system outside.On the other hand, for increasing the reliability of digital system, external reset signal has more than one the tunnel usually.And have only the digital system of a reseting pin for some, power-on reset signal with from the reset signal of outside with a shared reseting pin.So far, except that requiring electrification reset, the digital system that makes that also requires not interfere with each other between each the road reset signal from the outside resets, simultaneously when a certain road external reset signal perseverance occurs and resets, can not cause digital system perseverance to occur and reset, and not influence normally resetting of other each road reset signal.
Summary of the invention
The purpose of this invention is to provide a kind of multichannel that prevents that perseverance from resetting and isolate reset circuit mutually, this reset circuit is made up of with door electrification reset branch road, the first external reset branch road, the second external reset branch road and three inputs, be on the basis of original electrify restoration circuit, to have expanded to prevent that the perseverance of multichannel external input signal from resetting, and have the branch road that resets of isolation features.The multichannel external reset signal can independently realize resetting of lower computer system by reset circuit of the present invention, has mutual buffer action between the multichannel external reset signal, and after a certain road external reset signal generation perseverance resets, still can guarantee normally resetting of lower computer system.
The present invention is that a kind of multichannel that prevents that perseverance from resetting is isolated reset circuit mutually, and this reset circuit is connected between master system and the lower computer system, is used for lower computer system is carried out system reset; This reset circuit is made up of with door electrification reset branch road, the first external reset branch road, the second external reset branch road and three inputs;
Described electrification reset props up route RC circuit, A inverter, B inverter formation, the original reset signal V of RC circuit output
1The inversion signal V first time that output has the high level characteristic after the A inverter carries out anti-phase the processing
2, inversion signal V for the first time
2The system power-on reset signal A that output has the low level characteristic after the B inverter is handled
0To three inputs and door;
The described first external reset branch road receives the first via external reset signal f of master system output
1, first via external reset signal f
1Output A road sensitive signal V after A negative pulse sensitive circuit discharges and recharges capacitance
3, A road sensitive signal V
3The first external reset branch output signal A that output has the low level characteristic after the C inverter carries out anti-phase the processing
1To three inputs and door;
The described second external reset branch road receives the second tunnel external reset signal f of master system output
2, the second tunnel external reset signal f
2Output B road sensitive signal V after B negative pulse sensitive circuit discharges and recharges capacitance
4, B road sensitive signal V
4The second external reset branch output signal A that output has the low level characteristic after the D inverter carries out anti-phase the processing
2To three inputs and door;
Described three inputs and the system power-on reset signal A of door to receiving
0, the first external reset branch output signal A
1, the second external reset branch output signal A
2Carry out with calculation process after output have the reset signal f of low level available characteristic
3Give lower computer system.
The present invention prevents that multichannel that perseverance resets from isolating the characteristics of reset circuit mutually and being: (1) this circuit can be to playing good buffer action between the first external reset branch road, the second external reset branch input signal, make the external reset branch road of winning, the second external reset branch road can not produce interference each other, guarantee that lower computer system is more reliable.Externally input signal is permanent for (2) the first external reset branch roads and the second external reset branch road when be low level, has the permanent reset capability of resisting, and has guaranteed the operate as normal of lower computer system effectively.(3) reset circuit simplicity of design adopts analog circuit to build, and the main devices that relates to has only four Schmidt trigger SN74AHCT1G14, three input and door SN54ALS11A, four diode 2CK84F and five resistance, three electric capacity; (4) be easy to expand to adapt to the demand of multichannel external signal.(5) electrification reset reliability height if supply voltage is near the reseting limit just, yet can not triggered upset repeatedly and causes lower computer system normally to reset because of supply voltage rises very slowly or exists noise to produce reset circuit on the power supply.
Description of drawings
Fig. 1 is that the present invention prevents that multichannel that perseverance resets from isolating the theory diagram of reset circuit mutually.
Fig. 2 is that the present invention prevents that multichannel that perseverance resets from isolating the circuit theory diagrams of reset circuit mutually.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
In Fig. 1, the present invention is that a kind of multichannel that prevents that perseverance from resetting is isolated reset circuit mutually and is made up of with door electrification reset branch road, the first external reset branch road, the second external reset branch road and three inputs;
Described electrification reset props up route RC circuit, A inverter, B inverter formation, the original reset signal V of RC circuit output
1The inversion signal V first time that output has the high level characteristic after the A inverter carries out anti-phase the processing
2, inversion signal V for the first time
2The system power-on reset signal A that output has the low level characteristic after the B inverter is handled
0To three inputs and door;
Route A negative pulse sensitive circuit is propped up in described first external reset, the C inverter constitutes, and the first external reset branch road receives the first via external reset signal f of upper circuit output
1, first via external reset signal f
1Output A road sensitive signal V after A negative pulse sensitive circuit discharges and recharges capacitance
3, A road sensitive signal V
3The first external reset branch output signal A that output has the low level characteristic after the C inverter carries out anti-phase the processing
1To three inputs and door;
Route B negative pulse sensitive circuit is propped up in described second external reset, the D inverter constitutes, and the described second external reset branch road receives the second tunnel external reset signal f of upper circuit output
2, the second tunnel external reset signal f
2Output B road sensitive signal V after B negative pulse sensitive circuit discharges and recharges capacitance
4, B road sensitive signal V
4The second external reset branch output signal A that output has the low level characteristic after the D inverter carries out anti-phase the processing
2To three inputs and door;
Described three inputs and the system power-on reset signal A of door to receiving
0, the first external reset branch output signal A
1, the second external reset branch output signal A
2Carry out with calculation process after the reset signal f of output low level available characteristic
3Give the next circuit.
In the present invention, master system can be reset controlling system and the watchdog circuit that PC+dsp processor and/or FPGA processor or single-chip microcomputer+ARM etc. form.
In the present invention, lower computer system can be the system that embedded chips such as dsp processor and/or FPGA processor or single-chip microcomputer+ARM constitute.
In Fig. 2, the RC circuit that first resistance R 1 is connected with first capacitor C 1 and constituted.
In Fig. 2, the first isolating diode D1, the second pull-up resistor R2, the second capacitance C2, the 4th pull down resistor R4, the 3rd protection diode D3 form A negative pulse sensitive circuit.The first via external reset signal f of the 1 termination master system output of the first isolating diode D1
1, 2 ends of the first isolating diode D1 and+be connected to the second pull-up resistor R2 between the 5V power supply (should+5V power supply can provide) by lower computer system, 2 ends of the first isolating diode D1 connect with 1 end of the second capacitance C2; Be connected to the 4th pull down resistor R4 between 2 ends of the second capacitance C2 and the simulation ground, 2 ends of the second capacitance C2 connect with 2 ends of C inverter U3; The 3rd protection diode D3 is connected on 2 ends of simulation ground and C inverter U3; The 3rd protection diode D3 can play the limited amplitude protection effect, makes the input peak value of C inverter U3 be not less than the forward conduction voltage drop of the 3rd protection diode D3, plays the operate as normal of protection C inverter U3.
In Fig. 2, the second isolating diode D2, the 3rd pull-up resistor R3, the 3rd capacitance C3, the 5th pull down resistor R5, the 4th protection diode D4 form B negative pulse sensitive circuit.The second tunnel external reset signal f of the 1 termination master system output of the second isolating diode D2
2, 2 ends of the second isolating diode D2 and+be connected to the 3rd pull-up resistor R3 between the 5V power supply (should+5V power supply can provide) by lower computer system, 2 ends of the second isolating diode D2 connect with 1 end of the 3rd capacitance C3; Be connected to the 5th pull down resistor R5 between 2 ends of the 3rd capacitance C3 and the simulation ground, 2 ends of the 3rd capacitance C3 connect with 2 ends of D inverter U4; The 4th protection diode D4 is connected on 2 ends of simulation ground and D inverter U4; The 4th protection diode D4 can play the limited amplitude protection effect, makes the input peak value of D inverter U4 be not less than the forward conduction voltage drop of the 4th protection diode D4, plays the operate as normal of protection D inverter U4.
In the present invention, A inverter U1, B inverter U2, C inverter U3 and D inverter U4 choose the Schmidt trigger of SN74AHCT1G14 model.Three inputs choose the SN54ALS11A model with door U5 with the door chip.Four diode D1, D2, D3 and D4 choose 2CK84F model diode.
The present invention prevents that multichannel that perseverance resets from isolating each terminal of reset circuit mutually and being connected to:
One, each terminal of electrification reset branch road is connected to: 2 ends of A inverter U1 and+be connected to first resistance R 1 between the 5V power supply (should+5V power supply can provide) by lower computer system, 2 ends of A inverter U1 are connected to first capacitor C 1 with simulating between the ground; 3 terminations of A inverter U1 simulation ground, 5 terminations of A inverter U1+5V power supply (should+5V power supply can provide) by lower computer system, 4 ends of A inverter U1 connect with 2 ends of B inverter U2 and (are used for and will have the inversion signal V first time of high level characteristic
2Export to B inverter U2);
3 terminations of B inverter U2 simulation ground, 5 terminations of B inverter U2+5V power supply (should+5V power supply can provide) by lower computer system, 4 ends of B inverter U2 connect with 2 ends of a U5 with three inputs and (are used for system power-on reset signal A
0Export to three inputs and door U5).
Two, each terminal of the first external reset branch road is connected to: the first via external reset signal f of the 1 termination master system output of the first isolating diode D1 in the A negative pulse sensitive circuit
1, 2 ends of the first isolating diode D1 and+be connected to the second pull-up resistor R2 between the 5V power supply (should+5V power supply can provide) by lower computer system, 2 ends of the first isolating diode D1 connect with 1 end of the second capacitance C2; Be connected to the 4th pull down resistor R4 between 2 ends of the second capacitance C2 and the simulation ground, 2 ends of the second capacitance C2 connect with 2 ends of C inverter U3; The 3rd protection diode D3 is connected on 2 ends of simulation ground and C inverter U3; 3 terminations of C inverter U3 simulation ground, 5 terminations of C inverter U3+5V power supply (should+5V power supply can provide) by lower computer system; 4 ends of C inverter U3 connect (the first external reset branch output signal A1 that is used for having the low level characteristic exports to three inputs and door U5) with 3 ends of door U5 with three inputs.
Three, each terminal of the second external reset branch road is connected to: the second tunnel external reset signal f of the 1 termination master system output of the second isolating diode D2 in the B negative pulse sensitive circuit
2, 2 ends of the second isolating diode D2 and+be connected to the 3rd pull-up resistor R3 between the 5V power supply (should+5V power supply can provide) by lower computer system, 2 ends of the second isolating diode D2 connect with 1 end of the 3rd capacitance C3; Be connected to the 5th pull down resistor R5 between 2 ends of the 3rd capacitance C3 and the simulation ground, 2 ends of the 3rd capacitance C3 connect with 2 ends of D inverter U4; The 4th protection diode D4 is connected on 2 ends of simulation ground and D inverter U4; The 4th protection diode D4 is connected on 2 ends of simulation ground and D inverter U4; 3 terminations of D inverter U4 simulation ground, 5 terminations of D inverter U4+5V power supply (should+5V power supply can provide) by lower computer system; 4 ends of D inverter U4 connect with 19 ends of door U5 with three inputs and (are used for and will have the second external reset branch output signal A of low level characteristic
2Export to three inputs and door U5).
Four, three inputs are connected to each end of door U5: three inputs connect with 4 ends of B inverter U2 with 2 ends of door U5, three inputs are connected with 4 ends of C inverter U3 with door 3 ends, three inputs connect with 4 ends of D inverter U4 with 19 ends of door U5, and the 18 ends output of three inputs and door U5 has the reset signal f of low level available characteristic
3The reset signal f of this low level available characteristic
3Be used for lower computer system is realized resetting.
The multichannel that prevents that perseverance from resetting of the present invention is isolated reset circuit mutually, constant T resetting time of electrification reset branch road
0Constant T resetting time with the first external reset branch road
1, the second external reset branch road constant T resetting time
2Be different, i.e. T
0≠ T
1, T
0≠ T
2, and T
1=T
2Constant T resetting time of electrification reset branch road
0Constant T resetting time more than or equal to 10 times of first external reset branch road
1(T
0〉=10T
1), perhaps more than or equal to constant T resetting time of 10 times the second external reset branch road
2(T
0〉=10T
2).So the first external reset branch road and/or the second external reset branch road reach stable state earlier than electrification reset branch road.
In the present invention, the electrification reset mechanism analysis is as follows:
When system powers on, in the electrification reset branch road+the 5V power supply gives first capacitor C 1 charging by first resistance R 1.Because the initial condition of first capacitor C, 1 both end voltage is zero, 2 ends of A inverter U1 are input as low level, behind A inverter U1 and B inverter U2, still are low level, and the electrification reset branch road is output as low level; Along with first capacitor C 1 continues charging, voltage between first capacitor C 1 and first resistance R 1 increases gradually, when surpassing A inverter U1 positive threshold (during 1V～2V), the output of A inverter U1 is by high step-down, uprised by low behind B inverter U2, after this because 1 charging of first capacitor C finishes, the level between first capacitor C 1 and first resistance R 1 can not be lower than the reverse threshold value (0.55V～1.55V) of A inverter U1, thus, the electrification reset branch road reaches stable state.
At the first external reset branch road not during reset mode, first via external reset signal f
1Be high level, because the first isolating diode D1 reversal connection, + 5V power supply charges to the second capacitance C2 by the second pull-up resistor R2, because the initial condition of the second capacitance C2 both end voltage is zero, 2 ends of C inverter U3 are input as low level, the 4 ends output high level of C inverter U3 is output as high level when promptly the first external reset branch road powers on.Along with the charging of the second capacitance C2, the 2 end incoming levels of C inverter U3 raise gradually, and the forward thresholding that surpasses C inverter U3 at last (is the attribute of C inverter U3 itself, is generally 1V～2V) make C inverter U3 be output as low.After second capacitance C2 charging finished, because the effect of the 4th pull down resistor R4,2 ends of C inverter U3 finally were pulled low level, so high level is got back in C inverter U3 output once more.Thus, the first external reset branch road reaches stable state.
The second external reset branch road is consistent with the first external reset branch road operation principle.But because the time constant of first, second external reset branch road so first, second external reset branch road at first reaches stable state, is promptly exported high level less than the electrification reset branch road.And the output of electrification reset branch road still is low level at this moment.After the effect through three inputs and door U5, three inputs are output as low level (this low level is the effective reset signal that reset circuit of the present invention is exported, and then high level is then invalid) with door U5, and lower computer system is in reset mode, thereby finishes electrification reset.After the electrification reset branch road reached stable state, three inputs were high level with the input of door U5, and lower computer system breaks away from reset mode.
In the present invention, the external reset mechanism of isolating mutually is as follows:
After electrification reset was finished, lower computer system can adopt the first external reset branch road and/or the second external reset branch road to carry out external reset when needs carry out external reset.With the first external reset branch road is example, when lower computer system need reset, and the first via external reset signal f of master system output
1Be low level, this moment the first isolating diode D1 forward conduction, level between the second pull-up resistor R2 and the second capacitance C2 will be dragged down, because the level between this moment second capacitance C2 and the 4th pull down resistor R4 also is a low level, so 4 ends of C inverter U3 are exported high level.Through constant T resetting time
1Back reset signal becomes high level by low level, the first isolating diode D1 by, cause the second capacitance C2 to charge again, repeat the first external reset branch road power up, thereby the square wave negative pulse that it is 8ms that a pulsewidth will appear in 4 ends of C inverter U3.Because the second external reset branch road is output as high level at this moment, the output of electrification reset branch road also is high level, with a U5 lower computer system is resetted through three inputs.
In the present invention, perseverance resets and prevents that mechanism is as follows:
After electrification reset was finished, electrification reset branch road, the first external reset branch road, second each branch road of external reset branch road all were in stable state, and promptly each branch road is output as high level.With the first external reset branch road is example, first via external reset signal f
1Permanent situation about resetting occurs, still can not cause slave computer generation perseverance to reset.First via external reset signal f
1When taking place to bear saltus step, the first isolating diode D1 forward conduction, level between the second pull-up resistor R2 and the second capacitance C2 will be dragged down, because the level between the second capacitance C2 and the 4th pull down resistor R4 also is a low level at this moment, so the output of C inverter U3 can not change, promptly still keep high level.As first via external reset signal f
1Permanent be low level after, owing to first isolating diode D1 forward conduction still, the level between the second pull-up resistor R2 and the second capacitance C2 still keeps low level, so the output of the first external reset branch road still any variation can not take place, promptly still keeps high level.Behind three inputs and door U5, three inputs are exported reset signal f with 18 ends of door U5
3Any change can not take place, promptly still be high level.The second external reset branch road operation principle and the first external reset branch road are identical, do not elaborate herein.
Claims (7)
1. a multichannel that prevents that perseverance from resetting is isolated reset circuit mutually, this reset circuit is connected between host computer and the slave computer, be used for slave computer is carried out system reset, it is characterized in that: this reset circuit is made up of with door electrification reset branch road, the first external reset branch road, the second external reset branch road and three inputs;
Described electrification reset props up route RC circuit, A inverter, B inverter formation, the original reset signal V of RC circuit output
1The inversion signal V first time that output has the high level characteristic after the A inverter carries out anti-phase the processing
2, inversion signal V for the first time
2The system power-on reset signal A that output has the low level characteristic after the B inverter is handled
0To three inputs and door;
The described first external reset branch road receives the first via external reset signal f of upper circuit output
1, first via external reset signal f
1Output A road sensitive signal V after A negative pulse sensitive circuit discharges and recharges capacitance
3, A road sensitive signal V
3The first external reset branch output signal A that output has the low level characteristic after the C inverter carries out anti-phase the processing
1To three inputs and door;
The described second external reset branch road receives the second tunnel external reset signal f of upper circuit output
2, the second tunnel external reset signal f
2Output B road sensitive signal V after B negative pulse sensitive circuit discharges and recharges capacitance
4, B road sensitive signal V
4The second external reset branch output signal A that output has the low level characteristic after the D inverter carries out anti-phase the processing
2To three inputs and door;
Described three inputs and the system power-on reset signal A of door to receiving
0, the first external reset branch output signal A
1, the second external reset branch output signal A
2Carry out with calculation process after the reset signal f of output low level available characteristic
3Give the next circuit;
Described electrification reset branch road, the first external reset branch road, the second external reset branch road and three inputs are connected to the circuit of door: the input of A inverter U1 and+be connected to first resistance R 1 between the 5V power supply, the input of A inverter U1 and simulate between the ground and be connected to first capacitor C 1; The ground connection termination of A inverter U1 simulation ground, A inverter U1 connects high power supply termination+5V power supply, and the output of A inverter U1 connects with the input of B inverter U2; The ground connection termination of B inverter U2 simulation ground, B inverter U2 connects high power supply termination+5V power supply, and the output of B inverter U2 connects with the first input end of a U5 with three inputs;
The negative pole end of the first isolating diode D1 meets the first via external reset signal f of host computer output
1, the positive terminal of the first isolating diode D1 and+be connected to the second pull-up resistor R2 between the 5V power supply, the positive terminal of the first isolating diode D1 connects with 1 end of the second capacitance C2; Be connected to the 4th pull down resistor R4 between 2 ends of the second capacitance C2 and the simulation ground, 2 ends of the second capacitance C2 connect with the input of C inverter U3; The 3rd protection diode D3 is connected on the input of simulation ground and C inverter U3; The ground connection termination of C inverter U3 simulation ground, C inverter U3 connects high power supply termination+5V power supply; The output of C inverter U3 connects with second input of three inputs with door U5;
The negative pole end of the second isolating diode D2 meets the second tunnel external reset signal f of host computer output
2, the positive terminal of the second isolating diode D2 and+be connected to the 3rd pull-up resistor R3 between the 5V power supply, the positive terminal of the second isolating diode D2 connects with 1 end of the 3rd capacitance C3; Be connected to the 5th pull down resistor R5 between 2 ends of the 3rd capacitance C3 and the simulation ground, 2 ends of the 3rd capacitance C3 connect with the input of D inverter U4; The 4th protection diode D4 is connected on the input of simulation ground and D inverter U4; The ground connection termination of D inverter U4 simulation ground, D inverter U4 connects high power supply termination+5V power supply; The output of D inverter U4 connects with 19 ends of three inputs with door U5;
Three inputs connect with the output of B inverter U2 with the first input end of door U5, three inputs are connected with the output of the family status two inputs with C inverter U3, three inputs connect with the output of D inverter U4 with the 3rd input of door U5, the output output reset signal of three inputs and door U5.
2. the multichannel that prevents that perseverance from resetting according to claim 1 is isolated reset circuit mutually, it is characterized in that: constant T resetting time of electrification reset branch road
0Constant T resetting time with the first external reset branch road
1, the second external reset branch road constant T resetting time
2Be different, i.e. T
0≠ T
1, T
0≠ T
2, and T
1=T
2
3. the multichannel that prevents that perseverance from resetting according to claim 2 is isolated reset circuit mutually, it is characterized in that: constant T resetting time of electrification reset branch road
0Constant T resetting time more than or equal to 10 times of first external reset branch road
1, i.e. T
0〉=10T
1Perhaps constant T resetting time of electrification reset branch road
0Constant T resetting time more than or equal to 10 times the second external reset branch roads
2, i.e. T
0〉=10T
2
4. the multichannel that prevents that perseverance from resetting according to claim 1 is isolated reset circuit mutually, it is characterized in that: A inverter, B inverter, C inverter and D inverter are chosen the trigger of SN74AHCT1G14 model; Three inputs choose the SN54ALS11A model with door with the door chip.
5. the multichannel that prevents that perseverance from resetting according to claim 1 is isolated reset circuit mutually, it is characterized in that: the RC circuit that first resistance R 1 is connected with first capacitor C 1 and constituted.
6. the multichannel that prevents that perseverance from resetting according to claim 5 is isolated reset circuit mutually, it is characterized in that: the first isolating diode D1, the second pull-up resistor R2, the second capacitance C2, the 4th pull down resistor R4, the 3rd protection diode D3 form A negative pulse sensitive circuit.
7. the multichannel that prevents that perseverance from resetting according to claim 5 is isolated reset circuit mutually, it is characterized in that: the second isolating diode D2, the 3rd pull-up resistor R3, the 3rd capacitance C3, the 5th pull down resistor R5, the 4th protection diode D4 form B negative pulse sensitive circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101172230A CN101359904B (en) | 2008-07-25 | 2008-07-25 | Multipath insulated resetting circuit preventing constant reset |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101172230A CN101359904B (en) | 2008-07-25 | 2008-07-25 | Multipath insulated resetting circuit preventing constant reset |
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| CN101359904A CN101359904A (en) | 2009-02-04 |
| CN101359904B true CN101359904B (en) | 2010-06-02 |
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| CN2008101172230A Expired - Fee Related CN101359904B (en) | 2008-07-25 | 2008-07-25 | Multipath insulated resetting circuit preventing constant reset |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104714618A (en) * | 2013-12-11 | 2015-06-17 | 鸿富锦精密电子(天津)有限公司 | Reset circuit |
| CN103944546A (en) * | 2014-03-28 | 2014-07-23 | 山东华芯半导体有限公司 | Device and method for preventing reset signal inside chip from losing efficacy |
| CN105406847A (en) * | 2015-11-27 | 2016-03-16 | 深圳市芯海科技有限公司 | Compact low-power-consumption multi-threshold reset circuit |
| CN109004927B (en) * | 2018-10-18 | 2024-01-12 | 深圳线易微电子有限公司 | Pulse signal transmission circuit and pulse signal refreshing circuit |
| CN113296433A (en) * | 2021-04-28 | 2021-08-24 | 成都秦川物联网科技股份有限公司 | Singlechip resetting method |
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| CN1781066A (en) * | 2003-04-25 | 2006-05-31 | 日本电气株式会社 | Reset circuit and digital communication apparatus |
| CN1924758A (en) * | 2005-09-02 | 2007-03-07 | 中兴通讯股份有限公司 | Multi-clock domain system reset circuit |
| CN1959595A (en) * | 2005-11-04 | 2007-05-09 | 鸿富锦精密工业（深圳）有限公司 | Reset circuit of computer system |
-
2008
- 2008-07-25 CN CN2008101172230A patent/CN101359904B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1781066A (en) * | 2003-04-25 | 2006-05-31 | 日本电气株式会社 | Reset circuit and digital communication apparatus |
| CN1924758A (en) * | 2005-09-02 | 2007-03-07 | 中兴通讯股份有限公司 | Multi-clock domain system reset circuit |
| CN1959595A (en) * | 2005-11-04 | 2007-05-09 | 鸿富锦精密工业（深圳）有限公司 | Reset circuit of computer system |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平6-196988A 1994.07.15 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101359904A (en) | 2009-02-04 |
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