CN113296433A - Singlechip resetting method - Google Patents
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- CN113296433A CN113296433A CN202110465296.4A CN202110465296A CN113296433A CN 113296433 A CN113296433 A CN 113296433A CN 202110465296 A CN202110465296 A CN 202110465296A CN 113296433 A CN113296433 A CN 113296433A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24032—Power on reset, powering up
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- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
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Abstract
The invention discloses a singlechip reset method, which belongs to the technical field of singlechip control and is characterized by comprising the following steps of: a. the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and the FPGA/CPLD clears the internal time count; b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals; c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second; d. after resetting is successful, the FPGA/CPLD pulls up the RST pin of the singlechip. The invention is suitable for severe and complicated electromagnetic environment, has stable and reliable operation, and can be widely used in occasions with high requirements on the reliability of industrial and medical equipment.
Description
Technical Field
The invention relates to the technical field of single chip microcomputer control, in particular to a single chip microcomputer resetting method.
Background
The reset is to restart the program in the singlechip to execute when the singlechip is just powered on or in a severe electromagnetic environment, which mainly prevents program confusion, i.e. runaway or dead halt, so that the system enters an initial state to receive various instructions to work at any time, and the reset reliability of the singlechip determines the stability of a product system.
Chinese patent publication No. CN 106489109a, published as 2017, 03, and 08 discloses a single chip microcomputer system and a reset method for the single chip microcomputer system, where the single chip microcomputer system includes: the single chip microcomputer system is connected with a main control system through one end of the reset pin, the other end of the reset pin is connected with the control unit, and the control unit is respectively connected with the CPU and the peripheral, wherein the main control system is used for controlling the reset pin to output a reset level; the control unit is used for detecting the signal duration of the reset level output by the reset pin and triggering wakeup or resetting the singlechip according to the signal duration of the reset level, and the signal duration for triggering wakeup is different from the signal duration for triggering reset.
The single chip microcomputer system and the reset method for the single chip microcomputer system disclosed in the patent document determine to wake up or reset the single chip microcomputer by detecting the reset pulse width of the reset pin, and realize two functions of waking up and resetting without increasing system resources, thereby reducing the number of input/output (I/O) ports and reducing the consumption of system resources. However, the single-chip microcomputer is not suitable for being used in a severe and complex electromagnetic environment, normal work of an external crystal oscillator of the single-chip microcomputer can be directly influenced under interference of the severe and complex electromagnetic environment, and the running reliability is poor.
Chinese patent publication No. CN 103576813a, published as 2014, 12.02 discloses a method for controlling low-voltage reset of a single chip, which is characterized by comprising:
A. the system is powered on, wherein the single chip microcomputer is powered by a storage battery;
B. starting a first timer, simultaneously starting a low-voltage reset detection circuit LVR, and sending a low-voltage reset signal to a reset unit in the single chip microcomputer when detecting that the power supply voltage of the single chip microcomputer meets the reset condition within the timing time of the first timer;
C. when the timing time of the first timer is up, closing the low-voltage reset detection circuit LVR and simultaneously starting the second timer, and turning to the step B when the timing time of the second timer is up;
the reset condition is that the power supply voltage of the singlechip is smaller than a preset voltage threshold, and the duration of the power supply voltage which is kept smaller than the preset voltage threshold is larger than or equal to a preset time threshold.
According to the single chip microcomputer low-voltage reset control method disclosed by the patent document, the LVR function is turned on and off at intervals in a single chip microcomputer program, and when the LVR function is turned on, if a low-voltage reset signal is detected to be sent to the single chip microcomputer, the operation is executed, so that the purposes of reducing current consumption, prolonging the battery life and prolonging the service life are achieved. However, the method is still not suitable for being used in a severe and complex electromagnetic environment, and the operation stability is influenced under the interference of the severe and complex electromagnetic environment.
Disclosure of Invention
The invention provides a singlechip reset method for overcoming the defects of the prior art, is suitable for severe and complicated electromagnetic environments, runs stably and reliably, and can be widely applied to occasions with high requirements on the reliability of industrial and medical equipment.
The invention is realized by the following technical scheme:
a single chip microcomputer reset method is characterized by comprising the following steps:
a. after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count;
b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals;
c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second;
d. after the single chip microcomputer is reset successfully, the FPGA/CPLD pulls up the RST pin of the single chip microcomputer.
In the step a, the request signal is a custom protocol, and a byte sum check is set at the tail end of the request signal.
In the step a, the preamble signal specifically refers to a 9 ms low time and a 4.5 ms high time of the preamble.
The request signal specifically refers to 280 microseconds low level time and 280 microseconds high level time of bit0 bits, 280 microseconds low level time and 840 microseconds high level time of bit1 bits.
In the step c, the time count inside the FPGA/CPLD exceeds the preset value, which means that no signal is received within 1 second.
The FPGA refers to a field programmable gate array.
The CPLD of the invention refers to a complex programmable logic device.
The RST is a reset circuit.
The invention has the beneficial effects that:
1. in the invention, after the first singlechip a is electrified, the singlechip firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count; b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals; c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second; d. after the singlechip is successfully reset, the RST pin of the singlechip is pulled up by the FPGA/CPLD, and compared with the prior art, the FPGA/CPLD is suitable for severe and complex electromagnetic environments, is stable and reliable in operation, and can be widely applied to occasions with high requirements on reliability of industrial and medical equipment.
2. According to the invention, due to the unique hardware physical structure of the FPGA/CPLD, the single chip microcomputer can never be down as long as the program is powered on without errors, and reliable guarantee can be provided for resetting the single chip microcomputer, so that the single chip microcomputer can stably run for a long time under the interference of severe and complex electromagnetic environments.
Detailed Description
Example 1
A single chip microcomputer reset method comprises the following steps:
a. after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count;
b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals;
c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second;
d. after the single chip microcomputer is reset successfully, the FPGA/CPLD pulls up the RST pin of the single chip microcomputer.
The embodiment is the most basic implementation mode, after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count; b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals; c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second; d. after the singlechip is successfully reset, the RST pin of the singlechip is pulled up by the FPGA/CPLD, and compared with the prior art, the FPGA/CPLD is suitable for severe and complex electromagnetic environments, is stable and reliable in operation, and can be widely applied to occasions with high requirements on reliability of industrial and medical equipment.
Example 2
A single chip microcomputer reset method comprises the following steps:
a. after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count;
b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals;
c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second;
d. after the single chip microcomputer is reset successfully, the FPGA/CPLD pulls up the RST pin of the single chip microcomputer.
In the step a, the request signal is a custom protocol, and a byte sum check is set at the tail end of the request signal.
This embodiment is a preferred embodiment.
Example 3
A single chip microcomputer reset method comprises the following steps:
a. after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count;
b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals;
c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second;
d. after the single chip microcomputer is reset successfully, the FPGA/CPLD pulls up the RST pin of the single chip microcomputer.
In the step a, the request signal is a custom protocol, and a byte sum check is set at the tail end of the request signal.
In the step a, the preamble signal specifically refers to a 9 ms low time and a 4.5 ms high time of the preamble.
This embodiment is yet another preferred embodiment.
Example 4
A single chip microcomputer reset method comprises the following steps:
a. after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count;
b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals;
c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second;
d. after the single chip microcomputer is reset successfully, the FPGA/CPLD pulls up the RST pin of the single chip microcomputer.
In the step a, the request signal is a custom protocol, and a byte sum check is set at the tail end of the request signal.
In the step a, the preamble signal specifically refers to a 9 ms low time and a 4.5 ms high time of the preamble.
The request signal specifically refers to 280 microseconds low level time and 280 microseconds high level time of bit0 bits, 280 microseconds low level time and 840 microseconds high level time of bit1 bits.
This embodiment is yet another preferred embodiment.
Example 5
A single chip microcomputer reset method comprises the following steps:
a. after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count;
b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals;
c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second;
d. after the single chip microcomputer is reset successfully, the FPGA/CPLD pulls up the RST pin of the single chip microcomputer.
In the step a, the request signal is a custom protocol, and a byte sum check is set at the tail end of the request signal.
In the step a, the preamble signal specifically refers to a 9 ms low time and a 4.5 ms high time of the preamble.
The request signal specifically refers to 280 microseconds low level time and 280 microseconds high level time of bit0 bits, 280 microseconds low level time and 840 microseconds high level time of bit1 bits.
In the step c, the time count inside the FPGA/CPLD exceeds the preset value, which means that no signal is received within 1 second.
The embodiment is the best implementation mode, after the first singlechip is powered on, the singlechip firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count; b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals; c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second; d. after the singlechip is successfully reset, the RST pin of the singlechip is pulled up by the FPGA/CPLD, and compared with the prior art, the FPGA/CPLD is suitable for severe and complex electromagnetic environments, is stable and reliable in operation, and can be widely applied to occasions with high requirements on reliability of industrial and medical equipment.
Due to the unique hardware physical structure of the FPGA/CPLD, the single chip microcomputer can be reset without downtime as long as the program is powered on without error, and therefore the single chip microcomputer can stably operate for a long time under the interference of severe complex electromagnetic environments.
Claims (5)
1. A single chip microcomputer reset method is characterized by comprising the following steps:
a. after the single chip microcomputer is powered on, the single chip microcomputer firstly sends a guide code signal to the FPGA/CPLD and then sends a request signal, and after the FPGA/CPLD receives the request signal, the FPGA/CPLD clears the internal time count;
b. the single chip microcomputer repeatedly sends request signals to the FPGA/CPLD at intervals;
c. when the FPGA/CPLD does not receive the request signal from the singlechip and the internal time count of the FPGA/CPLD exceeds a preset value, the FPGA/CPLD executes the reset operation on the singlechip and pulls down the RST pin of the singlechip for 1 second;
d. after the single chip microcomputer is reset successfully, the FPGA/CPLD pulls up the RST pin of the single chip microcomputer.
2. The single chip microcomputer resetting method according to claim 1, characterized in that: in the step a, the request signal is a custom protocol, and a byte sum check is set at the tail end of the request signal.
3. The single chip microcomputer resetting method according to claim 1, characterized in that: in the step a, the preamble signal specifically refers to a 9 ms low time and a 4.5 ms high time of the preamble.
4. The single chip microcomputer resetting method according to claim 1, characterized in that: the request signal specifically refers to 280 microseconds low level time and 280 microseconds high level time of bit0 bits, 280 microseconds low level time and 840 microseconds high level time of bit1 bits.
5. The single chip microcomputer resetting method according to claim 1, characterized in that: in the step c, the time count inside the FPGA/CPLD exceeds the preset value, which means that no signal is received within 1 second.
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| FENG-CHAI LIAO: "The microphone array speech enhancement system designe base on DS beamformer and AT89C52 singlechip", 《2012 INTERNATIONAL CONFERENCE ON WAVELET ACTIVE MEDIA TECHNOLOGY AND INFORMATION PROCESSING (ICWAMTIP)》 * |
| 李子华: "单片机复位状态及外设复位信号的处理", 《辽宁师专学报》 * |
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Application publication date: 20210824 |