CN206489410U - A kind of equipment remote measuring and controlling system based on optical communication module - Google Patents
A kind of equipment remote measuring and controlling system based on optical communication module Download PDFInfo
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- CN206489410U CN206489410U CN201720111296.3U CN201720111296U CN206489410U CN 206489410 U CN206489410 U CN 206489410U CN 201720111296 U CN201720111296 U CN 201720111296U CN 206489410 U CN206489410 U CN 206489410U
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- chip microcomputer
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- optical communication
- fpga
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Abstract
The utility model discloses a kind of equipment remote measuring and controlling system based on optical communication module, including FPGA processor, optical communication module and single-chip microcomputer；Single-chip microcomputer is internally provided with AD conversion module and program memory ROM, and the analog input end of AD conversion module is the collection of simulant signal input of remote measuring and controlling system；Single-chip microcomputer realizes data communication by SPI serial communication interfaces and FPGA processor；The management data input delivery outlet MDIO of optical communication module is connected with the IO of FPGA processor, and the management data sync clock input port MDC of optical communication module is connected with the IO of FPGA processor.The utility model has design difficulty low, it is not necessary to be equipped with specialized configuration device for primary processor FPGA, and system power dissipation is low, is conducive to improving advantage of the equipment long lasting for ability to work.
Description
Technical field
The utility model is related to a kind of equipment remote measuring and controlling system, is specifically that a kind of realized using optical communication module measures number
According to the TT＆C system of remote transmission, belong to observation and control technology field.
Background technology
The various operational factors of detection device are generally required in the industrial production, and are controlled according to parameters obtained, but
It is that live site environment residing for equipment often has that temperature is too high or too low, dust is excessive etc. and is not suitable for survey crew scene
The situation of measurement, therefore need a kind of to realize the circuit system of device parameter signal remote collection in industrial production.
In the prior art, due to FPGA processor have hardware logic aboundresources, calculate disposal ability it is strong, low in energy consumption and
The characteristics of job stability is high, thus be widely used in it is various need parameter acquisition, processing and transmission field, parameter signal is remote
Journey acquisition system coordinates AD conversion chip to realize signal acquisition there is also using FPGA processor as master chip, reuses light and leads to
News module sets up the technical scheme of data communication with central control system, in such technical scheme, is arranged on production scene
Feeding FPGA processor (is used in FPGA after the analog signal of field instrument output is converted to data signal through AD conversion chip
Hardware description language programming realization AD conversion controller)；FPGA processor realizes the configuration required for inherent logic circuit function
Data are then stored in configuration device chip, after system electrification from configuration device chip be loaded into FPGA in realize FPGA itself
Logic circuit function, therefore there is following defect in such scheme of the prior art：
(1) need to use hardware description language programming realization AD conversion controller in FPGA, inside FPGA
The design difficulty of circuit, also occupies FPGA internal logic resources.(2) AD conversion chip must be used to realize analog-to-digital conversion, this
Also so that system integrated circuit is not simple enough, and increase system power dissipation (equipment for being arranged on the production scene of bad environments is remote
Journey TT＆C system needs have longer continuous firing ability, and this requires to reduce system power dissipation as far as possible).(3) it must be equipped with solely
Vertical FPGA configuration device chips, which in turns increases system hardware complexity, power consumption in cost (configuration device price compared with
It is high).
Utility model content
For deficiencies of the prior art, the purpose of this utility model is：It is low how a kind of design difficulty is provided,
Specialized configuration device need not be equipped with for primary processor FPGA, and system power dissipation is low, be conducive to improving equipment long lasting for
The remote measuring and controlling system of ability to work, the utility model employs following technical scheme.
A kind of equipment remote measuring and controlling system based on optical communication module, it is characterised in that：Including FPGA processor, optical communication
Module and single-chip microcomputer；The single-chip microcomputer is internally provided with AD conversion module and program memory ROM, and the single-chip microcomputer is
STC12C5A60S2 type single-chip microcomputers；The optical communication module is IP113F cake cores；
The analog input end of the AD conversion module is the collection of simulant signal input of remote measuring and controlling system, the monolithic
The IO of machine is the digital signal acquiring input of remote measuring and controlling system；
The single-chip microcomputer realizes data communication by SPI serial communication interfaces and FPGA processor；
The management data input delivery outlet MDIO of the optical communication module is connected with the IO of FPGA processor, and the light leads to
The management data sync clock input port MDC of news module is connected with the IO of FPGA processor；
The configuration data of FPGA processor is stored in the program memory ROM of single-chip microcomputer；FPGA processor has data
Interface is configured, FPGA data configuration interface includes：Arrangement reset pin nCONFI, the first configuration status pin nSTATU, second are matched somebody with somebody
Configuration state pin CONF_DON, configuration data transmission pin DATA and configurable clock generator pin CLK；The arrangement reset pin nCONFI and monolithic
The IO of machine is connected, and the first configuration status pin nSTATU is connected with the IO of single-chip microcomputer, the second configuration status pin
CONF_DON is connected with the IO of single-chip microcomputer, and the configuration data transmission pin DATA is connected with the IO of single-chip microcomputer, the configuration
Clock pin CLK is connected with the IO of single-chip microcomputer.
Further, the FPGA is also connected with external memory storage.
Compared with prior art, the utility model has the following advantages that：
In the utility model, in (1) the system using chip microcontroller AD conversion function (at present in majority singlechip chip
All it is configured with AD conversion module), this can not only simplify circuit system structure, reduction system power dissipation, and also the signal of signal is adopted
Collection brings flexibility and (for example, because single-chip microcomputer I/O resource quantity is more, control flexible, programming is easy, grasps singlechip technology
Developer's also reason such as more, can be easy to realize increase signal acquisition way work(by setting up the modes such as analog switch
Can).
(2) configuration data of FPGA processor is deposited in the system using the program memory ROM inside single-chip microcomputer, this
Not only eliminate configuration device chip, simplify circuit design, it is clear that can also further reduce system power dissipation, this is right
Raising system has good effect long lasting for ability to work.
Brief description of the drawings
Fig. 1 is circuit structure diagram of the present utility model；
Embodiment
The utility model is described in further detail with reference to the accompanying drawings and detailed description.
First, the utility model circuit structure
As shown in figure 1, a kind of equipment remote measuring and controlling system based on optical communication module, is mainly led to by FPGA processor, light
Interrogate module and the big core devices of single-chip microcomputer three composition；
Wherein, FPGA processor is core processing device, and the main data for completing collected data calculate, store and control
Data are uploaded to central control system by optical communication module.Single-chip microcomputer is used for AD conversion and FPGA processor progress data is matched somebody with somebody
Put.The not responsible data processing of single-chip microcomputer in the utility model but the ROM that is internally integrated using itself and AD conversion module come
Respectively using FPGA configuration data storage and the analog-to-digital conversion dual-use function of collected signal, this is should with common single-chip microcomputer
With the maximum difference of system, (in common scm application system, single-chip microcomputer is typically the microprocessor core for being used as calculating data
The heart), and this particular design also the utility model preferably to meet equipment remotely to survey in of the present utility model use
Low-power consumption requirement required by control system (circuit structure is simple, few using number of devices).FPGA processor is public using Xilinx
Spartan series is taken charge of, this kind of chip cost is low, and capacity is medium, performance can meet general logical design requirement.Single-chip microcomputer is used
STC12C5A60S2 type single-chip microcomputers, STC12C5A60S2 series monolithics are the single-chip microcomputers of the single clock of macrocrystalline science and technology production, are
At a high speed, low-power consumption, superpower jamproof 8051 single-chip microcomputer of new generation, instruction code completely compatible traditional 8051, but the fast 8- of speed
12 times.It is internally integrated MAX810 Special reset circuits, 2 road PWM, 8 road 10-bit high speed AD conversion modules；Optical communication module is
IP113F cake cores, IP113F chips are that a of ICPlus companies production has gateway function, the optical fiber transceiving of super low-power consumption
Device.2 mouth switch kernels of transceiver design are aimed at built in IP113F, can be checked during transmission packet without MAC Address mark
And CRC check, single mode/there is provided TS-1000 marks for multimode fibre conversion can be supported using flow control under complete/semiduplex mode
Accurate maintenance frame.
Individually below to realize that each main process of data signal acquisition is served as theme elaboration circuit connecting relation：
1st, in order to realize capture setting production scene field instrument export analog signal use circuits below structure：
The analog input end of AD conversion module of the analog signal output of field instrument with being arranged on inside single-chip microcomputer is connected, certainly
This is to be attached by the simulation input mouthful pin of single-chip microcomputer.Because AD conversion module is arranged on inside single-chip microcomputer (this
STC12C5A60S2 series monolithic chip internals selected by utility model are integrated with 8 road 10-bit high speed A/D converters), therefore AD
The CPU of the acquisition control of conversion just inside single-chip microcomputer is carried out, and this is pure hard with the prior art being realized in FPGA processor
The AD conversion control module of part is different, and AD conversion control here is realized by software, although this stability is not as good as the AD of pure hardware
Modular converter, but design difficulty is small, and design efforts would is small and does not expend FPGA logical resource.Due to having inside single-chip microcomputer
8 road 10-bit high speed AD conversion modules, therefore the utility model actually the utility model can gather 8 tunnel analog signals simultaneously.
The IO of single-chip microcomputer is the digital signal acquiring input of remote measuring and controlling system, and this can easily realize field instrument numeral output
The collection of signal.
2nd, in order to which the data transfer that collects single-chip microcomputer is to FPGA processor, connected using circuits below：Single-chip microcomputer
Data communication is realized by SPI serial communication interfaces and FPGA processor.Specifically connecting is, four IO and the FPGA cores of single-chip microcomputer
Four general data IO of piece are corresponded to respectively to be connected, when producing SPI work by way of by software programming by single-chip microcomputer
Sequence realizes the SPI communication interface between single-chip microcomputer and fpga chip, so as to complete the transmission of data between the two.
3rd, to realize control of the FPGA processor to optical communication module, connected using following hardware：The pipe of optical communication module
Reason data input delivery outlet is connected with the IO of FPGA processor, the management data sync clock input port of the optical communication module
It is connected with the IO of FPGA processor.
4th, in order to realize that single-chip microcomputer is connected to the data configuration of FPGA processor using following hardware：FPGA processor has
Data configuration interface, FPGA data configuration interface includes：Arrangement reset pin nCONFI, the first configuration status pin nSTATU,
Two configuration status pin CONF_DON, configuration data transmission pin DATA and configurable clock generator pin CLK；Above-mentioned configuration pin is and single-chip microcomputer
IO be connected.
5th, in order to be stored gathered data to transmit with calling in the future, FPGA is also connected with external memory storage.
External memory storage uses common eprom memory.
2nd, utility model works principle
1st, the operation principle for the analog signal that field instrument of the capture setting in production scene is exported：It is arranged on production scene
The analog signal of field instrument output send into collection of simulant signal input of the present utility model (certain the utility model also set
Put in production scene), sent into after being converted to data signal through the AD conversion module inside single-chip microcomputer through SPI serial communication interfaces
Inside FPGA processor.The principle class that the operation principle that the data signal of field instrument output is collected is collected in analog signal
Seemingly.
2nd, the data transfer that single-chip microcomputer is collected to FPGA processor operation principle：When single-chip microcomputer produces SPI work
Sequence realizes the SPI communication interface between single-chip microcomputer and CPLD chips, and at least there is this communication mode the line of root 4 (to only need to unidirectional
3 lines can also be realized during communication), be respectively specifically：1st, slave unit Data In-Line SDI, is also main equipment DOL Data Output Line；
2nd, slave unit DOL Data Output Line SDO, is also main equipment Data In-Line；3rd, clock cable SCLK, clock signal is by main equipment
Produce；4th, slave unit enables signal wire CS.Serial data transmission is synchronized between main equipment and slave unit, in the shifting of main equipment
Digit pulse, data step-by-step transmission is high-order preceding, and status is full-duplex communication rear, it is simple efficiently.Monolithic in the utility model
Machine is main equipment, and FPGA processor is slave unit.
3rd, operation principle of the FPGA processor to the control of optical communication module：
Optical communication module I P113F sends some maintenance frames by optical port to be used to realize remote management, and user can pass through management
Data input delivery outlet MDIO and management data sync clock input port management MII register groups, monitor or reset and be local
Or the working condition of distal fiber transceiver.As long as user is performed to MII register read-write operations, specifically, MDC rises
Along saltus step, data will from high to low be transmitted bit by bit in MDIO.When SMI is in idle condition, MDIO is then in high-impedance state.
FPGA processor sends 32 continuous " 1 " and " beginning " signal initialization MDIO interfaces on MDIO, retransmits read/write operation
Code, then sends 5 IP1 13F address and 5 bit register addresses, finally sends the register data of 16.IP113F's
Data transfer is that this two lines is communicated with external unit by MDC and MDIO, therefore to carry out sequential from FPGA I0 mouths
Simulation and data transfer.FPGA processor realizes that optical communication module also will can just be gathered while control optical communication module
To field data report, central control system.
4th, the operation principle that single-chip microcomputer carries out data configuration to FPGA processor is：Usual FPGA processor realizes that itself is patrolled
(these configuration datas are by VHDL or principle map file lamp to configuration data required for volume circuit function
Fpga logic Functional Design file is converted, the application program of their similar single-chip microcomputers, is that FPGA realizes setting for specific function
Count) be then stored in configuration device chip, after system electrification from configuration device chip be loaded into FPGA in realize FPGA
Inherent logic circuit function, it is therefore desirable to special configuration device chip, the utility model is by the configuration data of FPGA processor
(ROM is generally used for depositing singlechip application programs) is stored in the program memory ROM of single-chip microcomputer, and concrete configuration principle is such as
Under：Deposited and realized on FPGA configuration data after electricity by single-chip microcomputer control to FPGA device using the program storage area of single-chip microcomputer
Data configuration, that is to say and use passive configuration mode, and configuration data sends FPGA, configuration process to using serial mode
It can be summarized as：(1) the first input/output port from single-chip microcomputer is (multiple to FPGA arrangement reset pin nCONFI transmission reset signals
Position signal is a low level and a high level closelyed follow) carry out arrangement reset.(2) whether detection arrangement reset succeeds, such as
The first configuration status pin nSTATU that fruit single-chip microcomputer detects FPGA by its second input/output port is converted by script low level
Then illustrate arrangement reset success for high level, otherwise arrangement reset does not fail, continue send configuration reset signal.(3) configure multiple
Single-chip microcomputer transmits pin DATA and configurable clock generator pin CLK by FPGA configuration data and carries out serial data transmission after the success of position, will
The configuration data being stored in single-chip microcomputer sends FPGA to, and FPGA configuration data transmission pin DATA is responsible for connecing in this course
Configuration data is received, configurable clock generator pin CLK, which is responsible for receiving, a rising edge, configuration does not occur on shift clock, configurable clock generator pin CLK
Data transfer pin DATA receives a configuration data until configuration data is transmitted.(4) whether detection configuration completes.Single-chip microcomputer
Detect whether the level on FPGA the second configuration status pin CONF_DON uprises, if not uprising, illustrate configuration failure, it should weight
It is new to start configuration process.
The larger AD conversion chip of power consumption is replaced by the AD conversion module inside single-chip microcomputer in the utility model, price
FPGA specialized configurations device chip costly is also replaced by single-chip microcomputer, and one side configuration data is stored in inside single-chip microcomputer
In ROM, the control of another aspect single-chip microcomputer flexibly can easily realize the data configuration to FPGA, to sum up, compared with prior art,
The utility model has the significant advantage that low in energy consumption, circuit structure is simple, cost is low.
Finally illustrate, above example is only unrestricted to illustrate the technical solution of the utility model, although ginseng
The utility model is described in detail according to preferred embodiment, it will be understood by those within the art that, can be to this
The technical scheme of utility model is modified or equivalent substitution, without departing from the objective and model of technical solutions of the utility model
Enclose, it all should cover among right of the present utility model.
Claims (2)
1. a kind of equipment remote measuring and controlling system based on optical communication module, it is characterised in that：Including FPGA processor, optical communication mould
Block and single-chip microcomputer；The single-chip microcomputer is internally provided with AD conversion module and program memory ROM, and the single-chip microcomputer is
STC12C5A60S2 type single-chip microcomputers；The optical communication module is IP113F cake cores；
The analog input end of the AD conversion module is the collection of simulant signal input of remote measuring and controlling system, the single-chip microcomputer
IO is the digital signal acquiring input of remote measuring and controlling system；
The single-chip microcomputer realizes data communication by SPI serial communication interfaces and FPGA processor；
The management data input delivery outlet MDIO of the optical communication module is connected with the IO of FPGA processor, the optical communication mould
The management data sync clock input port MDC of block is connected with the IO of FPGA processor；
The configuration data of FPGA processor is stored in the program memory ROM of single-chip microcomputer；FPGA processor has data configuration
Interface, FPGA data configuration interface includes：Arrangement reset pin nCONFI, the first configuration status pin nSTATU, the second configuration shape
State pin CONF_DON, configuration data transmission pin DATA and configurable clock generator pin CLK；The arrangement reset pin nCONFI's and single-chip microcomputer
IO is connected, and the first configuration status pin nSTATU is connected with the IO of single-chip microcomputer, the second configuration status pin CONF_
DON is connected with the IO of single-chip microcomputer, and the configuration data transmission pin DATA is connected with the IO of single-chip microcomputer, the configurable clock generator pin
CLK is connected with the IO of single-chip microcomputer.
2. a kind of equipment remote measuring and controlling system based on optical communication module according to claim 1, it is characterised in that described
FPGA is also connected with external memory storage.
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| CN201720111296.3U CN206489410U (en) | 2017-01-24 | 2017-01-24 | A kind of equipment remote measuring and controlling system based on optical communication module |
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| CN201720111296.3U CN206489410U (en) | 2017-01-24 | 2017-01-24 | A kind of equipment remote measuring and controlling system based on optical communication module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113296433A (en) * | 2021-04-28 | 2021-08-24 | 成都秦川物联网科技股份有限公司 | Singlechip resetting method |
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- 2017-01-24 CN CN201720111296.3U patent/CN206489410U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113296433A (en) * | 2021-04-28 | 2021-08-24 | 成都秦川物联网科技股份有限公司 | Singlechip resetting method |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170912 Termination date: 20180124 |
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| CF01 | Termination of patent right due to non-payment of annual fee |