CN207650628U - A kind of cascaded high-voltage frequency converter master control system of multiple processor structure - Google Patents
A kind of cascaded high-voltage frequency converter master control system of multiple processor structure Download PDFInfo
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- CN207650628U CN207650628U CN201721881520.3U CN201721881520U CN207650628U CN 207650628 U CN207650628 U CN 207650628U CN 201721881520 U CN201721881520 U CN 201721881520U CN 207650628 U CN207650628 U CN 207650628U
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Abstract
The utility model provides a kind of cascaded high-voltage frequency converter master control system of multiple processor structure, and high voltage frequency transformer main control system includes ARM circuit units, FPGA circuitry unit and DSP circuit unit；Communication between ARM circuit units and DSP circuit unit carries out data real-time, interactive by the dual port RAM inside FPGA circuitry unit；ARM circuit units have shared the function of communications portion in high-voltage frequency converter for handling PERCOM peripheral communication；FPGA circuitry unit is handled for realizing internal high real-time and error protection；DSP circuit unit is used for high-pressure frequency-conversion algorithm process.The cascaded high-voltage frequency converter master control system of the utility model ARM+FPGA+DSP frameworks has the characteristics that rich interface, real-time are high, scalability is good, strong antijamming capability, meets the various demands for control of cascaded high-voltage frequency converter.
Description
Technical field
The utility model is related to a kind of master control system, more particularly to a kind of cascaded high-voltage frequency converter of multiple processor structure
Master control system.
Background technology
Core of the control system of cascaded high-voltage frequency converter as high-voltage frequency converter, had both needed various external interfaces
The given, parameter setting for user's input, it is also desirable to which the analog quantitys such as voltage, electric current when real-time sampling is run, real-time control are high
Power cell is pressed, while being also needed to real time fail defencive function.
With the release of Novel control device, the control system of cascaded high-voltage frequency converter just towards control accuracy higher,
Response speed is faster, user interface is more convenient, maintainable preferably direction is developed.
Existing control system generally existing response speed influenced by communication interface, do not have remote maintenance upgrade function,
User interface less need for extend out PLC, master control scalability is not strong the problems such as.
Utility model content
It is rung existing for existing cascaded high-voltage frequency-changing control system the technical problem to be solved by the present invention is to be directed to
Answer speed and influenced by communication interface, without remote maintenance upgrade function, user interface less need for extend out PLC, master control can expand
Malleability is not equal by force and devises a kind of cascaded high-voltage frequency converter master control system of multiple processor structure；The master control system uses
ARM+FPGA+DSP frameworks, multiprocessor complement one another, and system provides abundant external interface in order to control, with the control system
High performance algorithm control and real-time system monitoring and protection can be carried out for platform.
In order to achieve the above objectives, the technical solution of the utility model is as follows：
A kind of cascaded high-voltage frequency converter master control system of multiple processor structure, the high voltage frequency transformer main control system packet
It includes：
One ARM circuit units, ARM circuit units have shared communications portion in high-voltage frequency converter for handling PERCOM peripheral communication
Function；
One FPGA circuitry unit, FPGA circuitry unit is handled for realizing internal high real-time and error protection；
One DSP circuit unit, DSP circuit unit are used for high-pressure frequency-conversion algorithm process；
Communication between ARM circuit units and DSP circuit unit carries out data by the dual port RAM inside FPGA circuitry unit
Real-time, interactive.
In one embodiment of the utility model, the ARM circuit units include Cortex M4 core ARM chips,
Cortex M4 core ARM chips are equipped with Ethernet data interface, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485
Interface；
The FPGA circuitry unit includes that fpga chip and the optical fiber driving chip and LVDS that are connect with fpga chip connect
Mouth chip, LVDS interface chip are equipped with 28 pairs of fiber optic communication expansion interfaces, and optical fiber driving chip is equipped with 4 road fiber optic data communication interfaces,
Fpga chip has encoder interfaces, control I/O interfaces, voltage to frequency conversion circuit, zero passage detection input circuit and fault detect
Input circuit；
The DSP circuit unit includes high performance float-point DSP and is connect with high performance float-point DSP serial
FLASH chip, FLASH chip, RTC circuit, the first high-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips；First
High-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips are also connect with fpga chip.
In one embodiment of the utility model, the ARM circuit units further include isolating chip, and isolating chip is used for
Signal isolation is carried out to Ethernet data interface, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485 interfaces.
Through the above technical solutions, the utility model has the beneficial effects that：
There is the utility model multiple processor structure, correspondence with foreign country function all to be handled by ARM circuit units, have abundant
External interface, support remote condition monitoring and remote system software upgrading, without extending out PLC；FPGA circuitry is rung with failure
Should be fast, system is easily scalable and extends the characteristics of, Fiber Optic Extension has used differential interface mode, improves system rejection to disturbance；It is high
The external high-precision AD of performance float-point DSP, is absorbed in algorithm process, between simultaneous processor by double parallel port RAM mode into
Row data interaction, improves system response time and control accuracy.
Description of the drawings
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, other drawings may also be obtained based on these drawings.
Fig. 1 is the block diagram of the utility model；
Fig. 2 is the utility model ARM circuit unit connection diagrams；
Fig. 3 is the utility model DSP circuit unit connection diagram；
Fig. 4 is the utility model FPGA circuitry unit connection diagram；
Number and the corresponding component title represented by letter in figure：
100, ARM circuit units 110, Cortex M4 core ARM chips 120, Ethernet data interface 130, PROFIBUS
DP interfaces 140, CAN BUS interfaces 150, Modbus485 interfaces 200, FPGA circuitry unit 210, fpga chip 211, encoder
Interface 212, control I/O interfaces 213, voltage to frequency conversion circuit 214, zero passage detection input circuit 215, fault detect input circuit
220, optical fiber driving chip 221, fiber optic data communication interface 230, LVDS interface chip 231, fiber optic communication expansion interface 300, DSP electricity
Road unit 310, high performance float-point DSP 320, serial FLASH chip 330, FLASH chip 340, RTC circuit 350, first
High-precision A/D sampling A/D chips 360, the second high-precision A/D sampling A/D chips.
Specific implementation mode
In order to make the technical means, creative features, achievement of purpose, and effectiveness of the utility model be easy to understand, under
Face combines and is specifically illustrating, and the utility model is expanded on further.
Shown in Figure 1, the utility model discloses a kind of cascaded high-voltage frequency converter master control systems of multiple processor structure
System, high voltage frequency transformer main control system includes ARM circuit units 100, FPGA circuitry unit 200 and DSP circuit unit 300；ARM
Communication between circuit unit 100 and DSP circuit unit 300 carries out data reality by the dual port RAM inside FPGA circuitry unit 200
When interact；ARM circuit units 100 have shared the function of communications portion in high-voltage frequency converter for handling PERCOM peripheral communication；FPGA electricity
Road unit 200 is for realizing the processing of internal high real-time and error protection；DSP circuit unit 300 is at high-pressure frequency-conversion algorithm
Reason.
The utility model ARM circuit units 100 include Cortex M4 core ARM chips 110, Cortex M4 core ARM chips
110 are equipped with Ethernet data interface 120, PROFIBUS DP interfaces 130, CAN BUS interfaces 140 and Modbus485 interfaces
150；FPGA circuitry unit 200 includes that fpga chip 210 and the optical fiber driving chip 220 and LVDS that are connect with fpga chip connect
Mouth chip 230, LVDS interface chip 230 are equipped with 28 pairs of fiber optic communication expansion interfaces 231, and optical fiber driving chip 220 is equipped with 4 road light
Fiber communication interface 221, fpga chip 210 have encoder interfaces 211, control I/O interfaces 212, voltage to frequency conversion circuit 213, mistake
Zero detection input circuit 214 and fault detect input circuit 215；DSP circuit unit 300 includes high performance float-point DSP
310 and the serial FLASH chip 320, FLASH chip 330, the RTC circuit 340, first that are connect with high performance float-point DSP
High-precision A/D sampling A/D chips 350, the second high-precision A/D sampling A/D chips 360；First high-precision A/D sampling A/D chips 350, second are high
Precision A/D sampling A/D chips 360 are also connect with fpga chip 210.
ARM circuit units 100 further include isolating chip (being not drawn into figure), and isolating chip is for connecing Ethernet data
Mouth, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485 interfaces carry out signal isolation.
As shown in Fig. 2, ARM circuit units, ARM chips are directly connected by parallel port with procotol chip stack, network
PHY outputs on chip are connected with network transformer, wherein NWE, NRD, NCS1, A [12..0], D [15..0], are ARM chips
FSMC interfaces, used NCS1 therein as network chip piece select, INT [3..0] be ARM chips GPIO mouths, pass through
GPIO interruptions can correspond to 4 SOCKET respectively, it can be achieved that Fast Ethernet connects.Profibus chips are also parallel interface,
The data/address bus form (D [15..0]) of 16 bit wides has been used, high-speed data interaction, Profibus chips can be carried out with ARM chips
Piece choosing has used the NCS2 of the FSMC interfaces of ARM chips；Use a GPIO mouth line as the interruption mouth line of Profibus simultaneously,
Summary responses communications command, Profibus outputs are isolated by Magnetic isolation chip, improve system rejection to disturbance；In addition ARM
Circuit unit realizes is isolated 485 interfaces and all the way isolated can interface all the way, passes through Magnetic isolation chip, output, signal mouth line point
RXD, TXD, RTS, CANTXD and CANRXD are not corresponded to；ARM circuit units take full advantage of the correspondence with foreign country ability of ARM chips,
A variety of PERCOM peripheral communication demands can be met.
As shown in Fig. 3, in DSP circuit unit, the FRAM with a piece of 512KB is connect with DSP by EMIF mouthfuls,
In due to EMIFA address wires it is inadequate, used 4 mouth lines simulation A [17..13]；Dsp chip stores program by serial FLASH
And Large Volume Data, the SPI0 interfaces of DSP are utilized, piece selects SPI_CS, serial clock SPI_CLK, serial data to go out SPI_DO
It is connect respectively with CS, CLK, MOSI, MISO of serial FLASH chip with serial data SPI_DI；RTC circuit and serial FLASH
It is similar, but the SPI1 interfaces of DSP have been used, while DSP circuit unit has reserce cell, it is ensured that real-time clock after power down
It remains to continue to run with, it is ensured that the failure logging time is accurate；In DSP circuit unit, DSP is also connected with two panels high-precision AD
It connects, connecting interface is parallel bus mode, wherein bus load is excessive in order to prevent and bus signals are isolated, is increased a piece of total
Line signal isolation chip, isolating chip piece select the common CS by two AD by being formed with door, when AD is not read in guarantee, isolated core
Piece output is high-impedance state, and the triggering of A/D chip and control signal are generated by FPGA, and signal is respectively to start conversion CONVST, just
RESET is resetted in conversion BUSY, AD, in addition DSP also has special FINT signals to be all the way connected with FPGA, is used to indicate AD conversion knot
Beam, this framework can make that the sampling time is more accurate, the DSP stand-by period is shorter；
As shown in Fig. 4 in conjunction with attached drawing 1, in FPGA circuitry unit, after encoder input A, B, Z are isolated by optocoupler, into
Enter ENCODE_A, ENCODE_B and ENCODE_Z mouth line to FPGA；Voltage to frequency conversion circuit is by voltage to frequency conversion chip, by voltage
Input is converted to frequency signal, and after being isolated by high speed optocoupler, into the VF_IN mouth lines of FPGA, it is defeated to provide additional simulation
Enter channel；It was generated for the zero cross detection circuit of synchronized sampling by being compared with zero potential to input ac voltage
Zero pulse enters the NZ_IN mouth lines of FPGA；The overvoltage that is obtained by other channels, overcurrent, the input of excess temperature failure, directly into
Enter OV_IN, OT_IN, IOC_IN mouth line to FPGA；15 tunnels control the I for entering FPGA after optocoupler is isolated with number I/O
[15..0] and O [15..0] mouth line；
It is directly connected to fiber optic data communication interface and has used 4 pairs of fiber optical transceivers, optical fiber is inputted by electrical level transferring chip, is defeated
Go out 5V TTL electric signals, is converted to FPGA mouth line acceptable 3.3V LVCMOS signals, has used the FIA of FPGA altogether
[3..0] and FOA [3..0] totally 8 mouth lines；In addition LVDS interface chip (DS90CF384MTD of TI) has been used to carry out optical fiber logical
Letter extension input and output, 28 pairs of input and output be connected to FPGA ERX [27..0] mouth lines and ETX [27..0] mouth line, LVDS it is defeated
Enter and all have enabled input with output interface chip, corresponding input and output can be closed when not in use by being connected to, and be connected respectively to
TEN the and REN mouth lines of FPGA；Using differential input and output mode, the anti-interference of Fiber Optic Extension is improved；
In FPGA circuitry unit, FPGA while the bridge as DSP circuit unit and ARM circuit units, respectively with DSP's
The parallel ports EMIF are connected with the parallel ports FSMC of ARM；The piece choosing of ARM FSMC is connected using NCS3 with FPGA ACS mouth lines；DSP's
The piece choosing of the parallel ports EMIF is applicable in NCS5 and is connected with FPGA DCS mouth lines；In addition to common read signal RD, write signal WR, data/address bus D
[15..0] outside, also uses two AWAIT, DWAIT mouth lines and is connected to corresponding NWAIT feet, for preventing burst access from rushing
It is prominent；In addition DSP has used three mouth line FA [15..13] for simulating address signal；And also increase between ARM, FPGA and DSP
AINT [3..0] and BINT [3..0] 4 match lines, for carrying out handshake communication between processor.
The utility model proposes a kind of cascaded high-voltage frequency converter master control system based on ARM+FPGA+DSP frameworks, tools
There is the characteristics of rich interface, real-time are high, scalability is good, strong antijamming capability, meets each of cascaded high-voltage frequency converter
Kind demand for control.
The advantages of basic principles and main features and the utility model of the utility model have been shown and described above.One's own profession
The technical staff of industry is it should be appreciated that the present utility model is not limited to the above embodiments, described in above embodiments and description
Only illustrate the principles of the present invention, on the premise of not departing from the spirit and scope of the utility model, the utility model is also
It will have various changes and improvements, these various changes and improvements fall within the scope of the claimed invention.The utility model
Claimed range is defined by the appending claims and its equivalent thereof.
Claims (3)
1. a kind of cascaded high-voltage frequency converter master control system of multiple processor structure, which is characterized in that the high-voltage frequency converter master
Control system includes：
One ARM circuit units, ARM circuit units have shared the work(of communications portion in high-voltage frequency converter for handling PERCOM peripheral communication
Energy；
One FPGA circuitry unit, FPGA circuitry unit is handled for realizing internal high real-time and error protection；
One DSP circuit unit, DSP circuit unit are used for high-pressure frequency-conversion algorithm process；
Communication between ARM circuit units and DSP circuit unit is real-time by the dual port RAM progress data inside FPGA circuitry unit
Interaction.
2. a kind of cascaded high-voltage frequency converter master control system of multiple processor structure according to claim 1, feature exist
In：
The ARM circuit units include Cortex M4 core ARM chips, and Cortex M4 core ARM chips connect equipped with Ethernet data
Mouth, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485 interfaces；
The FPGA circuitry unit includes fpga chip and the optical fiber driving chip being connect with fpga chip and LVDS interface core
Piece, LVDS interface chip are equipped with 28 pairs of fiber optic communication expansion interfaces, and optical fiber driving chip is equipped with 4 road fiber optic data communication interfaces, FPGA
Chip has encoder interfaces, control I/O interfaces, voltage to frequency conversion circuit, zero passage detection input circuit and fault detect input
Circuit；
The DSP circuit unit includes high performance float-point DSP and is connect with high performance float-point DSP serial
FLASH chip, FLASH chip, RTC circuit, the first high-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips；First
High-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips are also connect with fpga chip.
3. a kind of cascaded high-voltage frequency converter master control system of multiple processor structure according to claim 2, feature exist
In the ARM circuit units further include isolating chip, and isolating chip is for meeting Ethernet data interface, PROFIBUS DP
Mouth, CAN BUS interfaces and Modbus485 interfaces carry out signal isolation.
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| CN201721881520.3U CN207650628U (en) | 2017-12-28 | 2017-12-28 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721881520.3U CN207650628U (en) | 2017-12-28 | 2017-12-28 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
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| Publication Number | Publication Date |
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| CN207650628U true CN207650628U (en) | 2018-07-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108052066A (en) * | 2017-12-28 | 2018-05-18 | 上海澳通韦尔电力电子有限公司 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
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2017
- 2017-12-28 CN CN201721881520.3U patent/CN207650628U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108052066A (en) * | 2017-12-28 | 2018-05-18 | 上海澳通韦尔电力电子有限公司 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
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Granted publication date: 20180724 |