CN108052066A - A kind of cascaded high-voltage frequency converter master control system of multiple processor structure - Google Patents
A kind of cascaded high-voltage frequency converter master control system of multiple processor structure Download PDFInfo
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- CN108052066A CN108052066A CN201711463415.2A CN201711463415A CN108052066A CN 108052066 A CN108052066 A CN 108052066A CN 201711463415 A CN201711463415 A CN 201711463415A CN 108052066 A CN108052066 A CN 108052066A
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- 230000009977 dual effect Effects 0.000 claims abstract description 4
- 238000012545 processing Methods 0.000 claims abstract description 4
- 238000005070 sampling Methods 0.000 claims description 17
- 239000000835 fiber Substances 0.000 claims description 11
- 239000013307 optical fiber Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 6
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1103—Special, intelligent I-O processor, also plc can only access via processor
Abstract
The present invention provides a kind of cascaded high-voltage frequency converter master control system of multiple processor structure, high voltage frequency transformer main control system includes ARM circuit units, FPGA circuitry unit and DSP circuit unit；Communication between ARM circuit units and DSP circuit unit carries out data real-time, interactive by the dual port RAM inside FPGA circuitry unit；ARM circuit units have shared the function of communications portion in high voltage converter for handling PERCOM peripheral communication；FPGA circuitry unit is used to implement internal high real-time processing and error protection；DSP circuit unit is used for high-pressure frequency-conversion algorithm process.The cascaded high-voltage frequency converter master control system of ARM+FPGA+DSP frameworks of the present invention has the characteristics that rich interface, real-time are high, scalability is good, strong antijamming capability, meets the various demands for control of cascaded high-voltage frequency converter.
Description
Technical field
The present invention relates to a kind of master control system, the cascaded high-voltage frequency converter master control of more particularly to a kind of multiple processor structure
System.
Background technology
Core of the control system of cascaded high-voltage frequency converter as high voltage converter, had both needed various external interfaces
It is given for user's input, parameter setting, it is also desirable to which the analog quantitys such as voltage, electric current when real-time sampling is run, control is high in real time
Power cell is pressed, while is also needed to real time fail defencive function.
With the release of Novel control device, the control system of cascaded high-voltage frequency converter just towards control accuracy higher,
Response speed is faster, user interface is more convenient, maintainable preferably direction is developed.
Existing control system generally existing response speed influenced by communication interface, without remote maintenance upgrade function,
User interface less need for extend out PLC, master control scalability is not strong the problems such as.
The content of the invention
The technical problem to be solved in the present invention is for the existing response speed of existing cascaded high-voltage frequency-changing control system
Degree influenced by communication interface, without remote maintenance upgrade function, user interface less need for extending out PLC, master control scalability
It does not wait by force and devises a kind of cascaded high-voltage frequency converter master control system of multiple processor structure；The master control system has used ARM+
FPGA+DSP frameworks, multiprocessor complement one another, and system provides abundant external interface in order to control, are flat using the control system
Platform can carry out high performance algorithm control and real-time system monitoring and protect.
In order to achieve the above objectives, technical scheme is as follows：
A kind of cascaded high-voltage frequency converter master control system of multiple processor structure, the high voltage frequency transformer main control system bag
It includes：
One ARM circuit units, ARM circuit units have shared communications portion in high voltage converter for handling PERCOM peripheral communication
Function；
One FPGA circuitry unit, FPGA circuitry unit are used to implement internal high real-time processing and error protection；
One DSP circuit unit, DSP circuit unit are used for high-pressure frequency-conversion algorithm process；
Communication between ARM circuit units and DSP circuit unit carries out data by the dual port RAM inside FPGA circuitry unit
Real-time, interactive.
In one embodiment of the invention, the ARM circuit units include Cortex M4 core ARM chips, Cortex
M4 core ARM chips are equipped with Ethernet data interface, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485 interfaces；
The optical fiber driving chip and LVDS that the FPGA circuitry unit includes fpga chip and is connected with fpga chip connect
Mouth chip, LVDS interface chip are equipped with 28 pairs of fiber optic communication expansion interfaces, and optical fiber driving chip is equipped with 4 road fiber optic data communication interfaces,
Fpga chip has encoder interfaces, control I/O interfaces, voltage to frequency conversion circuit, zero passage detection input circuit and fault detect
Input circuit；
The DSP circuit unit includes high performance float-point DSP and is connected with high performance float-point DSP serial
FLASH chip, FLASH chip, RTC circuit, the first high-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips；First
High-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips are also connected with fpga chip.
In one embodiment of the invention, the ARM circuit units further include isolating chip, isolating chip be used for
Too network data interface, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485 interfaces carry out signal isolation.
Through the above technical solutions, the beneficial effects of the invention are as follows：
The present invention has multiple processor structure, and correspondence with foreign country function is all handled by ARM circuit units, outside abundant
Portion's interface supports remote condition monitoring and remote system software upgrading, without extending out PLC；FPGA circuitry have failure response it is fast,
The characteristics of system is easily scalable and extends, Fiber Optic Extension has used differential interface mode, improves system rejection to disturbance；High-performance is floated
The point external high-precision AD of dsp chip, is absorbed in algorithm process, and mode carries out data by double parallel port RAM between simultaneous processor
Interaction, improves system response time and control accuracy.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention, for those of ordinary skill in the art, without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is structure diagram of the present invention；
Fig. 2 is ARM circuit units connection diagram of the present invention；
Fig. 3 is DSP circuit unit connection diagram of the present invention；
Fig. 4 is FPGA circuitry unit connection diagram of the present invention；
Corresponding component title of the number represented by with letter in figure：
100th, ARM circuit units 110, Cortex M4 core ARM chips 120, Ethernet data interface 130, PROFIBUS
DP interfaces 140, CAN BUS interfaces 150, Modbus485 interfaces 200, FPGA circuitry unit 210, fpga chip 211, encoder
Interface 212, control I/O interfaces 213, voltage to frequency conversion circuit 214, zero passage detection input circuit 215, fault detect input circuit
220th, optical fiber driving chip 221, fiber optic data communication interface 230, LVDS interface chip 231, fiber optic communication expansion interface 300, DSP electricity
Road unit 310, high performance float-point DSP 320, serial FLASH chip 330, FLASH chip 340, RTC circuit 350, first
High-precision A/D sampling A/D chips 360, the second high-precision A/D sampling A/D chips.
Specific embodiment
In order to be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, tie below
Conjunction is specifically illustrating, and the present invention is further explained.
It is shown in Figure 1, it is high the invention discloses a kind of cascaded high-voltage frequency converter master control system of multiple processor structure
Voltage frequency changer master control system includes ARM circuit units 100, FPGA circuitry unit 200 and DSP circuit unit 300；ARM circuits
Communication between unit 100 and DSP circuit unit 300 carries out data by the dual port RAM inside FPGA circuitry unit 200 and hands in real time
Mutually；ARM circuit units 100 have shared the function of communications portion in high voltage converter for handling PERCOM peripheral communication；FPGA circuitry list
Member 200 is used to implement internal high real-time processing and error protection；DSP circuit unit 300 is used for high-pressure frequency-conversion algorithm process.
ARM circuit units 100 of the present invention include Cortex M4 core ARM chips 110, and Cortex M4 core ARM chips 110 are set
There are Ethernet data interface 120, PROFIBUS DP interfaces 130, CAN BUS interfaces 140 and Modbus485 interfaces 150；
FPGA circuitry unit 200 includes fpga chip 210 and the optical fiber driving chip 220 and LVDS interface core that are connected with fpga chip
Piece 230, LVDS interface chip 230 are equipped with 28 pairs of fiber optic communication expansion interfaces 231, and optical fiber driving chip 220 leads to equipped with 4 road optical fiber
Believe interface 221, fpga chip 210 has encoder interfaces 211, control I/O interfaces 212, voltage to frequency conversion circuit 213, zero passage inspection
Survey input circuit 214 and fault detect input circuit 215；DSP circuit unit 300 include high performance float-point DSP 310 with
And serial FLASH chip 320, FLASH chip 330, the RTC circuit 340, first being connected with high performance float-point DSP are high-precision
Spend A/D sampling A/D chips 350, the second high-precision A/D sampling A/D chips 360；The 350, second high-precision of first high-precision A/D sampling A/D chips
A/D sampling A/D chips 360 are also connected with fpga chip 210.
ARM circuit units 100 further include isolating chip (being not drawn into figure), and isolating chip is used to connect Ethernet data
Mouth, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485 interfaces carry out signal isolation.
As shown in Figure 2, ARM circuit units, ARM chips are directly connected with procotol chip stack by parallel port, network
PHY outputs on chip are connected with network transformer, wherein NWE, NRD, NCS1, A [12..0], D [15..0], are ARM chips
FSMC interfaces, used NCS1 therein as network chip piece select, INT [3..0] be ARM chips GPIO mouths, pass through
GPIO interruptions can correspond to 4 SOCKET respectively, it can be achieved that Fast Ethernet connects.Profibus chips are also parallel interface,
The data/address bus form (D [15..0]) of 16 bit wides has been used, high-speed data interaction, Profibus chips can be carried out with ARM chips
Piece choosing has used the NCS2 of the FSMC interfaces of ARM chips；Interruption mouth line of the GPIO mouth line as Profibus is used simultaneously,
Summary responses communications command, Profibus outputs are isolated by Magnetic isolation chip, improve system rejection to disturbance；In addition ARM
Circuit unit realizes isolates 485 interfaces and all the way isolated can interface all the way, passes through Magnetic isolation chip, output, signal mouth line point
RXD, TXD, RTS, CANTXD and CANRXD are not corresponded to；ARM circuit units take full advantage of the correspondence with foreign country ability of ARM chips,
A variety of PERCOM peripheral communication demands can be met.
As shown in Figure 3, in DSP circuit unit, there is the FRAM of a piece of 512KB, be connected with DSP by EMIF mouthfuls,
In due to EMIFA address wires it is inadequate, used 4 mouth lines simulation A [17..13]；Dsp chip stores program by serial FLASH
And Large Volume Data, the SPI0 interfaces of DSP are make use of, piece selects SPI_CS, serial clock SPI_CLK, serial data to go out SPI_DO
It is connected with CS, CLK, MOSI, the MISO of serial data SPI_DI respectively with serial FLASH chip；RTC circuit and serial FLASH
It is similar, but the SPI1 interfaces of DSP have been used, while DSP circuit unit has reserce cell, it is ensured that real-time clock after power down
It remains to continue to run with, it is ensured that the failure logging time is accurate；In DSP circuit unit, DSP is also connected with two panels high-precision AD
It connects, connecting interface is parallel bus mode, wherein bus load is excessive in order to prevent and bus signals are isolated, is added a piece of total
Line signal isolation chip, isolating chip piece selects the common CS by two AD by being formed with door, when AD is not read in guarantee, isolated core
For high-impedance state, the triggering of A/D chip and control signal are generated by FPGA for piece output, and signal is respectively to start conversion CONVST, just
RESET is resetted in conversion BUSY, AD, in addition DSP also has special FINT signals to be all the way connected with FPGA, is used to indicate AD conversion knot
Beam, this framework can make that the sampling time is more accurate, the DSP stand-by period is shorter；
As shown in Figure 4 with reference to attached drawing 1, in FPGA circuitry unit, after encoder input A, B, Z are isolated by optocoupler, into
Enter ENCODE_A, ENCODE_B and ENCODE_Z mouth line to FPGA；Voltage to frequency conversion circuit is by voltage to frequency conversion chip, by voltage
Input is converted to frequency signal, and after isolating by high speed optocoupler, into the VF_IN mouth lines of FPGA, it is defeated to provide additional simulation
Enter passage；For the zero cross detection circuit of synchronized sampling, by compared with zero potential, being generated to input ac voltage
Zero pulse enters the NZ_IN mouth lines of FPGA；The overvoltage that is obtained by other channels, overcurrent, the input of excess temperature failure, directly into
Enter OV_IN, OT_IN, IOC_IN mouth line to FPGA；15 tunnels control the I for entering FPGA after optocoupler is isolated with number I/O
[15..0] and O [15..0] mouth line；
It is directly connected to fiber optic data communication interface and has used 4 pairs of fiber optical transceivers, optical fiber is inputted by electrical level transferring chip, is defeated
Go out 5V TTL electric signals, be converted to FPGA mouth line acceptable 3.3V LVCMOS signals, used the FIA of FPGA altogether
[3..0] and FOA [3..0] totally 8 mouth lines；In addition LVDS interface chip (DS90CF384MTD of TI) has been used to carry out optical fiber to lead to
Letter extension input and output, 28 pairs of input and output be connected to FPGA ERX [27..0] mouth lines and ETX [27..0] mouth line, LVDS it is defeated
Enter and be respectively provided with enabled input with output interface chip, corresponding input and output can be closed when not in use by being connected to, and be connected respectively to
TEN the and REN mouth lines of FPGA；Using differential input and output mode, the anti-interference of Fiber Optic Extension is improved；
In FPGA circuitry unit, FPGA is simultaneously as DSP circuit unit and the bridge of ARM circuit units, respectively with DSP's
EMIF parallel ports are connected with the FSMC parallel ports of ARM；The piece choosing of ARM FSMC is connected using NCS3 with FPGA ACS mouth lines；DSP's
The piece choosing of EMIF parallel ports is applicable in NCS5 and is connected with FPGA DCS mouth lines；Except common read signal RD, write signal WR, data/address bus D
[15..0] outside, also uses two AWAIT, DWAIT mouth lines and is connected to corresponding NWAIT feet, for preventing burst access from rushing
It is prominent；In addition DSP has used three mouth line FA [15..13] for simulating address signal；And also increase between ARM, FPGA and DSP
AINT [3..0] and BINT [3..0] 4 match lines, for carrying out handshake communication between processor.
The present invention proposes a kind of cascaded high-voltage frequency converter master control system based on ARM+FPGA+DSP frameworks, has and connects
The characteristics of mouth is abundant, real-time is high, scalability is good, strong antijamming capability, meets the various controls of cascaded high-voltage frequency converter
Demand processed.
The basic principles, main features and the advantages of the invention have been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the above embodiments and description only describe this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes
Change and improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention by appended claims and its
Equivalent thereof.
Claims (3)
- A kind of 1. cascaded high-voltage frequency converter master control system of multiple processor structure, which is characterized in that the high voltage converter master Control system includes：One ARM circuit units, ARM circuit units have shared the work(of communications portion in high voltage converter for handling PERCOM peripheral communication Energy；One FPGA circuitry unit, FPGA circuitry unit are used to implement internal high real-time processing and error protection；One DSP circuit unit, DSP circuit unit are used for high-pressure frequency-conversion algorithm process；Communication between ARM circuit units and DSP circuit unit is real-time by the dual port RAM progress data inside FPGA circuitry unit Interaction.
- 2. a kind of cascaded high-voltage frequency converter master control system of multiple processor structure according to claim 1, feature exist In：The ARM circuit units include Cortex M4 core ARM chips, and Cortex M4 core ARM chips connect equipped with Ethernet data Mouth, PROFIBUS DP interfaces, CAN BUS interfaces and Modbus485 interfaces；The FPGA circuitry unit includes fpga chip and the optical fiber driving chip and LVDS interface core that are connected with fpga chip Piece, LVDS interface chip are equipped with 28 pairs of fiber optic communication expansion interfaces, and optical fiber driving chip is equipped with 4 road fiber optic data communication interfaces, FPGA Chip has encoder interfaces, control I/O interfaces, voltage to frequency conversion circuit, zero passage detection input circuit and fault detect input Circuit；The DSP circuit unit includes high performance float-point DSP and is connected with high performance float-point DSP serial FLASH chip, FLASH chip, RTC circuit, the first high-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips；First High-precision A/D sampling A/D chips, the second high-precision A/D sampling A/D chips are also connected with fpga chip.
- 3. a kind of cascaded high-voltage frequency converter master control system of multiple processor structure according to claim 2, feature exist In the ARM circuit units further include isolating chip, and isolating chip is used to meet Ethernet data interface, PROFIBUS DP Mouth, CAN BUS interfaces and Modbus485 interfaces carry out signal isolation.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711463415.2A CN108052066A (en) | 2017-12-28 | 2017-12-28 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
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| CN201711463415.2A CN108052066A (en) | 2017-12-28 | 2017-12-28 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109212303A (en) * | 2018-10-22 | 2019-01-15 | 大禹电气科技股份有限公司 | Digital signal samples processing circuit for high-voltage frequency converter |
| CN112147918A (en) * | 2019-06-26 | 2020-12-29 | 中车株洲电力机车研究所有限公司 | Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture |
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| CN204667101U (en) * | 2015-05-28 | 2015-09-23 | 南车株洲电力机车研究所有限公司 | A kind of frequency converter controller |
| CN105373041A (en) * | 2015-11-19 | 2016-03-02 | 中冶南方（武汉）自动化有限公司 | High-performance frequency conversion controller |
| CN207650628U (en) * | 2017-12-28 | 2018-07-24 | 上海澳通韦尔电力电子有限公司 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
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Patent Citations (4)
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| CN203520080U (en) * | 2013-09-28 | 2014-04-02 | 南车株洲电力机车研究所有限公司 | Real-time controller of universal frequency converter |
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| CN105373041A (en) * | 2015-11-19 | 2016-03-02 | 中冶南方（武汉）自动化有限公司 | High-performance frequency conversion controller |
| CN207650628U (en) * | 2017-12-28 | 2018-07-24 | 上海澳通韦尔电力电子有限公司 | A kind of cascaded high-voltage frequency converter master control system of multiple processor structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109212303A (en) * | 2018-10-22 | 2019-01-15 | 大禹电气科技股份有限公司 | Digital signal samples processing circuit for high-voltage frequency converter |
| CN112147918A (en) * | 2019-06-26 | 2020-12-29 | 中车株洲电力机车研究所有限公司 | Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture |
| CN112147918B (en) * | 2019-06-26 | 2022-02-11 | 中车株洲电力机车研究所有限公司 | Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture |
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