CN204650202U

CN204650202U - A kind of CPLD of utilization realizes the single-chip computer control system of ports-Extending

Info

Publication number: CN204650202U
Application number: CN201520305660.0U
Authority: CN
Inventors: 郑�和; 刘修军; 况君; 林稳章
Original assignee: Chongqing Telecommunication Polytechnic College
Current assignee: Chongqing Telecommunication Polytechnic College
Priority date: 2015-05-06
Filing date: 2015-05-06
Publication date: 2015-09-16
Anticipated expiration: 2025-05-06

Abstract

The utility model discloses the single-chip computer control system that a kind of CPLD of utilization realizes ports-Extending, comprise single-chip microcomputer and CPLD chip, single-chip microcomputer realizes being electrically connected by SPI serial communication interface and CPLD chip: the first input/output port of single-chip microcomputer is connected with the first input/output port of CPLD chip, and connecting line is designated as from device data input line SDI; Second input/output port of single-chip microcomputer is connected with the second input/output port of CPLD chip, and connecting line is designated as from device data output line SDO; 3rd input/output port of single-chip microcomputer is connected with the 3rd input/output port of CPLD chip, and connecting line is designated as clock cable SCLK; 4th input/output port of single-chip microcomputer is connected with the 4th input/output port of CPLD chip, and connecting line is designated as from devices enable signal wire CS.It is fast that the utility model has operating rate, and job stability is high, and can realize the advantage of system port expansion.

Description

A kind of CPLD of utilization realizes the single-chip computer control system of ports-Extending

Technical field

The utility model relates to a kind of single chip control module, and specifically a kind of CPLD of utilization chip realizes the single chip control module of control system ports-Extending, belongs to electronic technology field.

Background technology

Single-chip computer control system in the application of intelligent control circuit design field widely, can say it is the leading role of Electronic Design at China's single-chip microcomputer, single-chip computer control system has simplicity of design, control flexibly, design and develop the plurality of advantages such as language (C language) is universal, but single-chip computer control system also exists obvious shortcoming: (1) operating rate is low, μ s level usually can only be operated in; (2) functional reliability is low in addition, and the reset of moment also can cause serious consequence in some cases, and therefore single-chip computer control system needs to use a large amount of digital circuits to coordinate with it some function; (3) in the application that design is more complicated, special distinct issues are: single-chip microcomputer input/output port amount is limited, therefore a large amount of digit chips must be used as ports-Extending device in order to carry out system extension, such as in the design of LED display driving circuit, this situation shows particularly outstanding.

Utility model content

For prior art above shortcomings, the purpose of this utility model is: how to provide a kind of operating rate, and the purer single-chip computer control system of job stability is excellent, and can realize the single chip control module of ports-Extending.

To achieve these goals, the utility model have employed following technical scheme.

A kind of CPLD of utilization realizes the single-chip computer control system of ports-Extending, it is characterized in that: comprise single-chip microcomputer and CPLD chip, described single-chip microcomputer realizes being electrically connected by SPI serial communication interface and CPLD chip: the first input/output port of single-chip microcomputer is connected with the first input/output port of CPLD chip, and connecting line is designated as from device data input line SDI; Second input/output port of single-chip microcomputer is connected with the second input/output port of CPLD chip, and connecting line is designated as from device data output line SDO; 3rd input/output port of single-chip microcomputer is connected with the 3rd input/output port of CPLD chip, and connecting line is designated as clock cable SCLK; 4th input/output port of single-chip microcomputer is connected with the 4th input/output port of CPLD chip, and connecting line is designated as from devices enable signal wire CS.

Further, described single-chip microcomputer is connected with computing machine by serial ports.

Compared to existing technology, the utility model tool has the following advantages:

In the utility model, SPI serial communication interface is adopted to be electrically connected between single-chip microcomputer and CPLD chip, this had both achieved the communication between single-chip microcomputer and CPLD, achieve again higher design flexibility: on the one hand, CPLD chip has a large amount of input/output port resources, usually have at least 36 input/output ports, owing to being SPI serial communication connection between single-chip microcomputer and CPLD, therefore single-chip microcomputer realizes utilizing the expansion of the input/output port of CPLD by SPI serial data transmission; On the other hand, CPLD belongs to the very high digit chip of a kind of integrated level, it can realize complicated Design of Digital Circuit, therefore the function originally needing independent middle scale digital integrated circuit to realize in single-chip computer control system design just can use CPLD to realize, and this makes the operating rate of whole single-chip computer control system and functional reliability be obtained for lifting.Therefore compare the pure control module being unique control core with single-chip microcomputer to compare, it is fast that the utility model has operating rate, and job stability is high, and can realize the advantage of system port expansion.

Accompanying drawing explanation

Fig. 1 is circuit structure diagram of the present utility model;

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

The core of common single-chip computer control system is the minimum system with singlechip chip, that is to say and comprise single-chip microcomputer, clock circuit and reset circuit three part, single-chip microcomputer has 16 input/output port pins usually, in hardware design, usual minimum system can match with a large amount of digit chip and realize various function, as background technology analyzed this hardware architecture often to there is speed low, poor stability, and use a large amount of digit chip for expanding one-chip machine port or realizing other functions, therefore the area of pcb board all can increase with wiring difficulty, and designed reliability and design efficiency all can be restricted.

As shown in Figure 1, the single-chip computer control system that a kind of CPLD of utilization of the utility model realizes ports-Extending then adopts following hardware architecture:

Control system comprises single-chip microcomputer and CPLD chip.Single-chip microcomputer realizes being electrically connected with CPLD chip by SPI serial communication interface, the basis realizing above-mentioned communication connection is: single-chip microcomputer can simulate SPI Control timing sequence as a kind of intelligent control chip, modern and realize single-chip microcomputer spi bus and send data to CPLD chip and order carrys out control CPLD internal digital logic unit.

Physical circuit annexation is: the first input/output port of single-chip microcomputer is connected with the first input/output port of CPLD chip, and connecting line is designated as from device data input line SDI; Second input/output port of single-chip microcomputer is connected with the second input/output port of CPLD chip, and connecting line is designated as from device data output line SDO; 3rd input/output port of single-chip microcomputer is connected with the 3rd input/output port of CPLD chip, and connecting line is designated as clock cable SCLK; 4th input/output port of single-chip microcomputer is connected with the 4th input/output port of CPLD chip, and connecting line is designated as from devices enable signal wire CS.

Four input/output ports of single-chip microcomputer and four input/output ports of CPLD chip are corresponding is respectively connected in a word, produce by single-chip microcomputer the SPI communication interface that SPI work schedule realizes between single-chip microcomputer and CPLD chip, thus complete the transmission of data between the two.

Concrete single-chip microcomputer can select MCS51 series, and CPLD chip can adopt EPM7032S type CPLD chip to realize.

Principle of work of the present utility model is: single-chip microcomputer generation SPI work schedule realizes the SPI communication interface between single-chip microcomputer and CPLD chip, this communication mode at least has root 4 line when one-way communication (only need 3 lines also can realize), concrete respectively: 1, from device data input line SDI, be also main equipment DOL Data Output Line; 2, from device data output line SDO, be also main equipment Data In-Line; 3, clock cable SCLK, clock signal is produced by main equipment; 4, from devices enable signal wire CS.

Main equipment and carry out synchronous serial-data transmission between equipment, under the shift pulse of main equipment, data step-by-step is transmitted, and high-order front, status, rear, is full-duplex communication, simply efficiently.

In the utility model, single-chip microcomputer is main equipment, and CPLD is from equipment, and CPLD can be first temporary after receiving the data of single-chip microcomputer, then for control or the data input of CPLD internal digital logic unit.On the one hand, EPM7032S chip has 36 I/O mouths, and removing is used for 4 ports with single chip communication, also has 32 ports to use, and this can meet the demand of major part for ports-Extending design completely; CPLD is extensive programmable digital integrated circuit on the other hand, inside has a large amount of digital logic unit, call design by hardware description language or schematic diagram and all can realize complicated stable Digital Logic, thus for whole system provide at a high speed, stable hardware foundation.

In addition, following scheme can be adopted to solve about work clock: to utilize outer clock circuit to provide work clock for CPLD chip, CPLD chip internal operating clock signals is supplied to single-chip microcomputer and uses as work clock after the inner frequency division module frequency division of CPLD, so just can simplify circuit design further.

Single-chip microcomputer also realizes the communication with computing machine by its serial ports, some results of such CPLD are by inputting single-chip microcomputer from device data output line SDO, single-chip microcomputer is sent to computing machine by serial ports, and this can meet the demand of in the application in a little DATA REASONING field, data being carried out to display analysis.

What finally illustrate is, above embodiment is only in order to illustrate the technical solution of the utility model and unrestricted, although be described in detail the utility model with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify to the technical solution of the utility model or equivalent replacement, and not departing from aim and the scope of technical solutions of the utility model, it all should be encompassed in the middle of right of the present utility model.

Claims

1. the single-chip computer control system utilizing CPLD to realize ports-Extending, it is characterized in that: comprise single-chip microcomputer and CPLD chip, described single-chip microcomputer realizes being electrically connected by SPI serial communication interface and CPLD chip: the first input/output port of single-chip microcomputer is connected with the first input/output port of CPLD chip, and connecting line is designated as from device data input line SDI; Second input/output port of single-chip microcomputer is connected with the second input/output port of CPLD chip, and connecting line is designated as from device data output line SDO; 3rd input/output port of single-chip microcomputer is connected with the 3rd input/output port of CPLD chip, and connecting line is designated as clock cable SCLK; 4th input/output port of single-chip microcomputer is connected with the 4th input/output port of CPLD chip, and connecting line is designated as from devices enable signal wire CS.

2. a kind of CPLD of utilization according to claim 1 realizes the single-chip computer control system of ports-Extending, it is characterized in that, described single-chip microcomputer is connected with computing machine by serial ports.