CN211149445U

CN211149445U - High-speed data processing platform

Info

Publication number: CN211149445U
Application number: CN201921988126.9U
Authority: CN
Inventors: 陶思宇; 孙舟; 石建华; 王国辉; 王江涛; 郭奇; 蔡佳欣
Original assignee: Xi'an Ziguo Micro Technology Co ltd
Current assignee: Xi'an Ziguo Micro Technology Co ltd
Priority date: 2019-11-18
Filing date: 2019-11-18
Publication date: 2020-07-31
Anticipated expiration: 2029-11-18

Abstract

The utility model relates to a high-speed data processing platform, including two sets of two DSP minimum systems, FPGA control module, power network and interface unit, two DSP minimum systems are the hardware platform core, adopt 4 high performance multicore DSPs, 4 DSPs divide into two sets ofly, two DSP minimum systems are constituteed to 2 DSPs, two DSP minimum systems of every group are equipped with independent electrical power generating system, realize the interconnection through the high-speed bus, FPGA control module mainly realizes that DSP is gone up from loading mode configuration control, power is gone up supervisory control, clock network configuration control, L ED monitoring indicator lamp logic control, logic control resets, power network provides the electric energy for whole processing platform, interface unit includes VPX interface and front panel interface two parts, two DSP minimum system clock adopt CDCE62005 multichannel clock frequency synthesizer to realize the clock network of minimum system, two DSP minimum system power core voltage select UCD9244+ UCD7242 programmable digital combination for use.

Description

High-speed data processing platform

Technical Field

The utility model belongs to computer network application, concretely relates to high-speed data processing platform.

Background

The existing high-speed data processing platform is a system platform combining a hardware system platform and a software distribution implementation component technology, and comprises a plurality of heterogeneous processing units, wherein the heterogeneous processing units adopt different chip technologies and hardware architectures, the plurality of processing units form a cooperative cluster based on Ethernet, a software system of a distributed intrusion detection system performs parallel computation on the cluster, and high-efficiency communication and high-efficiency processing synchronization mechanisms are realized among the processing units, so that another solution of a high-performance intrusion detection system is provided, and when a large amount of application data is analyzed and processed, a data packet is distributed to different data processing analysis units for processing, so that the problem that the single system is overloaded and the performance is reduced is avoided.

However, the existing high-speed data processing platform has low hardware reliability and poor function expansibility, can only be used in specific common occasions, has wide application range, and cannot completely meet the requirements of industries such as industrial automation, radar, autopilot, military and the like.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the above problem, provide a high-speed data processing platform of goods posture, high reliability and function expansibility.

In order to achieve the above object, the utility model provides a following technical scheme:

a high-speed data processing platform comprises two groups of double-DSP minimum systems, an FPGA control module, a power network and an interface part, wherein the double-DSP minimum system is a hardware platform core and adopts 4 pieces of high-performance multi-core DSPs, the 4 pieces of DSPs are divided into two groups, 2 pieces of DSPs form the double-DSP minimum system, each group of double-DSP minimum system is provided with an independent power system and is interconnected through a high-speed bus;

the dual-DSP minimum system clock adopts a CDCE62005 multi-path clock frequency synthesizer to realize a clock network of a minimum system; the dual-DSP minimum system power supply core voltage selects a programmable digital combination of UCD9244+ UCD 7242.

Further, the double-DSP minimum system adopts a TMS320C6678 processor, the TMS320C6678 processor is provided with a DDR3 high-speed external memory control interface with 64-bit bus width, the DDR3 high-speed external memory control interface is divided into three parts of address, control and data, and is connected BY adopting an F L Y-BY topology.

Furthermore, the processing platform meets the requirements of high-speed data exchange between chips and between boards through a high-speed bus, and realizes system management, monitoring and debugging through a low-speed bus; the high-speed bus comprises an SRIO high-speed serial bus, a PCIe high-speed bus and a Hyperlink high-speed bus, and the low-speed bus comprises a UART and an I2C common bus.

Furthermore, the PCB design of the processing platform adopts a blind buried hole design.

Further, the TMS320C6678 processor internal DDR3 memory interface employs standard HST L _1.5V level logic.

Furthermore, TPS74401 is selected as the power supply I/O voltage of the double-DSP minimum system, a TPS54620+ TPS51200 combination is selected as the voltage of DDR3, and TPS74401 power supplies are selected as the power supply parts of the FPGA and the interface except a PTH08T240W switch power supply part of 3.3V.

Compared with the prior art, the beneficial effects of the utility model reside in that:

the utility model discloses processing platform satisfies the demand of high-speed data interchange between the piece and between the board through high-speed bus, realizes system management, control and debugging through low-speed bus, can satisfy most users to high performance digital signal processing and image processing's demand. The high-speed system adopted by the processing platform has high data processing speed, large power consumption and high requirements on signal integrity and power integrity. The reliable signal integrity and power integrity design not only can improve the reliability of the system, but also can play a certain role in the heat dissipation capacity of the system. The PCB is designed by adopting a blind buried hole, so that the wiring density can be improved, and the device placing space can be increased; the platform can be used as a radio digital baseband platform and a digital image processing verification platform, can meet the requirements of a weapon equipment system on signal and image real-time processing, is suitable for signal processing systems such as radar, image and sonar, can be applied to research in the fields related to industrial automation, radar, automatic driving and the like, and has high reliability, strong function expansibility and strong universality.

Drawings

In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings required to be used in the description of the embodiment will be briefly introduced below, it is obvious that the drawings in the following description are only for more clearly illustrating the embodiment of the present invention or the technical solution in the prior art, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative effort.

Fig. 1 is a block diagram of the platform bus interconnection structure of the present invention;

fig. 2 is a schematic diagram of the DDR3 interface of the present invention;

FIG. 3 is a schematic diagram of the dual DSP minimum system clock network connection of the present invention;

fig. 4 is a block diagram of the power network connection of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood by those skilled in the art, the present invention will be further described with reference to the following specific embodiments, which are provided as illustration only and are not intended to limit the present invention.

As shown in fig. 1 to 4, the high-speed data processing platform is a generalized, standardized, and modularized high-speed data processing platform, which considers the problems of signal integrity and power integrity at the initial stage of design, and fully considers the problems of signal and power quality influences, such as the wiring requirements of key signals, the current flow direction of a power system, the type selection and placement of filter capacitors, and the PCB lamination arrangement, at the stage of schematic diagram and PCB design. Meanwhile, in the later stage of PCB design, the PCB design is guided through signal integrity simulation and power integrity simulation.

The whole hardware platform comprises 2 groups of double-DSP minimum systems, an FPGA control module, a power network, an interface and the like, wherein the double-DSP minimum system is a hardware platform core, the 2 groups of minimum systems form a DSP array to realize high-performance data calculation, the FPGA control module mainly realizes control functions of DSP power-on self-loading mode configuration, power-on management, clock network configuration, L ED monitoring indicator light logic, reset logic and the like.

As shown in the block diagram of the platform bus interconnection structure of fig. 1: the hardware design of the high-speed data processing platform adopts a modular design idea, 4 DSPs are divided into two groups, 2 DSPs form a double-DSP minimum system, each group of minimum system is provided with an independent power supply system, and the 2 groups of double-DSP minimum systems are interconnected through a high-speed bus to complete the hardware design of the high-speed data processing platform.

The processing platform meets the requirement of high-speed data exchange between chips and between boards through a high-speed bus, and realizes system management, monitoring and debugging through a low-speed bus. The high-speed bus comprises an SRIO high-speed serial bus, a PCIe high-speed bus and a Hyperlink high-speed bus; the low-speed bus comprises a UART and an I2C common bus. The dual-DSP minimum system adopts a TMS320C6678 processor (hereinafter referred to as C6678), and in FIG. 1, C6678(1), C6678(2), C6678(3), and C6678(4) respectively represent

processors

1, 2, 3, and 4.

SRIO bus: the 1-path X1SRIO bus realizes the connection of the 1 processor, the 4 processor, the 2 processor and the 3 processor, and the 2-path X2SRIO bus realizes the connection of the 1 processor, the 2 processor, the 3 processor and the 4 processor; the 4-path X1SRIO realizes that the 1, 2, 3 and 4 processor is connected with the VPX back plate to be used as a connecting path with the main control equipment. SRIO bus communication rate is up to 5 Gbps.

PCIe bus: the 4 processors are respectively provided with a 1-path X2 PCIe bus interface connected with a VPX backplane to be used as an expansion bus interface. PCIe bus communication rates are up to 5 Gbps.

Hyperlink bus: the 4 processors on the board are divided into two groups, X4 Hyperlink buses are interconnected among each group and used as auxiliary fast data channels among the processing nodes, and the communication speed of each channel is 12.5Gbps at most.

Gigabit ethernet: the 2-way SGMII interface is respectively led out from the

processors

1 and 2 and connected to the RJ45 interface of the front panel through PHY. The 2-way SGMII interface is respectively led out from the

processors

3 and 4 and connected to the VPX backplane through PHY.

I2C bus: the I2C bus daisy-chains the 4 processors and connects them to the VPX backplane as a monitor and management interface for the entire board.

A UART bus: the UART bus is led out from the processor 1, and is converted into an RS485 interface through MAX3160 after being subjected to FPGA level conversion (1.8V to 3.3V). The interface acts as a debug interface.

The DDR3 interface schematic diagram shown in FIG. 2:

the C6678 High Speed external memory interface has a 64-bit bus width DDR3, the size of the memory space is 8Gb, the memory space supports 800, 1033, 1333, 1600MTS (Mega Transfers per second) data access rate, can be configured to 16bit, 32bit, 64bit bus width mode, can be interconnected with 8 pieces of DDR3SDRAM at most, the C6678 internal DDR3 memory interface adopts the standard HST L _1.5V (High Speed Transceiver L logic) level logic.

The DDR3 memory data bus that commonly uses is 8bit or 16bit, the utility model discloses a 4 pieces of DDR3SDRAM extensions that the bit wide is 16bit are 64bit memory cell and C6678's 64bit DDR3 storage control interface connection, every piece of C6678's storage capacity 8 Gb.DDR3 control interface divide into the address after the extension, control, the data triplex adopts "F L Y-BY" topology connection to satisfy the requirement of DDR3SDRAM to the chronogenesis.

Fig. 3 a dual DSP minimum system clock network:

the dual-DSP minimum system clock is more in types and mostly is differential level, the utility model discloses a CDCE62005 multi-path clock frequency synthesizer of TI company realizes the clock network design of minimum system, the multi-path clock frequency synthesizer supports 2 paths of differential clock inputs or 2 paths of single-end clock inputs, the input frequency range is 40 kHz-1500 MHz, 1 path of passive crystal inputs, the input frequency range is 2 MHz-42 MHz, the output end supports 5 paths of differential outputs, 10 paths of single-end outputs or differential single-end mixed output modes, the output frequency range is 4.25 MHz-1.5 GHz, the input and output support multiple level logic (L VDS, &lttttranslation = L "&gttTtTtL/T &gttVPEC L VCMOS). CDCE62005 has a path of SPI interface to realize P LL and clock frequency configuration, the SPI interface is realized by FPGA logic and realizes the configuration to CDCE 62005.

As shown in fig. 4, the power network connection block diagram:

the double-DSP minimum system power supply mainly supplies power to the two DSPs, and the two DSPs adopt an independent power supply design. The core voltage is combined by UCD9244+ UCD7242 programmable numbers, the I/O voltage is combined by TPS74401, and the DDR3 voltage is combined by TPS54620+ TPS51200, so that the DSP power supply can be realized. Except that the FPGA and interface power supply part adopts a PTH08T240W switch power supply for 3.3V, the rest power supplies all adopt TPS74401 power supplies.

The utility model provides a low-cost, convenient easy-to-use function is complete, the reliability is high and the high-speed data processing platform that function expansibility is strong. The high-speed system adopted by the platform has high data processing speed, large power consumption and high requirements on signal integrity and power integrity. The reliable signal integrity and power integrity design not only can improve the reliability of the system, but also can play a certain role in the heat dissipation capacity of the system. The method is generally suitable for research in the fields related to industrial automation, radar, automatic driving and the like, and has strong universality.

The utility model discloses what the main protection was hardware part, other not do the content of detailed description are prior art.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed data processing platform is characterized by comprising two groups of double-DSP minimum systems, an FPGA control module, a power network and an interface part, wherein the double-DSP minimum system is a hardware platform core and adopts 4 pieces of high-performance multi-core DSPs, the 4 pieces of DSPs are divided into two groups, 2 pieces of DSPs form the double-DSP minimum system, each group of the double-DSP minimum system is provided with an independent power system and is interconnected through a high-speed bus;

2. The platform of claim 1, wherein the dual-DSP minimal system employs a TMS320C6678 processor, the TMS320C6678 processor is provided with a DDR3 high-speed external memory control interface with 64-bit bus width, and the DDR3 high-speed external memory control interface is divided into three parts, namely address, control and data, and is connected BY adopting an "F L Y-BY" topology.

3. The high-speed data processing platform according to claim 1, wherein the processing platform meets the requirement of high-speed data exchange between chips and boards through a high-speed bus, and realizes system management, monitoring and debugging through a low-speed bus; the high-speed bus comprises an SRIO high-speed serial bus, a PCIe high-speed bus and a Hyperlink high-speed bus, and the low-speed bus comprises a UART and an I2C common bus.

4. A high speed data processing platform according to claim 1, wherein said processing platform PCB design employs a blind buried via design.

5. The high speed data processing platform of claim 2, wherein the TMS320C6678 processor internal DDR3 memory interface employs standard HST L _1.5V level logic.

6. A high-speed data processing platform according to any one of claims 1 to 5, wherein the dual DSP minimum system power I/O voltage is TPS74401, the DDR3 voltage is TPS54620+ TPS51200 combination, the FPGA and interface power supply part uses TPS74401 power supply except for 3.3V PTH08T240W switch power supply.