CN107704407A - A kind of system and method for being used for data processing between SPI and UART - Google Patents
A kind of system and method for being used for data processing between SPI and UART Download PDFInfo
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- CN107704407A CN107704407A CN201711065736.7A CN201711065736A CN107704407A CN 107704407 A CN107704407 A CN 107704407A CN 201711065736 A CN201711065736 A CN 201711065736A CN 107704407 A CN107704407 A CN 107704407A
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- China
- Prior art keywords
- uart
- spi
- data
- cpld
- protocol conversion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
Abstract
Include the invention discloses a kind of for the system of data processing and anti-method, the system between SPI and UART：The spi bus of data exchange is carried out for the BMC with storage system；Connected with spi bus and UART buses, for carrying out the CPLD of protocol conversion；For connecting CPLD and host computer UART buses.Protocol conversion between spi bus and UART buses is realized using CPLD, due to being bound to use CPLD in storage system, so it can reduce by an extended chip for being exclusively used in protocol conversion, not only reduce device cost, more it is reduction of the overall cost of hardware design of storage system, CPLD stability ensure that the stability of protocol conversion simultaneously, so as to can more improve the overall stability of storage system, and reduce the power consumption of storage system.
Description
Technical field
The present invention relates to technical field of memory, more particularly to a kind of system for being used for data processing between SPI and UART
And method.
Background technology
In this current big data epoch, high in the clouds becomes a part essential in people's life, such as cloud space, respectively
Large resource website etc., this storage device for just needing capacity huge support the operation in these high in the clouds.
The information security of storage beyond the clouds becomes key point, and information security not only refers to confidentiality, in addition to is not easy
The property lost, that is, the information preserved beyond the clouds are not lost, then the stability of storage system is just into key.In some current
In the design of storage device, SPI and UART are the necessary buses used, and the method changed between SPI and UART buses is also all
It is that the single extended chips of UART buses is turned by SPI to complete.Within the storage system, cost and stability are that people pursue
Target.
Therefore, the cost and can that how can reduce storage system improves its stability, is that those skilled in the art are current
The technical issues that need to address.
The content of the invention
, can it is an object of the invention to provide a kind of system and method for being used for data processing between SPI and UART
The cost and can for reducing storage system improves its stability.
In order to solve the above technical problems, the invention provides following technical scheme：
A kind of system for being used for data processing between SPI and UART, including：
The spi bus of data exchange is carried out for the BMC with storage system；
Connected with the spi bus and UART buses, for carrying out the CPLD of protocol conversion；
For connecting the UART buses of the CPLD and host computer.
Preferably, the CPLD includes：
For supporting the SPI modules of spi bus agreement；
It is connected with the SPI modules, carries out the Function modules of protocol conversion；
It is connected with the Function modules, supports the UART modules of UART bus protocols.
Preferably, the Function modules include：
For depositing SPI data and/or UART serial datas, and the string that the SPI data conversions can be read into UART
Line number is converted into the register for the data that SPI can be read according to this and by the UART serial datas；
For the controller units interrupt and register controls.
Preferably, the UART modules include：
For storing the UART baud rates of default fixation and the memory cell of verification mode information；
For performing the processing unit of corresponding actions according to the storage information in the memory cell and the instruction received.
A kind of method for being used for data processing between SPI and UART, including：
Obtain SPI data and/or UART serial datas；
Itself default protocol conversion is called to instruct by the CPLD connected with spi bus and UART buses；
Corresponding protocol conversion is carried out to the data of acquisition according to protocol conversion instruction；
The data obtained after conversion are exported by corresponding bus.
Compared with prior art, above-mentioned technical proposal has advantages below：
A kind of system for being used for data processing between SPI and UART provided by the present invention, including：For and storage system
BMC carry out data exchange spi bus；Connected with spi bus and UART buses, for carrying out the CPLD of protocol conversion；
For connecting CPLD and host computer UART buses.Protocol conversion between spi bus and UART buses is realized using CPLD, by
It is bound to use CPLD in storage system, it is possible to reduce by an extended chip for being exclusively used in protocol conversion, not only reduce
Device cost, the overall cost of hardware design of storage system is more reduction of, while CPLD stability ensure that agreement turns
The stability changed, so as to can more improve the overall stability of storage system, and reduce the power consumption of storage system.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
The system knot for being used for data processing between SPI and UART that Fig. 1 is provided for a kind of embodiment of the present invention
Structure schematic diagram；
Fig. 2 is used between SPI and UART in the system of data processing for what a kind of embodiment of the present invention was provided
CPLD structural representations.
Embodiment
The core of the present invention is to provide a kind of system and method for being used for data processing between SPI and UART, can
The cost and can for reducing storage system improves its stability.
In order that the above objects, features and advantages of the present invention can become apparent it is understandable, below in conjunction with the accompanying drawings to this hair
Bright embodiment is described in detail.
Detail is elaborated in the following description in order to fully understand the present invention.But the present invention can with it is a variety of not
Other manner described here is same as to implement, those skilled in the art can do class in the case of without prejudice to intension of the present invention
Like popularization.Therefore the present invention is not limited to the specific embodiments disclosed below.
Fig. 1 is refer to, Fig. 1 is used between SPI and UART at data for what a kind of embodiment of the present invention was provided
The system structure diagram of reason.
A kind of embodiment of the present invention provides a kind of system for being used for data processing between SPI and UART, bag
Include：The spi bus 11 of data exchange is carried out for the BMC with storage system；Connect, be used for spi bus and UART buses
Carry out the CPLD12 of protocol conversion；For connecting CPLD and host computer UART buses 13.
CPLD (Complex Programmable Logic Device) is CPLD, SPI
(Serial Peripheral Interface) is Serial Peripheral Interface (SPI), UART (Universal Asynchronous
Receiver/Transmitter) it is universal asynchronous receiving-transmitting transmitter.In the present embodiment, using CPLD as storage system
While control chip, also increase the function of protocol conversion for it.Wherein it is possible to carried out using Verilog hardware description languages
Programming.The system command that the BMC (baseboard management controller) of storage system is sent is based on spi bus agreement to CPLD, is passed through
Cross after CPLD conversion, be converted into UART, the transmission for being conveniently attached to UART ports to be instructed, so as to be to storage
System current state is controlled, and makes command adapted thereto.Due to being bound to use CPLD in storage system, it is possible to reduce one
The extended chip of protocol conversion is exclusively used in, not only reduces device cost, the overall hardware for being more reduction of storage system is set
Cost is counted, while CPLD stability ensure that the stability and high efficiency of protocol conversion, it is whole so as to can more improve storage system
The stability of body, and reduce the power consumption of storage system.
Fig. 2 is refer to, Fig. 2 is used between SPI and UART at data for what a kind of embodiment of the present invention was provided
CPLD structural representations in the system of reason.
Further, CPLD12 includes：For supporting the SPI modules 121 of spi bus agreement；It is connected, enters with SPI modules
The Function modules 122 of row protocol conversion；It is connected with Function modules, supports the UART modules 123 of UART bus protocols.
Further, Function modules 122 include：For depositing SPI data and/or UART serial datas, and will
SPI data conversions are converted into posting for the data that SPI can be read into the UART serial datas that can be read and by UART serial datas
Storage 1221；For the controller units 1222 interrupt and register controls.
UART modules include：For storing the UART baud rates of default fixation and the memory cell of verification mode information；
For performing the processing unit of corresponding actions according to the storage information in memory cell and the instruction received.
In the present embodiment, CPLD mainly includes three modules when realizing protocol conversion function：
SPI modules be one realize standard SPI transmission module, be mainly used in by SPI protocol to BMC send instruction and
The data that BMC is sent by SPI protocol are received, SPI is a kind of synchronous serial Peripheral Interface, and it can make MCU and various peripheries
Equipment is communicated to exchange information in a serial fashion.SPI modules have three registers to be respectively：Control register SPCR, shape
State register SPSR, data register SPDR.Ancillary equipment includes FLASHRAM, network controller, LCD display drivers, A/D
Converter and MCU etc..SPI modules can directly with each manufacturer production multiple standards peripheral components direct interface, the interface one
As use 4 lines：Serial time clock line (SCLK), main frame input/slave output data line MISO, main frame output/slave input number
According to line MOSI and the effective slave selection line NSS of low level, (the SPI interface chip having carries interrupt signal line INT, the SPI having
Interface chip does not have main frame output/slave input data line MOSI), optionally it is configured.
UART modules are mainly to receive the serial data that host computer transmits, and send beating for storage system to host computer
Official seal ceases.UART modules be preferably according to standard UART bus protocols simplify after functional module, now UART baud rate,
Verification mode has all secured, the purpose for the arrangement is that not only realizing the function of UART data transfers but also reducing UART modules
Shared CPLD logical resource.
Function modules are cores, mainly realize the conversion of agreement.It deposits the SPI received data
The serial data that UART can be read is converted into inside to register, is then exported by UART；The UART serial numbers that will be received
The data that SPI is converted into inside register and can be read according to being stored in, then SPI modules, which are called, is transferred to BMC.Pass through
Controller units inside Function modules realize the control to interruption and register, and are entered by Function modules
Row data syn-chronization, realize the communication between asynchronous data, that is to say, that Function modules can be by SPI data and UART modules institute
The data come into carry out parsing and are stored in register, while SPI modules and UART modules also can be simultaneously to Function modules
The register collected carries out accessible reading and calling.
Super I/O chips are substituted using CPLD, realize the conversion of agreement between spi bus and UART buses.Because
Chip inherently has crash rate, and present embodiment reduces the usage amount of whole system chip, can not only reduce whole system
Cost, but also the stability of system can be improved.The use of chip is reduced, while the power consumption of circuit board can also be reduced, and
Some signal wires are advantageously reduced, are advantageous to layout cablings.CPLD is wide variety of hardware module in each system simultaneously, is led to
Cross CPLD and realize that the function can be more widely used.
Correspondingly, present invention also offers a kind of method for being used for data processing between SPI and UART, including：
Obtain SPI data and/or UART serial datas；
Itself default protocol conversion is called to instruct by the CPLD connected with spi bus and UART buses；
Corresponding protocol conversion is carried out to the data of acquisition according to protocol conversion instruction；
The data obtained after conversion are exported by corresponding bus.
In the present embodiment, the protocol conversion of itself is called to instruct the SPI data of acquisition by conversion by CPLD
Exported afterwards by UART buses, by the UART data of acquisition it is converted after export through spi bus.Only need to set association in CPLD in advance
Discuss the instruction of conversion and perform the processor of command adapted thereto.
Protocol conversion between spi bus and UART buses is realized using CPLD, due to being bound to use in storage system
CPLD, it is possible to reduce by an extended chip for being exclusively used in protocol conversion, not only reduce device cost, be more reduction of and deposit
The overall cost of hardware design of storage system, while CPLD stability ensure that the stability of protocol conversion, so as to can more improve
The overall stability of storage system, and reduce the power consumption of storage system.
Above to it is provided by the present invention it is a kind of be used between SPI and UART the system and method for data processing carried out in detail
It is thin to introduce.Specific case used herein is set forth to the principle and embodiment of the present invention, and above example is said
It is bright to be only intended to help the method and its core concept for understanding the present invention.It should be pointed out that the ordinary skill for the art
For personnel, under the premise without departing from the principles of the invention, some improvement and modification, these improvement can also be carried out to the present invention
Also fallen into modification in the protection domain of the claims in the present invention.
Claims (5)
- A kind of 1. system for being used for data processing between SPI and UART, it is characterised in that including：The spi bus of data exchange is carried out for the BMC with storage system；Connected with the spi bus and UART buses, for carrying out the CPLD of protocol conversion；For connecting the UART buses of the CPLD and host computer.
- 2. system according to claim 1, it is characterised in that the CPLD includes：For supporting the SPI modules of spi bus agreement；It is connected with the SPI modules, carries out the Function modules of protocol conversion；It is connected with the Function modules, supports the UART modules of UART bus protocols.
- 3. system according to claim 2, it is characterised in that the Function modules include：For depositing SPI data and/or UART serial datas, and the serial number that the SPI data conversions can be read into UART The register for the data that SPI can be read is converted into according to this and by the UART serial datas；For the controller units interrupt and register controls.
- 4. system according to claim 3, it is characterised in that the UART modules include：For storing the UART baud rates of default fixation and the memory cell of verification mode information；For performing the processing unit of corresponding actions according to the storage information in the memory cell and the instruction received.
- A kind of 5. method for being used for data processing between SPI and UART, it is characterised in that including：Obtain SPI data and/or UART serial datas；Itself default protocol conversion is called to instruct by the CPLD connected with spi bus and UART buses；Corresponding protocol conversion is carried out to the data of acquisition according to protocol conversion instruction；The data obtained after conversion are exported by corresponding bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711065736.7A CN107704407A (en) | 2017-11-02 | 2017-11-02 | A kind of system and method for being used for data processing between SPI and UART |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711065736.7A CN107704407A (en) | 2017-11-02 | 2017-11-02 | A kind of system and method for being used for data processing between SPI and UART |
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| CN107704407A true CN107704407A (en) | 2018-02-16 |
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| CN201711065736.7A Pending CN107704407A (en) | 2017-11-02 | 2017-11-02 | A kind of system and method for being used for data processing between SPI and UART |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108920392A (en) * | 2018-05-17 | 2018-11-30 | 歌尔科技有限公司 | A kind of conversion equipment and method of data-interface and SPI |
| CN110928813A (en) * | 2019-11-18 | 2020-03-27 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| CN113590520A (en) * | 2021-06-15 | 2021-11-02 | 珠海一微半导体股份有限公司 | Control method for automatically writing data into SPI system and SPI system |
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| CN202870808U (en) * | 2012-07-04 | 2013-04-10 | 四川九洲电器集团有限责任公司 | FPGA realization device of SPI serial port module |
| CN103440219A (en) * | 2013-08-23 | 2013-12-11 | 上海航天测控通信研究所 | Novel general bus transforming bridge IP core |
| CN105680900A (en) * | 2016-03-21 | 2016-06-15 | 北京龙鼎源科技股份有限公司 | Data transmission system and method |
| CN106445853A (en) * | 2016-08-30 | 2017-02-22 | 天津天地伟业数码科技有限公司 | Transformation method of SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver/Transmitter) interface on the basis of FPGA (Field Programmable Gate Array) |
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2017
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| CN202167015U (en) * | 2011-08-19 | 2012-03-14 | 湖南文理学院 | Serial interface converting circuit |
| CN202870808U (en) * | 2012-07-04 | 2013-04-10 | 四川九洲电器集团有限责任公司 | FPGA realization device of SPI serial port module |
| CN103440219A (en) * | 2013-08-23 | 2013-12-11 | 上海航天测控通信研究所 | Novel general bus transforming bridge IP core |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108920392A (en) * | 2018-05-17 | 2018-11-30 | 歌尔科技有限公司 | A kind of conversion equipment and method of data-interface and SPI |
| CN110928813A (en) * | 2019-11-18 | 2020-03-27 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| CN113590520A (en) * | 2021-06-15 | 2021-11-02 | 珠海一微半导体股份有限公司 | Control method for automatically writing data into SPI system and SPI system |
| CN113590520B (en) * | 2021-06-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Control method for automatically writing data in SPI system and SPI system |
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