CN104714618A

CN104714618A - Reset circuit

Info

Publication number: CN104714618A
Application number: CN201310668578.XA
Authority: CN
Inventors: 高阳
Original assignee: Hongfujin Precision Electronics Tianjin Co Ltd; Hon Hai Precision Industry Co Ltd
Current assignee: Hongfujin Precision Electronics Tianjin Co Ltd
Priority date: 2013-12-11
Filing date: 2013-12-11
Publication date: 2015-06-17

Abstract

A reset circuit is used for making a chip reset. The chip comprises a reset end. The reset circuit comprises a power end, a power-on reset module and a start reset module. The power-on reset module is connected between the power end and the reset end of the chip. When the power end is powered on, the output end of the power-on reset module outputs a low level signal to the reset end of the chip, and the chip resets. After power-on is completed, the power-on reset module outputs a high level signal, and the chip enters the working state. The start reset module comprises a switch. The first end of the switch is connected with the power end and the reset end of the chip, and the second end of the switch is grounded. After power-on of the power end is completed, the switch is switched on so that the reset end of the chip can be grounded, and the chip resets. Compared with the prior art, the chip can be controlled by the power-on reset module and the start reset module of the reset circuit to reset when the power end is powered on and after power-on is completed.

Description

Reset circuit

Technical field

This relates to a kind of reset circuit.

Background technology

When standby power starts to power on, a reset operation can be performed to CPLD chip on mainboard (Complex Programmable Logic Device, CPLD).When system is restarted because of fault, CPLD chip cannot reset and retain error messages when breaking down, the operation of meeting influential system.

Summary of the invention

In view of this, be necessary to provide a kind of can to the reset circuit of chip reset.

A kind of reset circuit, in order to the chip that resets, this chip comprises a reset terminal, and this reset circuit comprises:

One power end;

One electrification reset module, be connected between this power end and reset terminal of chip, when power end powers on, the output terminal of this electrification reset module exports the reset terminal of a low level signal to chip, this chip reset, after having powered on, this electrification reset module exports high level signal, and chip enters duty; And

One starts reseting module, and this startup reseting module comprises a switch, and the first end of switch connects the reset terminal of power end and chip, and the second end ground connection of this switch, after power end has powered on, Closing Switch makes the reset terminal ground connection of chip, chip reset.

Compare prior art, the electrification reset module of reset circuit of the present invention and startup reseting module can control chip resets when power end powers on and after having powered on respectively.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of reset circuit of the present invention.

Main element symbol description

Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.

Embodiment

Please refer to Fig. 1, the better embodiment of reset circuit of the present invention is used for resetting to a chip 30, and this reset circuit comprises a power end VCC, an electrification reset module 10 and starts reseting module 20.This startup reseting module 20 is also in order to control the supply module 40 that can be main board power supply.

Power end VCC is standby power.In the present embodiment, chip 30 is the CPLD chip (Complex Programmable Logic Device, CPLD) of mainboard, and it comprises a reset terminal CLR.When reset terminal CLR receives low level signal, chip 30 resets; When reset terminal CLR receives high level signal, chip 30 enters duty.

This supply module 40 comprises South Bridge chip 410, triode Q and a power supply 420.This South Bridge chip 410 comprises a power management module 411, and this power management module 411 comprises an an input pin I1 and output pin O1.This power supply 420 comprises a control end ON.The base stage of this triode Q connects output pin O1, and the emitter of this triode Q connects the control end ON of power end VCC and power supply 420, the grounded collector of this triode Q.When input pin I1 receives level signal from high to low, can triggering voltage administration module 411, control output pin O1 and export high level signal and low level signal.

This electrification reset module 10 comprises a resistance R1, electric capacity C1, C2 and phase inverter U1, U2.Power end VCC is by this resistance R1 and this electric capacity C1 ground connection, node between this resistance R1 with this electric capacity C1 is connected the input end of phase inverter U1, the output terminal of this phase inverter U1 connects the input end of phase inverter U2, and the output terminal of this phase inverter U2 connects the reset terminal CLR of chip 30.The power input of this phase inverter U1, U2 all connects power end VCC, the equal ground connection of ground connection input end.The power input of this phase inverter U2 is also by electric capacity C2 ground connection.

This startup reseting module 20 comprises a switch B, resistance R2 and electric capacity C3.In the present embodiment, this switch B one often opens key switch, and press this switch B, this switch B connects, and unclamps this switch B, and this switch B disconnects.The two ends of this switch B are provided with two groups of links.Resistance R2 and electric capacity C3 is connected between power end VCC and ground, and two links of the first end of switch B connect the node between this resistance R2 and this electric capacity C3, two link ground connection of second end of this switch B.Node between this resistance R2 with this electric capacity C3 is connected the reset terminal CLR of the chip 30 and input pin I1 of power management module 411.

When power end VCC powers on, electric capacity C1 starts charging, the input end of phase inverter U1 receives low level signal, its output terminal exports high level signal, the input end of phase inverter U2 receives high level signal, its output terminal output low level signal, the reset terminal CLR of chip 30 receives low level signal, and chip 30 resets.After electric capacity C1 charging terminates, the input end of phase inverter U1 receives high level signal, its output terminal output low level signal, the input end of phase inverter U2 receives low level signal, its output terminal exports high level signal, and the reset terminal CLR of chip 30 receives high level signal, and chip 30 enters duty.In the process, when C1 charging starts, the node output low level between resistance R2 and this electric capacity C3; After C3 charging terminates, the node between resistance R2 and this electric capacity C3 exports high level.

After power end VCC powers on, namely unclamp after the switch B of started by press reseting module 20, when switch B connects, the reset terminal CLR of the chip 30 and input pin I1 of power management module 411 is simultaneously by switch B ground connection.The reset terminal CLR of chip 30 receives low level signal, and chip 30 resets; Input pin I1 reception one level signal from high to low of power management module 411, power management module 411 is triggered and controls output pin O1 and exports the base stage of high level signal to triode Q to make this triode Q conducting, the control end ON of power supply 420 receives low level signal, and then power-on 420, can be mainboard and power supply is provided.

Namely unclamp after the switch B of started by press reseting module 20 again, chip 30 resets.Input pin I1 reception one level signal from high to low of power management module 411, power management module 411 is triggered and controls the base stage of output pin O1 output low level signal to triode Q, this triode Q ends, the control end ON of power supply 420 receives high level signal, and then powered-down 420, stop to main board power supply.

In the present embodiment, electric capacity C2 can play filtering and Anti-Jamming, thus can improve the stability of power end VCC.

The startup reseting module 20 of reset circuit of the present invention not only by resetting by the B control chip 30 that compresses switch, but also can control supply module 40 for main board power supply or stopping are to main board power supply.

Claims

1. a reset circuit, in order to the chip that resets, this chip comprises a reset terminal, and this reset circuit comprises:

One power end;

2. reset circuit as claimed in claim 1, is characterized in that: this chip is a CPLD chip.

3. reset circuit as claimed in claim 1, is characterized in that: this electrification reset module comprises and is connected on a resistance and an electric capacity between power end and ground, the node between the reset terminal contact resistance of chip and electric capacity.

4. reset circuit as claimed in claim 3, it is characterized in that: this electrification reset module also comprises one first phase inverter and one second phase inverter, the output terminal of this first phase inverter connects the input end of this second phase inverter, node between the input end contact resistance of the first phase inverter and electric capacity, the output terminal of the second phase inverter connects the reset terminal of chip.

5. reset circuit as claimed in claim 4, is characterized in that: the power input of this first phase inverter and this second phase inverter connects power end, earth terminal ground connection, and the power input of the second phase inverter is also by one second capacity earth.

6. reset circuit as claimed in claim 1, is characterized in that: the first end of this switch connects the supply module that can be main board power supply.

7. reset circuit as claimed in claim 6, it is characterized in that: this supply module comprises a South Bridge chip, one triode and a power supply, this South Bridge chip comprises a power management module, the input pin of power management module connects the first end of this switch, the base stage of the output pin connecting triode of power management module, the collector of triode connects the control end of power end and power supply, the grounded emitter of triode, input pin receives one can control the base stage of output pin outputs level signals to triode to control conducting and the cut-off of this triode by triggering voltage administration module by the level signal of high step-down.

8. reset circuit as claimed in claim 7, is characterized in that: the control end of this power supply receives low level signal, electric power starting; The control end of power supply receives high level signal, power-off.

9. reset circuit as claimed in claim 1, is characterized in that: start reseting module and also comprise and be connected on a resistance between power end and ground and an electric capacity, the first end of switch connects the node between this resistance and electric capacity.

10. reset circuit as claimed in claim 1, is characterized in that: this switch is one often open key switch.