CN1932718A - Method and circuit for processing chip reset - Google Patents
Method and circuit for processing chip reset Download PDFInfo
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- CN1932718A CN1932718A CN 200610117147 CN200610117147A CN1932718A CN 1932718 A CN1932718 A CN 1932718A CN 200610117147 CN200610117147 CN 200610117147 CN 200610117147 A CN200610117147 A CN 200610117147A CN 1932718 A CN1932718 A CN 1932718A
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Abstract
The invention discloses a circuit used for slug resetting. It consists of two triggering units which are used to trigger asynchronous resetting signal and synchronous resetting signal and a logical combination unit. The output port of the one triggering unit was connected to the asynchronous resetting port of the other one. The output ports of the two triggering units were connected to the input port of the logical combination unit. The resetting signals were combined and connected to the asynchronous end of all triggers in the system clock. Asynchronous resetting and synchronous resetting were realized by this invention.
Description
Technical field
The present invention relates to the microelectronics design, process chip resets in especially a kind of Design of Digital Integrated Circuit method and circuit.
Background technology
In digital integrated circuit chip, for guaranteeing the operate as normal of chip, reset circuit is indispensable part.Along with the continuous increase of chip-scale, the access way of the structure of reset circuit and it and other circuit also becomes increasingly complex.Especially in ultra-large integrated circuit (IC) chip, generally have a plurality of clock zones, each clock zone all can have synchronous reset signal separately; In addition, chip also can provide the asynchronous reset port, to play the effect of Global reset.Whether operate as normal is most important to entire chip owing to reset circuit, so its realization must be simple in structure, and the reliability height.
The existing chip resetting technique, it generally is the asynchronous resetting end that the chip asynchronous reset signal is connected to each clock zone trigger element, and simultaneously the synchronous reset signal of each clock zone is connected to the synchronous clear terminal of this clock zone trigger element, to realize the asynchronous and synchronous zero clearing (resetting) of trigger.
One that is illustrated in figure 1 as existing reset circuit links synoptic diagram, comprise two d type flip flop A, B, wherein, system clock Sys_clk meets the digital input end D of d type flip flop A, B respectively, asynchronous reset signal Async_rst inserts the asynchronous resetting end R of d type flip flop A, B, and synchronous reset signal Sync_rst inserts the synchronous clear terminal SC of d type flip flop A, B.The defective of this design is:
At first, the asynchronous resetting end R of all triggers and synchronous clear terminal SC have inserted reset signal in the chip, cause the wiring of signal reset signal complicated, and area occupied is big, increases power consumption, has prolonged the development time to circuit design;
Secondly, ultra-large digital integrated circuit is because the clock frequency height, generally all adopt Synchronization Design, it is synchronous therefore requiring the inefficacy (" the jumping out " of withdrawing from reset mode or resetting) of reset signal, and all registers all are in stable original state after could guaranteeing like this to reset.And the reset circuit that application has earlier, asynchronous reset signal is directly connect the register asynchronous resetting end of (being made up of some trigger elements), it withdraws from reset mode is asynchronous, thereby causes the original state of each register uncertain, even can cause the chip cisco unity malfunction.Be illustrated in figure 2 as and insert two trigger A among Fig. 1, the sequential chart of the reset signal sequential chart of B and the output of Q end, as shown in the figure, reset signal is inconsistent to the time-delay of the asynchronous reset end R of trigger A with time-delay to the asynchronous reset end R of register B, if this time-delay differs bigger, will cause reset signal with respect to the position of clock signal deviation to take place: a reset signal is before rising edge clock arrives, and another reset signal is after rising edge clock arrives, this just probably causes the original state instability of chip, and can't guarantee that all registers in the same clock zone withdraw from reset mode in one-period, and the variation of reset signal effectively has enough big distance in the edge along relative time clock.
In the prior art, the trial that also promising solution reset mode can not be jumped out simultaneously, for example increase the time-delay impact damper reset signal is carried out compensation of delay, though but it has solved the problem that reset signal " is jumped out " synchronously, increased complexity, power consumption and the chip area of circuit design simultaneously because having increased more hardware cell.
Summary of the invention
Purpose of the present invention is to solve the above-mentioned technical matters in the existing reset mode, thereby a kind of method that process chip resets that is used for is provided.
A kind ofly be used for the method that process chip resets, comprise the step of importing a clock signal of system, an asynchronous reset signal and a synchronous reset signal from the outside, it is characterized in that this method also comprises:
Reset process comprises:
1) makes the described outside effective step of importing of asynchronous reset signal;
2) utilize a trigger element to export the step of effective internal asynchronous reset signal;
3) utilize the effective internal asynchronous reset signal of above-mentioned output and an outside described synchronous reset signal to trigger the step that the inside synchronous reset signal that generates carries out one first combinational logic operation generation, one combination reset signal; Reset mode is jumped out step, comprising:
1) step that the described outside asynchronous reset signal of importing was lost efficacy;
2) when described clock signal produce effectively trigger along the time, utilize described trigger element to export the step of the inside asynchronous reset signal of above-mentioned inefficacy;
3) utilize the inside asynchronous reset signal and the described inner synchronous reset signal of the inefficacy of above-mentioned output to carry out the described combination reset signal of described first combinational logic operation generation, and jump out the step of reset mode.
After above-mentioned inner synchronous reset signal and described inner asynchronous reset signal carried out described first logical combination operation, the described combination reset signal of generation inserted the asynchronous reset end of described chip follow-up register.
Above-mentioned first combinational logic is operating as when thereby described inner asynchronous reset signal or described inner synchronous reset signal effectively enter reset mode, also makes described combination reset signal enter the combinational logic operation steps of reset mode.
Above-mentioned first combinational logic is operating as when described inner asynchronous reset signal and described inner synchronous reset signal are jumped out reset mode, also makes described combination reset signal jump out the combinational logic operation steps of reset mode.
The present invention provides also that a kind of and said method are corresponding to be used for the circuit that process chip resets, and this circuit comprises:
Be used to trigger first trigger element of an asynchronous reset signal, comprise clock port, digital input port, asynchronous reset port and output port;
Be used to trigger second trigger element of a synchronous reset signal, comprise clock port, digital input port, asynchronous reset port and output port;
One combinatorial logic unit comprises several input ports and an output port; Wherein:
The output port of described first trigger element is connected with the asynchronous reset port of described second trigger element, and the output port of described first trigger element is connected with the input port of described combinatorial logic unit with the output port of described second trigger element.
When the output of the output port of the output port of described first trigger element or described second trigger element was effective, through after the described combinatorial logic unit, its output was also effective.When the output of the output port of the output port of described first trigger element or described second trigger element was invalid, through after the described combinatorial logic unit, its output was also invalid.
As a kind of embodiment of foregoing circuit, described combinatorial logic unit comprise one with door, the output port of the output port of described first trigger element and described second trigger element respectively with this with two input ends be connected.
Another kind of embodiment as foregoing circuit, described combinatorial logic unit comprise one with the door and a not gate, the output terminal of described not gate is connected with a described input end with door, the output port of described first trigger element is connected with described another input end with door, and the output port of described second trigger element is connected with the input end of described not gate.
The output terminal of combinations thereof logic can insert the deposit unit of chip, with the operation that resets and jump out reset mode that each deposit unit is unified.
Use said reset method and circuit to carry out chip design, synchronous reset and asynchronous reset can be integrated into a unified reset signal, and be applied in other triggers of chip, thereby greatly simplified the wiring of reset signal, and area is little, low in energy consumption; In addition,, can guarantee that all registers are released reset mode in the same clock zone in the same clock period, fully guarantee the stability of chip operation owing to adopt above-mentioned design.
Description of drawings
Fig. 1 is the schematic diagram of existing a kind of reset circuit;
Fig. 2 is the sequential chart of each signal among Fig. 1;
Fig. 3 is the module map of reset circuit of the present invention;
Fig. 4 is the circuit theory diagrams of an embodiment of reset circuit of the present invention;
Fig. 5 is the sequential chart of each signal among Fig. 4;
Fig. 6 is the circuit theory diagrams of another embodiment of reset circuit of the present invention;
Fig. 7 is the circuit theory diagrams of another embodiment of reset circuit of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the Method and circuits that is used for chip reset of the present invention is done detailed explanation.
Be the module map of reset circuit of the present invention as shown in Figure 3, as shown in the figure, this circuit comprises: be used to trigger first trigger element 100 of an asynchronous reset signal, comprise clock port 102, digital input port 104, asynchronous reset port one 06 and output port 108; Be used to trigger second trigger element 200 of a synchronous reset signal, comprise clock port 202, digital input port 204, asynchronous reset port 206 and output port 208; One combinatorial logic unit 300 comprises several input ports 302,304 and an output port 306; Wherein: the output port 108 of described first trigger element 100 is connected with the asynchronous reset port 206 of described second trigger element 200, and the output port 108 of described first trigger element 100 is connected with the input port 302,304 of described combinatorial logic unit with the output port 208 of described second trigger element 200.The output port 306 of combinational logic is connected with other registers of chip internal, is used to the operation that resets or jump out reset mode.In addition, a clock signal of system inserts the input end of clock mouth 102 of described first trigger element 100 and the output terminal of clock mouth 104 of second trigger element 200 respectively, is used to them that clock signal of system is provided.
Particularly, when carrying out reset operation, the asynchronous reset port one 06 of first trigger element 100 inserts the external asynchronous reset signal, and make this external asynchronous reset signal effective, at this moment, the effective reset signal of output port 108 outputs of trigger element 100, simultaneously, the digital input port 204 of second trigger element 200 inserts an external sync reset signal, the effective reset signal of output port 108 outputs of the efficient synchronization reset signal of its output port 208 outputs and trigger element 100 is carried out combinational logic then, thereby generates a combination reset signal.This combinatorial logic unit 300 guarantees that the output signal of its output port 306 is also effective when effective synchronous reset signal or asynchronous reset signal are effective.
Accordingly, when reset mode is jumped out, the asynchronous reset signal of described outside was lost efficacy, when described clock signal is effective, the asynchronous reset signal that utilizes 100 outputs of described first trigger element to lose efficacy; And then carry out described combinational logic operation with the synchronous reset signal of described output port 108 outputs, this combinatorial logic unit 300 is guaranteed when invalid synchronous reset signal or asynchronous reset signal are invalid, the output signal of its output port 306 is also invalid, thereby jumps out reset mode.
Below in conjunction with specific embodiment, each optimal way of more detailed description clock-reset circuit of the present invention, and they reset or reset mode is jumped out the principle and the step of operation.
Be illustrated in figure 4 as first embodiment of reset circuit of the present invention, as shown in the figure, this circuit comprises trigger DFF1 and DFF2, in the present embodiment, DFF1, DFF2 is d type flip flop, this circuit also comprise one with the door AND2, the input end of clock mouth connected system clock Sys_clk of trigger DFF1 wherein, it is the power Vcc (shown in A point among the figure) of high level that data-in port D often connects, asynchronous reset end R is that low level is effective, be connected to chip asynchronous reset signal Reset (shown in B point among the figure), output terminal Q can obtain a reset signal Async_rst who is synchronized to the Sys_clk clock zone; The data-in port of trigger DFF2 is connected to external sync reset signal Sync_in, external sync reset signal Sync_in produces the condition combination results by the clock zone synchronous reset, in the present embodiment, its low level is effective, the asynchronous reset port R of DFF2 connects above-mentioned asynchronous reset signal Async_rst, and export a synchronous reset signal Sync_rst, this synchronous reset signal Sync_rst and asynchronous reset signal Async_rst be connected to the input end of door AND2 mutually " with " after, obtain making up reset signal Sys_rst, this combination reset signal Sys_rst can connect into the asynchronous reset end of all registers of this clock zone (trigger), can realize asynchronous simultaneously and synchronous reset.
Be illustrated in figure 5 as the sequential chart that adopts the present embodiment circuit.In conjunction with Fig. 4, asynchronous reset signal Reset low level is effective, after Reset drags down (effectively), also step-down is (1. thereupon for Async_rst, asynchronous reset (zero clearing)), Reset draws high back (jumping out reset mode), and Async_rst waits until and just uprises (2., set (jumping out reset mode) synchronously) after the rising edge of clock Sys_clk arrives.
Be illustrated in figure 6 as the schematic diagram of another embodiment of reset circuit of the present invention, embodiment among itself and Fig. 4 is roughly the same, difference is, described synchronous reset signal Sync_rst is the effective signal of high level, at this moment, can be as shown in Figure 5, after Sync_rst process not gate INV negate, carry out mutually with asynchronous reset signal Async_rst again " with " combinational logic operation, thereby obtain low level and effectively make up reset signal Sys_rst, combination reset signal Sys_rst can be connected to asynchronous reset (zero clearing) end of all triggers of this clock zone, to realize asynchronous and synchronous reset.
Be illustrated in figure 7 as the circuit theory diagrams of another embodiment of reset circuit of the present invention, as shown in the figure, this circuit comprises two d type flip flop DFF1, DFF2, and two and a door AND2, wherein, one asynchronous reset signal Reset inserts the data-in port of d type flip flop DFF1, this reset signal Reset and carry out with the output port of DFF1 " with " logical operation, export an asynchronous reset signal Async_rst, one external sync reset signal Sync_in is connected with the data-in port of trigger DFF2, asynchronous reset signal Async_rst inserts the asynchronous reset port of DFF2, and the data-out port of DFF2 and asynchronous reset signal Async_rst by one with door AND2 mutually " with " after, by this output terminal output combination reset signal Sys_rst with door AND2.
Similar to the reset mode of above-mentioned two embodiment, utilize the reset circuit of present embodiment, when entering reset mode, at first the Reset signal is dragged down and enter reset mode, by E position Sheffer stroke gate among the figure Async_rst signal is also dragged down (as Fig. 4 1. shown in), then the Async_rst signal by the Sheffer stroke gate of F position among the figure Sys_rst signal is dragged down (as Fig. 4 3. shown in, asynchronous resetting), and the Sys_rst signal links to each other with the clear terminal of all registers of sys_clk clock zone in the chip, thereby makes all registers be in reset mode.When chip is jumped out reset mode, jumping out at first of reset mode drawn high from the Reset signal, because the Q end that meets DFF1 of the other end of E position Sheffer stroke gate institute still is low, so the Aysnc_rst signal temporarily also can not drawn high, rising edge up to next sys_clk, thereby DFF1 also puts height for high with the Q end owing to sample the Reset signal, the output Async_rst signal that is arranged in the Sheffer stroke gate of figure E position so just will uprise (as Fig. 4 2. shown in), transmit the Sheffer stroke gate of this F position then, thereby reset signal Sys_rst is drawn high (as Fig. 4 4. shown in, jump out synchronously), system jumps out reset mode.
In sum, utilize the Method and circuits for the treatment of chip reset of the present invention, can produce following beneficial effect:
1, the present invention resets synchronous and asynchronous and is integrated into a unified reset signal, and all triggers all use in the chip This signal has greatly been simplified the wiring of reset signal as asynchronous reset signal, and area is little, and is low in energy consumption, and test shows, Adopt this circuit, chip area can be dwindled about 5%.
2, the present invention has namely realized asynchronous reset, has realized again withdrawing from synchronously reset mode, so that all triggers after resetting All be in stable original state, thereby guaranteed the normal initialization of synchronous circuit.
3, the present invention is conducive to the temporal constraint of placement-and-routing in the chip design. It has guaranteed that in the same clock zone all post Storage withdraws from reset mode in the same clock cycle, and the variation of reset signal is enough along the distance on the effective edge of relative time clock Therefore, in chip design, can shorten the time of rear end placement-and-routing, thereby shorten the construction cycle greatly.
Claims (13)
1, a kind ofly be used for the method that process chip resets, comprise the step of importing a clock signal of system, an asynchronous reset signal and a synchronous reset signal from the outside, it is characterized in that this method also comprises:
Reset process comprises:
1) makes the described outside effective step of importing of asynchronous reset signal;
2) utilize a trigger element to export the step of effective internal asynchronous reset signal;
3) utilize the effective internal asynchronous reset signal of above-mentioned output and an outside described synchronous reset signal to trigger the step that the inside synchronous reset signal that generates carries out one first combinational logic operation generation, one combination reset signal; Reset mode is jumped out step, comprising:
1) step that the described outside asynchronous reset signal of importing was lost efficacy;
2) when described clock signal produce effectively trigger along the time, utilize described trigger element to export the step of the inside asynchronous reset signal of above-mentioned inefficacy;
3) utilize the inside asynchronous reset signal and the described inner synchronous reset signal of the inefficacy of above-mentioned output to carry out the described combination reset signal of described first combinational logic operation generation, and jump out the step of reset mode.
2, as claimed in claim 1ly be used for the method that process chip resets, it is characterized in that described trigger element is a d type flip flop.
3, as claimed in claim 2ly be used for the method that process chip resets, it is characterized in that effective asynchronous reset signal of described outside input is by inserting the asynchronous reset port output effective internal asynchronous reset signal of described d type flip flop.
4, as claimed in claim 2ly be used for the method that process chip resets, it is characterized in that, effective asynchronous reset signal of described outside input is by inserting the digital input port of described d type flip flop, and make the signal of output and this asynchronous reset signal carry out one second logical operation, thereby export effective reset signal.
5, as claimed in claim 1ly be used for the method that process chip resets, it is characterized in that, the synchronous reset signal of described outside input passes through to insert the digital input port of one second trigger element, and utilizes its output described inner synchronous reset signal of generation and described effective internal asynchronous reset signal to carry out described first combinational logic operation.
6, as claimed in claim 5ly be used for the method that process chip resets, it is characterized in that described effective internal asynchronous reset signal inserts the asynchronous reset port of described second trigger element.
7, the method that resets of process chip as claimed in claim 1, it is characterized in that, after described inner synchronous reset signal and described inner asynchronous reset signal carried out described first logical combination operation, the described combination reset signal of generation inserted the asynchronous reset end of described chip follow-up register.
8, the method that resets of process chip as claimed in claim 7, it is characterized in that, described first combinational logic is operating as when thereby described inner asynchronous reset signal or described inner synchronous reset signal effectively enter reset mode, makes described combination reset signal enter reset mode; When described inner asynchronous reset signal and described inner synchronous reset signal are jumped out reset mode, make described combination reset signal jump out the combinational logic operation steps of reset mode.
9, a kind ofly be used for the circuit that process chip resets, it is characterized in that this circuit comprises:
Be used to trigger first trigger element of an asynchronous reset signal, comprise clock port, digital input port, asynchronous reset port and output port;
Be used to trigger second trigger element of a synchronous reset signal, comprise clock port, digital input port, asynchronous reset port and output port;
One logical combination unit comprises several input ports and an output port; Wherein:
The output port of described first trigger element is connected with the asynchronous reset port of described second trigger element, and the output port of described first trigger element is connected with the input port of described logical combination unit with the output port of described second trigger element.
10, as claimed in claim 9ly be used for the circuit that process chip resets, it is characterized in that when the output of the output port of the output port of described first trigger element or described second trigger element was effective, through after the described combinatorial logic unit, its output was also effective; When the output of the output port of the output port of described first trigger element or described second trigger element was invalid, through after the described combinatorial logic unit, its output was also invalid.
11, as claimed in claim 9ly be used for the circuit that process chip resets, it is characterized in that the output terminal of described logical combination unit inserts the asynchronous reset end of other follow-up deposit units of this chip.
12, as claimed in claim 9ly be used for the circuit that process chip resets, it is characterized in that described asynchronous reset signal is connected with the asynchronous reset port of described first trigger element, a high level is connected with the digital input port of described first trigger element.Described synchronous reset signal is connected with the digital input port of described second trigger element.
13, as claimed in claim 9ly be used for the circuit that process chip resets, it is characterized in that, described asynchronous reset signal is connected with the digital input port of described first trigger element, the asynchronous reset port of described first trigger element is put sky, and, after the output port of described asynchronous reset signal and described first trigger element carries out logical operation, insert the asynchronous reset port of described second trigger element again, and be connected with the input port of described logical combination unit with the triggering port of described second trigger element.
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| CNB2006101171474A CN100464281C (en) | 2006-10-13 | 2006-10-13 | Method and circuit for processing chip reset |
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| CNB2006101171474A CN100464281C (en) | 2006-10-13 | 2006-10-13 | Method and circuit for processing chip reset |
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| CNB2006101171474A Expired - Fee Related CN100464281C (en) | 2006-10-13 | 2006-10-13 | Method and circuit for processing chip reset |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011100918A2 (en) * | 2011-04-13 | 2011-08-25 | 华为技术有限公司 | Resetting device |
| CN103944546A (en) * | 2014-03-28 | 2014-07-23 | 山东华芯半导体有限公司 | Device and method for preventing reset signal inside chip from losing efficacy |
| CN104850203A (en) * | 2015-06-10 | 2015-08-19 | 联想(北京)有限公司 | Electronic apparatus reset method and electronic apparatus |
| CN105024674A (en) * | 2015-03-13 | 2015-11-04 | 苏州迈瑞微电子有限公司 | Asynchronous resetting device |
| CN105425926A (en) * | 2015-12-22 | 2016-03-23 | 无锡芯响电子科技有限公司 | Controllable-bandwidth reset circuit capable of achieving asynchronous reset and synchronous release |
| CN109539908A (en) * | 2018-10-24 | 2019-03-29 | 重庆长安工业(集团)有限责任公司 | Electronic security(ELSEC) sequential control circuit |
| CN111857306A (en) * | 2020-07-30 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | SoC system universal reset method and system, universal reset unit and SoC reset circuit |
| CN112187233A (en) * | 2020-10-14 | 2021-01-05 | Oppo广东移动通信有限公司 | Reset device, method, clock system and electronic equipment |
| CN114327006A (en) * | 2021-12-22 | 2022-04-12 | 山东产研鲲云人工智能研究院有限公司 | Noc reset circuit, Noc chip, control method, control device and medium |
| CN116521604A (en) * | 2023-07-05 | 2023-08-01 | 芯耀辉科技有限公司 | Method for synchronizing data and related device |
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| US6480967B1 (en) * | 1999-05-21 | 2002-11-12 | Koninklijke Philips Electronics N.V. | Multiple module processing system with reset system independent of reset characteristics of the modules |
| DE10303673A1 (en) * | 2003-01-24 | 2004-08-12 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Asynchronous envelope for a globally asynchronous, locally synchronous (GALS) circuit |
| US6993671B2 (en) * | 2003-03-28 | 2006-01-31 | International Business Machines Corporation | High speed clock divider with synchronous phase start-up over physically distributed space |
| CN1297866C (en) * | 2004-08-18 | 2007-01-31 | 大唐微电子技术有限公司 | Reset method and reset system for integrated circuit |
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- 2006-10-13 CN CNB2006101171474A patent/CN100464281C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011100918A2 (en) * | 2011-04-13 | 2011-08-25 | 华为技术有限公司 | Resetting device |
| CN102204099A (en) * | 2011-04-13 | 2011-09-28 | 华为技术有限公司 | Resetting device |
| WO2011100918A3 (en) * | 2011-04-13 | 2012-01-12 | 华为技术有限公司 | Resetting device |
| CN102204099B (en) * | 2011-04-13 | 2013-04-17 | 华为技术有限公司 | Resetting device |
| CN103944546A (en) * | 2014-03-28 | 2014-07-23 | 山东华芯半导体有限公司 | Device and method for preventing reset signal inside chip from losing efficacy |
| CN105024674B (en) * | 2015-03-13 | 2018-06-12 | 苏州迈瑞微电子有限公司 | A kind of asynchronous reset |
| CN105024674A (en) * | 2015-03-13 | 2015-11-04 | 苏州迈瑞微电子有限公司 | Asynchronous resetting device |
| CN104850203A (en) * | 2015-06-10 | 2015-08-19 | 联想(北京)有限公司 | Electronic apparatus reset method and electronic apparatus |
| CN104850203B (en) * | 2015-06-10 | 2019-02-05 | 联想(北京)有限公司 | A kind of electronic equipment repositioning method and electronic equipment |
| CN105425926A (en) * | 2015-12-22 | 2016-03-23 | 无锡芯响电子科技有限公司 | Controllable-bandwidth reset circuit capable of achieving asynchronous reset and synchronous release |
| CN109539908A (en) * | 2018-10-24 | 2019-03-29 | 重庆长安工业(集团)有限责任公司 | Electronic security(ELSEC) sequential control circuit |
| CN111857306A (en) * | 2020-07-30 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | SoC system universal reset method and system, universal reset unit and SoC reset circuit |
| CN111857306B (en) * | 2020-07-30 | 2021-12-03 | 山东云海国创云计算装备产业创新中心有限公司 | SoC system universal reset method and system, universal reset unit and SoC reset circuit |
| CN112187233A (en) * | 2020-10-14 | 2021-01-05 | Oppo广东移动通信有限公司 | Reset device, method, clock system and electronic equipment |
| CN114327006A (en) * | 2021-12-22 | 2022-04-12 | 山东产研鲲云人工智能研究院有限公司 | Noc reset circuit, Noc chip, control method, control device and medium |
| CN114327006B (en) * | 2021-12-22 | 2024-03-15 | 山东产研鲲云人工智能研究院有限公司 | NoC reset circuit, noC chip, control method, device and medium |
| CN116521604A (en) * | 2023-07-05 | 2023-08-01 | 芯耀辉科技有限公司 | Method for synchronizing data and related device |
| CN116521604B (en) * | 2023-07-05 | 2024-03-19 | 芯耀辉科技有限公司 | Method for synchronizing data and related device |
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| CN100464281C (en) | 2009-02-25 |
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