CN106603442A - Cross-clock-domain high-speed data communication interface circuit of network on chip - Google Patents
Cross-clock-domain high-speed data communication interface circuit of network on chip Download PDFInfo
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- CN106603442A CN106603442A CN201611153386.5A CN201611153386A CN106603442A CN 106603442 A CN106603442 A CN 106603442A CN 201611153386 A CN201611153386 A CN 201611153386A CN 106603442 A CN106603442 A CN 106603442A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Abstract
A cross-clock-domain high-speed data communication interface circuit of a network on chip is mounted on a routing node of the network on chip. The circuit comprises the following three modules: an input multiplexer module, a data buffer storage module, and an output multiplexer module. The output end of the input multiplexer module is connected to the input end of the data buffer storage module, and the output end of the data buffer storage module is connected to the input end of the output multiplexer module. The data buffer storage module includes multiple annular asynchronous FIFOs based on a token ring. The input ends of the multiple annular asynchronous FIFOs based on a token ring are connected in parallel to the output end of the input multiplexer module, and the output ends of the multiple annular asynchronous FIFOs based on a token ring are connected in parallel to the input end of the output multiplexer module. In the circuit structure, the high-speed data stream passing through the data buffer storage module is continuously calculated and processed, so that seamless data stream buffer and transmission is realized.
Description
Technical field
The invention belongs to digital integrated electronic circuit field, and in particular to a kind of cross clock domain high-speed data communication of network-on-chip
Interface circuit.
Background technology
It is integrated on one chip with the complication of the fast-developing and FPGA system design of domestic microelectric technique
Hundreds of IP kernels are possibly realized.The appearance of network-on-chip (Network on chip, NOC) meets numerous IP kernel communications
Demand.However, traditional Design of Synchronization Technology adopts single voltage clocks domain, raising and the power consumption of NOC performances are limited
Reduce, the design bottleneck of network-on-chip has been increasingly becoming.In actual engineering, especially high-speed video is gathered and processing system
In, each functional module of internal system generally requires to be operated in the clock zone of different frequency, and cross clock domain process can not keep away
Exempt from.
In order to solve this problem, cross clock domain synchronous circuit mechanism and its method for designing become in recent years network-on-chip
Study hotspot.Conventional cross clock domain synchronous circuit has：Two-stage or multi-level register synchronization, level synchronization, shake hands it is synchronous, different
Step FIFO etc..Although these methods for designing are to a certain extent, cross clock domain is reduced well and transmits brought metastable state
Impact, but still cannot meet network-on-chip carries out real-time Transmission to Large Copacity, many bits and high speed stream of video data
Demand.
A design core difficult problem for current network-on-chip clock-domain crossing data communication interface, one is how to solve cross clock domain
Metastable issues caused by data transfer institute；Two is the transmission for how realizing network-on-chip cross clock domain high-speed data, avoids number
It is discontinuous with transmission data according to losing.The data transfer that cross clock domain is carried out between network-on-chip adjacent node easily causes Asia
Stable state, causes loss of data, affects the performance of network-on-chip high-speed video data processing system.MTBF(Mean time of
Failure, mean free error time) it is to weigh metastable efficiency index, the value of MTBF is bigger, then metastable issues occur
Probability is less.The computing formula of MTBF is：
MTBF=eTmet/C2/C1·fclk·fdata
The content of the invention
For the deficiencies in the prior art, the present invention proposes a kind of cross clock domain high-speed data communication interface electricity of network-on-chip
Road.The probability that metastable issues occur is preferably minimized, meanwhile, meet network-on-chip Large Copacity, many bits and regard at high speed
The requirement of the real-time Transmission of frequency data code flow.
The concrete technical scheme of the present invention is as follows：
A kind of clock-domain crossing data communication interface circuit of network-on-chip proposed by the present invention, is by input MUX
Module, data buffering memory module and output multi-channel selector module three parts composition.It is input into the defeated of MUX module
Go out the input that end is connected to data buffering memory module, the outfan of data buffering memory module is connected to output multi-channel selection
The input of device module.
Data buffering memory module, including multiple annular asynchronous FIFOs based on token ring, multiple rings based on token ring
The input of shape asynchronous FIFO is parallel-connected to the outfan of input MUX module, multiple based on the annular different of token ring
The outfan of step FIFO is parallel-connected to the input of output multi-channel selector module.
Based on the annular asynchronous FIFO of token ring, including token ring architecture, token ring architecture includes eight latch, eight
The connected mode of latch is connected to the input of the latch of next stage, afterbody for the outfan of the latch of upper level
The outfan of latch be connected to the input of first order latch.
Input data produced by the video acquisition IP kernel of network-on-chip is input to input MUX module, described
Input MUX module is sequentially output data buffering memory module in the case of enable signal is effective input data,
Described output multi-channel selector module enable signal it is effective in the case of by the data in data buffering memory module successively
Read, and output data is sent into into the Video processing IP kernel of network-on-chip.
Based on the token ring architecture in the annular asynchronous FIFO of token ring, the state of latch is defined as token when being 1, when
When enable signal is effective, the numerical value in upper level latch will be transferred in next stage latch, in afterbody latch
Numerical value will be transferred in first order latch, produced based on the annular asynchronous of token ring by the movement of token and adjustment
The read/write pointer of FIFO, read/write operation of the control based on the annular asynchronous FIFO of token ring.
Beneficial effects of the present invention are as follows：
The present invention proposes a kind of cross clock domain high-speed data communication interface circuit of network-on-chip.In circuit structure,
Using the design philosophy of the annular asynchronous FIFO based on token ring, by being input into MUX module and output multi-channel selector
The design of module, allows the annular asynchronous FIFO based on token ring by beat, the switching for cooperating, will be through data buffering
The high data rate bit stream of memory module continuously carries out computing and processes, and realizes seamless buffering and the transmission of data code flow.
A kind of cross clock domain high-speed data communication interface circuit of network-on-chip proposed by the invention, designs ingenious, knot
Structure is simple, reliable and can be greatly reduced metastable impact.Test result indicate that, the cross clock domain of the network-on-chip is at a high speed
Data communication interface circuit can realize the real-time biography of Large Copacity, many bits and high speed stream of video data on network-on-chip
It is defeated, it is ensured that the stability of network-on-chip high-speed video data processing system.
Description of the drawings
Fig. 1 is the cross clock domain high-speed data communication interface circuit design of the network-on-chip in the specific embodiment of the invention
Block diagram；
Fig. 2 is the token ring architecture figure in the specific embodiment of the invention；Wherein, it is specific embodiment party of the present invention to scheme (a)
The token ring architecture figure of the write pointer in formula, schemes the token ring architecture figure that (b) is the read pointer in the specific embodiment of the invention；
Fig. 3 is the input MUX module RTL structure chart in the specific embodiment of the invention；
Fig. 4 is the output multi-channel selector module RTL structure charts in the specific embodiment of the invention；
Fig. 5 is the cross clock domain high-speed data communication interface circuit in the specific embodiment of the invention in network-on-chip
Application drawing；
Fig. 6 is the cross clock domain high-speed data communication interface circuit top layer of the network-on-chip in the specific embodiment of the invention
RTL structure charts.
Specific embodiment
Below in conjunction with the accompanying drawings, with the network-on-chip that constituted using four parallel token ring annular fifo structures across clock
As a example by numeric field data communication interface circuit, a kind of embodiment to the present invention is described further.
A kind of cross clock domain high-speed data communication interface circuit of network-on-chip proposed by the present invention, is selected by input multichannel
Select device module, data buffering memory module and output multi-channel selector module three parts composition.Input MUX module
Outfan be connected to the input of data buffering memory module, the outfan of data buffering memory module is connected to output multi-channel
The input of selector module.The cross clock domain high-speed data communication interface circuit design block diagram of network-on-chip is as shown in Figure 1.
Data buffering memory module, including multiple annular asynchronous FIFOs based on token ring, multiple rings based on token ring
The input of shape asynchronous FIFO is parallel-connected to the outfan of input MUX module, multiple based on the annular different of token ring
The outfan of step FIFO is parallel-connected to the input of output multi-channel selector module.
Conventional asynchronous FIFO, comprising a two-port RAM, a port is used for the write of data, will data be stored in
To asynchronous FIFO, another port is used as the reading of data, will data read from asynchronous FIFO.Asynchronous FIFO utilization reading/
Write pointer is expired come the sky for judging asynchronous FIFO, and when read pointer catch up with write pointer, asynchronous FIFO is sky；Refer to when write pointer catch up with reading
During pin, asynchronous FIFO is full.
It is easier to occur asking when being transformed into another clock zone from a clock zone due to a binary count value
Topic, and when being counted using binary counter, all positions all may change simultaneously, in same clock along synchronous multiple
Signal is easier generating metastable problem.Therefore the present invention adopts token ring architecture, using token as asynchronous FIFO read/write
Pointer, the change of read/write pointer is produced by the running transform of token, and read/write pointer is synchronized to into asynchronous clock domain is carried out
Relatively, and using it as empty full state detection.
Based on the annular asynchronous FIFO of token ring, including token ring architecture, token ring architecture includes eight latch, eight
The connected mode of latch is connected to the input of the latch of next stage, afterbody for the outfan of the latch of upper level
The outfan of latch be connected to the input of first order latch, and specify token ring high level signal effectively, wherein wr
For write pointer, rr is read pointer, token ring architecture figure as shown in Fig. 2 wherein Fig. 2 (a) for write pointer token ring architecture figure, figure
The token ring architecture figure of (b) read pointer.The output of afterbody is connected with the input of the first order and constitutes an annular, wherein locking
The state of storage is defined as token when being 1, and when enabling signal and being effective, the numerical value in upper level latch will be transferred to next
In level latch, the numerical value in afterbody latch will be transferred in first order latch, the movement and tune by token
The whole read/write pointer to produce based on the annular asynchronous FIFO of token ring, control based on token ring annular asynchronous FIFO reading/
Write operation.Had based on the annular asynchronous FIFO of token ring and an only one of which read pointer rr and write pointer wr, they are with order
The form of board is transmitted clockwise in token ring, and when write operation is carried out based on the annular asynchronous FIFO of token ring, write pointer refers to
Data storage is carried out to the annular asynchronous FIFO data storage cell based on token ring, after having stored data, under write pointer is pointed to
Level one data memory element.In the same manner, when read operation is carried out based on the annular asynchronous FIFO of token ring, read pointer is pointed to based on order
The annular asynchronous FIFO data storage cell of board ring carries out data read-out, completes to read after data, and read pointer points to next DBMS
Memory element, read-write operation is circulated with this and carried out.
Read/write pointer based on the annular asynchronous FIFO of token ring is produced by the movement and adjustment of token, is simplified
Conventional asynchronous FIFO, it is to avoid use substantial amounts of lock unit, reduces area space, makes the property based on the annular FIFO of token
Can have and significantly increase, the requirement of big data quantity video data real-time Transmission can be met.
The input port of input MUX module includes clock signal port clk1, global reset signal port
Wrst_n and data input signal port data_in, output port includes that (i=1,2,3,4) write four fifoi_wen
(i=1,2,3,4) signal port, input MUX module RTL is tied for enable signal port and four data outputs wi_data
Composition is as shown in Figure 3.The specific works step of input MUX module is as follows：
When clock signal clk1 and effective global reset signal wrst_n, valid data pass through data_in ports by data
Write input MUX module.
The data characterized when fifo1_wen is effective in input MUX module are exported from w1_data；
The data characterized when fifo2_wen is effective in input MUX module are exported from w2_data；
The data characterized when fifo3_wen is effective in input MUX module are exported from w3_data；
The data characterized when fifo4_wen is effective in input MUX module are exported from w4_data.
The input port of output multi-channel selector module includes clock signal port clk2, global reset signal port
(i=1,2,3,4), output port includes four fifoi_ren (i to rrst_n and four data input signal port data_in2i
=1,2,3,4) read and enable signal port and a data output r_data signal port, output multi-channel selector module RTL
Structure chart is as shown in figure 4, specific works step is as follows.
When fifo1_ren is effective, output multi-channel selector module arrives the data output in input port data_in21
Output port r_data；
When fifo2_ren is effective, output multi-channel selector module arrives the data output in input port data_in22
Output port r_data；
When fifo3_ren is effective, output multi-channel selector module arrives the data output in input port data_in23
Output port r_data；
When fifo3_ren is effective, output multi-channel selector module arrives the data output in input port data_in24
Output port r_data.
The cross clock domain high-speed data communication interface circuit of the network-on-chip for designing is mounted on network-on-chip, is such as schemed
Shown in 5.Wherein (0,0), in the lower left corner of whole network-on-chip, (3,3) routing node is on the right side of whole network-on-chip for routing node
Upper angle, X-coordinate increases successively from left to right, and Y-coordinate increases successively from bottom to top.The routing node of network-on-chip can be with carry phase
The video acquisition IP kernel answered and Video processing IP kernel.Video acquisition IP kernel is mounted to (1,3) routing node, by Video processing IP
Core is mounted to (2,1) routing node.(1,3) clock of routing node is CLK1, and (2,1) clock of routing node is CLK2.Piece
Input data produced by the video acquisition IP kernel of upper network is input to input MUX module, is input into MUX mould
Block is sequentially output data buffering memory module, output multi-channel selector mould in the case of enable signal is effective input data
Block sequential reads out the data in data buffering memory module in the case of enable signal is effective, and output data is sent into into piece
The Video processing IP kernel of upper network.
Network-on-chip complete video acquisition, transmission, process specific works step it is as follows：
First, the valid data for collecting are transferred to video acquisition IP kernel the input port of input MUX, are led to
Which cross wflag flag bits to judge data buffer storage to the annular asynchronous FIFO based on token ring.
First be written efficiently into the clock cycle arrive when, video acquisition IP kernel by valid data by be input into MUX
Module is write first based on the annular asynchronous FIFO 1 of token ring；
Second be written efficiently into the clock cycle arrive when, video acquisition IP kernel by valid data by be input into MUX
Annular asynchronous FIFO 2 of the module write based on token ring；
3rd be written efficiently into the clock cycle arrive when, video acquisition IP kernel by valid data by be input into MUX
Annular asynchronous FIFO 3 of the module write based on token ring；
4th be written efficiently into the clock cycle arrive when, video acquisition IP kernel by valid data by be input into MUX
Annular asynchronous FIFO 4 of the module write based on token ring.
Secondly, judged by rflag flag bits, the output of output multi-channel selector module based on the annular asynchronous of token ring
Valid data in FIFO are read from which annular asynchronous FIFO based on token ring.
It is when first effective readout clock cycle arrives, the valid data of the annular asynchronous FIFO 4 based on token ring are defeated
Go out the output port to output multi-channel selector module；
It is when second effective readout clock cycle arrives, the valid data of the annular asynchronous FIFO 1 based on token ring are defeated
Go out the output port to output multi-channel selector module；
It is when 3rd effective readout clock cycle arrives, the valid data of the annular asynchronous FIFO 2 based on token ring are defeated
Go out the output port to output multi-channel selector module；
It is when 4th effective readout clock cycle arrives, the valid data of the annular asynchronous FIFO 3 based on token ring are defeated
Go out the output port to output multi-channel selector module.
Finally, by the output port of output multi-channel selector module and network-on-chip (1, the 3) local side of routing node
Valid data are transferred to network-on-chip by the connection of mouth, output multi-channel selector module, (1, the 3) significant figure in routing node
According to, by the routing algorithm of network-on-chip, be sent to (2,1) routing node, then Video processing IP is sent to by local port
Core.
Analyze by more than, using input MUX module, output multi-channel selector module and data buffering
Memory module, and being used cooperatively, reduces to the full extent the probability of metastable state generation, simplify network-on-chip across
The structure of clock zone high-speed data communication interface circuit.And it is electric to employ the cross clock domain high-speed data communication interface of network-on-chip
Road, network-on-chip can support the communication of multi-clock zone IP kernel, and the cross clock domain that can further reduce based on network-on-chip is high
The power consumption of fast data handling system.In addition, by input MUX module and output multi-channel selector module in the structure
The annular asynchronous FIFO based on token ring is allow by beat, the switching for cooperating, by through the stream of video data of buffering
Video processing IP kernel of the carry in network-on-chip is continuously sent to, seamless buffering and the transmission of data code flow is realized.If from piece
Data transmission procedure is seen at the two ends of the top-level module of the cross clock domain high-speed data communication interface circuit of upper network, input data and
Output data is all continuously to write and continuously read, no any pause, as shown in Figure 6.Therefore, the structure
Be very suitable for the pipeline of high-speed data-flow, meet high-speed video data code stream carry out on network-on-chip it is seamless
Buffering and real-time Transmission.
Claims (5)
1. a kind of cross clock domain high-speed data communication interface circuit of network-on-chip, is mounted on the routing node of network-on-chip,
Characterized in that, including three below module：Input MUX module, data buffering memory module and output multi-channel are selected
Device module；
The outfan of described input MUX module is connected to the input of data buffering memory module, and data buffering is deposited
The outfan of storage module is connected to the input of output multi-channel selector module.
2. a kind of cross clock domain high-speed data communication interface circuit of network-on-chip according to claim 1, its feature exists
In, described data buffering memory module, including multiple annular asynchronous FIFOs based on token ring, described is multiple based on token
The input of the annular asynchronous FIFO of ring is parallel-connected to the outfan of input MUX module, and described is multiple based on order
The outfan of the annular asynchronous FIFO of board ring is parallel-connected to the input of output multi-channel selector module.
3. a kind of cross clock domain high-speed data communication interface circuit of network-on-chip according to claim 1, its feature exists
In, the described annular asynchronous FIFO based on token ring, including token ring architecture, described token ring architecture is including eight latches
Device, the connected mode of eight described latch is connected to the defeated of the latch of next stage for the outfan of the latch of upper level
Enter end, the outfan of the latch of afterbody is connected to the input of first order latch.
4. the communication party of the cross clock domain high-speed data communication interface circuit of a kind of network-on-chip according to claim 1
Method, it is characterised in that the input data produced by the video acquisition IP kernel of described network-on-chip is input to input multi-path choice
Device module, described input MUX module is sequentially output data in the case of enable signal is effective input data
Buffered memory module, described output multi-channel selector module enable signal it is effective in the case of by data buffering memory module
In data sequential read out, and by output data send into network-on-chip Video processing IP kernel.
5. the communication party of the cross clock domain high-speed data communication interface circuit of a kind of network-on-chip according to claim 3
Method, it is characterised in that the token ring architecture in the described annular asynchronous FIFO based on token ring, when the state of latch is 1
Token is defined as, when enabling signal and being effective, the numerical value in upper level latch will be transferred in next stage latch, finally
Numerical value in one-level latch will be transferred in first order latch, be produced based on token by the movement and adjustment of token
The read/write pointer of the annular asynchronous FIFO of ring, read/write operation of the control based on the annular asynchronous FIFO of token ring.
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| CN106603442B CN106603442B (en) | 2019-06-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109217877A (en) * | 2017-06-29 | 2019-01-15 | 爱思开海力士有限公司 | Serializer and storage device including the serializer |
| CN110191069A (en) * | 2019-05-31 | 2019-08-30 | 西安理工大学 | A kind of annular network-on-chip with plurality of passages |
| CN110365530A (en) * | 2019-07-11 | 2019-10-22 | 电子科技大学 | A kind of test token passing network independently of network-on-chip |
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| CN1524215A (en) * | 2001-06-20 | 2004-08-25 | Ħ��������˾ | First-in, first-out memory system and method thereof |
| CN102063408A (en) * | 2010-12-13 | 2011-05-18 | 北京时代民芯科技有限公司 | Data bus in multi-kernel processor chip |
| CN102541506A (en) * | 2010-12-29 | 2012-07-04 | 深圳市恒扬科技有限公司 | First-in-first-out (FIFO) data register, chip and equipment |
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Patent Citations (3)
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| CN1524215A (en) * | 2001-06-20 | 2004-08-25 | Ħ��������˾ | First-in, first-out memory system and method thereof |
| CN102063408A (en) * | 2010-12-13 | 2011-05-18 | 北京时代民芯科技有限公司 | Data bus in multi-kernel processor chip |
| CN102541506A (en) * | 2010-12-29 | 2012-07-04 | 深圳市恒扬科技有限公司 | First-in-first-out (FIFO) data register, chip and equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109217877A (en) * | 2017-06-29 | 2019-01-15 | 爱思开海力士有限公司 | Serializer and storage device including the serializer |
| CN109217877B (en) * | 2017-06-29 | 2022-05-31 | 爱思开海力士有限公司 | Serializer and memory device including the same |
| CN110191069A (en) * | 2019-05-31 | 2019-08-30 | 西安理工大学 | A kind of annular network-on-chip with plurality of passages |
| CN110191069B (en) * | 2019-05-31 | 2021-04-06 | 西安理工大学 | Annular network on chip with multiple channels |
| CN110365530A (en) * | 2019-07-11 | 2019-10-22 | 电子科技大学 | A kind of test token passing network independently of network-on-chip |
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