CN110191069B - Annular network on chip with multiple channels - Google Patents
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- CN110191069B CN110191069B CN201910471952.4A CN201910471952A CN110191069B CN 110191069 B CN110191069 B CN 110191069B CN 201910471952 A CN201910471952 A CN 201910471952A CN 110191069 B CN110191069 B CN 110191069B
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- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H04L49/252—Store and forward routing
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The invention discloses an annular network-on-chip with a plurality of channels, which is formed by sequentially connecting a plurality of nodes, wherein each two adjacent nodes are connected through the plurality of channels for data transmission, the number of the channels between each two adjacent nodes is the same, the plurality of channels transmit data independently, the plurality of nodes are divided from a starting node to obtain a plurality of groups of nodes, the number of each group of nodes is equal to the number of the channels between each two adjacent nodes, each node in each group of nodes uniquely designates one channel in the plurality of channels as a data output channel of the node, and a path for data transmission between any two nodes in the annular network-on-chip is the data output channel of an upstream node between the two nodes. A ring network-on-chip with multiple channels can reduce the problems of blocking and time delay of ring network data transmission.
Description
Technical Field
The invention belongs to the technical field of network-on-chips, and particularly relates to a ring-shaped network-on-chip with a plurality of channels.
Background
With the development of multi-core processors, networks on chip as an interaction channel between cores have become an increasingly important research field. With the application of the multi-core processor in high-end servers, smart phones and even the field of internet of things becoming more and more extensive, the requirement on the network on chip becomes higher and higher. The factors for measuring the network-on-chip quality include power consumption, area, expandability, bandwidth, throughput rate, delay and the like. The performance requirements for networks on chip are also different for different application areas. Compared with networks on chip with other structures, the ring network has the characteristics of simple structure and easy realization, is a good choice under the condition of less core number, but has the disadvantages of time delay increase and throughput rate reduction of the common ring network on chip when the number of nodes is more, and can greatly influence the performance of the ring network.
Disclosure of Invention
The invention aims to provide a ring network-on-chip with a plurality of channels, which can reduce the problems of blocking and time delay of ring network data transmission.
The first technical scheme adopted by the invention is as follows: the utility model provides a ring shape network on chip with many passageways, connect gradually by a plurality of node and form ring shape network on chip, carry out data transfer through many passageway connections between every two adjacent nodes, and the passageway number between every two adjacent nodes is the same, the independent data transfer each other between many passageways, a plurality of node divides from the initial node and obtains multiunit node, the number of every group node equals with the passageway number between every two adjacent nodes, every node in every group node appoints a passageway in many passageways uniquely to be the data output channel of this node, the route that carries out data transfer between arbitrary two nodes in the ring shape network on chip is the data output channel of the upper reaches node between these two nodes.
The present invention is also characterized in that,
the nodes comprise ip cores, the ip cores are connected with network adapters in a bidirectional mode, the network adapters are connected with routers in a bidirectional mode, and the routers are connected with upstream nodes and downstream nodes to conduct information transmission.
The router comprises a data packet scheduling unit, wherein the input end of the data packet scheduling unit is connected with an upstream node to receive data sent by the upstream node, one output end of the data packet scheduling unit is connected with the input end of a network adapter to send a data packet of a current node in a target node to an ip core through the network adapter for processing, the other output end of the data packet scheduling unit is connected with one input end of a data packet transmitting unit, the other input end of the data packet transmitting unit is connected with the output end of the network adapter to receive data sent by the ip core, the output end of the data packet transmitting unit is connected with the upstream node to feed back information of the current node to the upstream node, and the data packet scheduling unit is also bidirectionally connected with the downstream node to send data to the downstream node and receive information fed back by the downstream node.
The data packet transmitting unit comprises an input buffer, the input end of the input buffer is connected with the output end of the data packet scheduling unit to receive the data packet transmitted by the upstream node, one output end of the input buffer is connected with the upstream node to feed back self-stored information to the upstream node, the other output end of the input buffer is connected with the first input end of the transmitting control unit to transmit the empty state information of the current input buffer and the stored data packet, the second input end of the transmitting control unit is connected with the downstream node to receive the information fed back by the downstream node, the first output end of the transmitting control unit is connected with the input buffer to transmit a signal to select the data packet to be stored in the input buffer, the second output end of the transmitting control unit is connected with the downstream node to transmit the data packet to the downstream node,
the output end of the data packet scheduling unit is also directly connected with the third input end of the transmission control unit, so that when the input buffer is stored as empty, the data packet sent by the upstream node is directly sent to the downstream node through the transmission control unit, and the data packet transmission delay is reduced.
The data packet transmitting unit further comprises a local buffer, one input end of the local buffer is connected with the output end of the network adapter and used for receiving the data packet sent by the ip core, the other input end of the local buffer is connected with the third output end of the transmitting control unit and used for selecting to store the data sent by the network adapter into the local buffer, and the output end of the local buffer is connected with the fourth input end of the transmitting control unit and used for sending the empty and full state information of the local buffer and the cached data packet.
The input buffer comprises a register I, the input end of the register I is connected with the output end of the data packet scheduling unit through a selector I and used for storing data sent by the data packet scheduling unit when a downstream node can not receive the data and the state of the register II is full, the output end of the register I is connected with the input end of the register II through the selector II, the output end of the register II is connected with the emission control unit,
the input end of the register II is also connected with the output end of the data packet scheduling unit through the selector II and is used for storing data sent by the data packet scheduling unit when a downstream node cannot receive the data,
the output end of the register I is also connected with the selector I for keeping the stored data packet unchanged when the data of the data packet scheduling unit is not required to be stored, the output end of the register I is also connected with the transmission control unit for sending the stored data packet and the empty and full state information of the register I to the transmission control unit for generating a selection signal of the selector I,
the output end of the register is also connected with a selector II for keeping the data of the register I and the data packet scheduling unit unchanged when the data is not required to be received,
the selector I and the selector II are also connected with the output end of the transmission control unit, and the transmission control unit respectively sends selection signals to the selector I and the selector II to select whether to continuously maintain the data packet in the register or receive the data packet sent by the data packet scheduling unit.
The invention has the beneficial effects that: according to the annular network on chip with the multiple channels, the multiple groups of nodes are obtained by dividing the multiple nodes, the output channel is assigned to each node, and the path for data transmission between any two nodes is the data output channel of the upstream node between the two nodes, so that when data is transmitted, the data can be transmitted without only one channel or only one channel with blockage, the network blockage and the transmission delay can be effectively relieved, and the throughput rate of the network is improved; meanwhile, the accuracy of data transmission is ensured because the multiple channels are independently transmitted; the data packet scheduling unit is directly connected with the transmission control unit, so that the data packet sent by the upstream node can be directly sent to the downstream node through the transmission control unit without passing through the input buffer when the input buffer is stored as empty, the data packet can continuously jump to a plurality of nodes in a single period from one node to reach a target node, and the transmission delay of the data packet is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a ring network-on-chip with multiple channels according to the present invention;
FIG. 2 is a schematic structural diagram of a node in a ring network on chip with multiple channels according to the present invention;
FIG. 3 is a schematic diagram of a router structure in a ring network on chip with multiple channels according to the present invention;
FIG. 4 is a schematic diagram of an input buffer in a ring network on chip with multiple channels according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention relates to a ring network-on-chip structure with a plurality of channels, as shown in figure 1, n nodes are connected in sequence to form a ring network-on-chip, every two adjacent nodes are connected through 4 channels for data transmission, the number of the channels between every two adjacent nodes is 4, and the channels are respectively marked as follows: 1. 2, 3, 4, data are transmitted independently among a plurality of channels, n nodes are divided from a starting node to obtain a plurality of groups of nodes, the number of each group of nodes is equal to the number of the channels between every two adjacent nodes and is also 4, each node in each group of nodes uniquely designates one channel of the plurality of channels as a data output channel of the node, the output channel of the node marked as 1 is channel 1, the output channel of the node marked as 2 is channel 2, the output channel of the node marked as 3 is channel 3, the output channel of the node marked as 4 is channel 4, and a path for data transmission between any two nodes in the ring network-on-chip is the data output channel of an upstream node between the two nodes.
As shown in fig. 2, the node includes an ip core, the ip core is bidirectionally connected with a network adapter, the network adapter is bidirectionally connected with a router, and the router is connected with an upstream node and a downstream node for information transmission.
As shown in fig. 3, the router includes a packet scheduling unit, an input end of the packet scheduling unit is connected to the upstream node to receive data sent by the upstream node, an output end of the packet scheduling unit is connected to an input end of the network adapter to send a packet, which is a current node in a destination node, to the ip core through the network adapter for processing, another output end of the packet scheduling unit is connected to one input end of a packet transmitting unit, another input end of the packet transmitting unit is connected to an output end of the network adapter to receive data sent by the ip core, an output end of the packet transmitting unit is connected to the upstream node to feed back information of the current node to the upstream node, and the packet scheduling unit is also bidirectionally connected to the downstream node to send data to the downstream node and receive information fed back by the downstream node.
The data packet transmitting unit comprises an input buffer, the input end of the input buffer is connected with the output end of the data packet scheduling unit to receive the data packet transmitted by the upstream node, one output end of the input buffer is connected with the upstream node to feed back self-stored information to the upstream node, the other output end of the input buffer is connected with the first input end of the transmitting control unit to transmit the empty state information of the current input buffer and the stored data packet, the second input end of the transmitting control unit is connected with the downstream node to receive the information fed back by the downstream node, the first output end of the transmitting control unit is connected with the input buffer to transmit a signal to select the data packet to be stored in the input buffer, the second output end of the transmitting control unit is connected with the downstream node to transmit the data packet to the downstream node,
the output end of the data packet scheduling unit is also directly connected with the third input end of the transmission control unit, so that when the input buffer is stored as empty, the data packet sent by the upstream node is directly sent to the downstream node through the transmission control unit, and the data packet transmission delay is reduced.
As shown in fig. 4, the packet transmitting unit further includes a local buffer, one input end of the local buffer is connected to the output end of the network adapter for receiving the packet sent by the ip core, another input end of the local buffer is connected to the third output end of the transmission control unit for selecting to store the data sent by the network adapter into the local buffer, and an output end of the local buffer is connected to the fourth input end of the transmission control unit for sending the empty/full status information of the local buffer and the buffered packet.
The input buffer comprises a register I, the input end of the register I is connected with the output end of the data packet scheduling unit through a selector I and used for storing data sent by the data packet scheduling unit when a downstream node can not receive the data and the state of the register II is full, the output end of the register I is connected with the input end of the register II through the selector II, the output end of the register II is connected with the emission control unit,
the input end of the register II is also connected with the output end of the data packet scheduling unit through the selector II and is used for storing data sent by the data packet scheduling unit when a downstream node cannot receive the data,
the output end of the register I is also connected with the selector I for keeping the stored data packet unchanged when the data of the data packet scheduling unit is not required to be stored, the output end of the register I is also connected with the transmission control unit for sending the stored data packet and the empty and full state information of the register I to the transmission control unit for generating a selection signal of the selector I,
the output end of the register is also connected with a selector II for keeping the data of the register I and the data packet scheduling unit unchanged when the data of the register I and the data packet scheduling unit are not required to be received.
The selector I and the selector II are also connected with the output end of the transmission control unit, and the transmission control unit respectively sends selection signals to the selector I and the selector II to select whether to continuously maintain the data packet in the register or receive the data packet sent by the data packet scheduling unit.
Description of the system principle of the invention: when the current node transmits information to a downstream node, the ip core is used for sending data to the network adapter, the network adapter packages the data and transmits the data packet to the router, the router transmits the data packet to the downstream node, when the current node receives the information transmitted by the upstream node, the router is used for receiving the data packet transmitted by the upstream node and selecting whether the data packet is stored locally or not according to the destination address information of the data packet, if the destination address information in the data packet is matched with the address information of the local node, the data packet is unpacked through the network adapter and then transmitted into the ip core for processing, and if the destination address information in the data packet is not matched with the address information of the local node, the router directly transmits the received data packet to the downstream node.
In the router structure of the invention, after receiving a data packet sent from an upstream node, a current node firstly transmits the data packet to a data packet scheduling unit, judges whether the current node is a destination node of the data packet according to destination node address information contained in the data packet, if so, stores the data packet in the local, otherwise, transmits the data packet to a data packet transmitting unit. The data packet of the data packet transmitting unit comes from two directions: one from the packet scheduling unit and the other from the packets sent by the local IP core through the network adapter. The other input of the packet transmitting unit is an iFull signal sent from the downstream node, and the signal indicates whether the downstream node has free storage space to receive the packet. Meanwhile, an input buffer in the data packet transmitting unit outputs an oFull signal to an upstream node to represent whether a spare storage space exists in the current node. After entering the data packet transmitting unit, the data packet is transmitted in two directions, one direction is directly bypassed to the transmission control unit, the bypass means that the output end of the data packet scheduling unit is also directly connected with the third input end of the transmission control unit, and the other direction is entered into the input buffer and then transmitted to the transmission control unit. Data packets sent from the local ip core through the network adapter are stored in the local buffer and then sent to the transmission control unit. After receiving the data packets in the three directions, the transmission control unit selects a data packet according to the empty states of the input buffer and the local buffer, and whether the data packet is output is determined by the iFull signal sent by the downstream node. The empty-full state of the input buffer sends InData signals to the emission control unit through the input buffer, the InData signals including InData1 and InData2 signals, and one-bit valid signals in the two signals represent the empty-full state of the current input buffer. In order to reduce the delay of data packet transmission in network, a bypass structure is added in the register, so that the data can be directly sent to the next node without buffering in the input buffer.
The input buffer structure of the invention comprises two registers which are connected in series, wherein the two registers have three states, one state is that the two registers are in an empty state, and if data input from an upstream node exists and cannot be transmitted to a downstream node, the data are preferentially stored in a register II, and the register I is empty. In the second state, register I is empty and register II is full, and if the data in register II is not sent when the upstream node arrives, the data from the upstream node is stored in register 1. In the third state, both registers are in a full state, and the oFull signal fed back to the upstream node is 1, so that the upstream node cannot send data. When iFull is 0, the representation downstream node can receive the data packet, at this time, the data of the register II is output preferentially, and meanwhile, the data of the register I is sent to the register II. At this point, oFull becomes 0, indicating that the upstream node's data can be received, and at this point, becomes the second state. Therefore, the states of the full register 1 and the empty register II can not occur, so that whether the nth node can send data or not only can the state of the register II of the (n-1) th node be judged. The selector I is used for selecting whether to store the data transmitted by the upstream node in the register 1, and the selector II is used for selecting the data transmitted from the register 1 and the data transmitted by the upstream node. Register i outputs an InData1 signal to the emission control unit, and an InData1 signal contains a packet to be transmitted and a 1-bit valid signal indicating whether this packet is valid. The characteristics of the InData2 signal are the same as those of the InData1 signal, and the emission control unit selects one data packet to output according to the values of the two bit signals after receiving the two signals. For example, in the case that both registers are full, the transmission control unit preferentially transmits the data of register ii, and at this time, the data packet in the InData2 is still in register ii, but the valid bit becomes invalid, and the transmission control unit changes the value of InSel2 after detecting that the valid bit in the InData2 becomes invalid, and stores the value of register 1 in register ii through selector ii.
InSel1 is a one-bit selection signal, when the value is 0, the data in register i is kept unchanged, and when the value is 1, the data in the packet scheduling unit is stored in register i; InSel2 is a two-bit selection signal, and when the value is 01, the data in register ii remains unchanged, when the value is 10, register 2 receives the data sent from register i, and when the value is 11, register ii receives the data in the packet scheduling unit. LoSel1 is a one-bit selection signal, when the value is 0, the data in register I is kept unchanged, and when the value is 1, the data of the network adapter is stored in register I; LoSel2 is a two-bit select signal, and when the value is 01, the data in register ii remains unchanged, when the value is 10, register ii receives the data sent from register i, and when the value is 11, register ii receives the data in the network adapter.
Claims (3)
1. A ring network-on-chip with multiple channels is characterized in that a plurality of nodes are sequentially connected to form a ring network-on-chip, every two adjacent nodes are connected through the multiple channels to carry out data transmission, the number of the channels between every two adjacent nodes is the same, the multiple channels independently transmit data, the multiple nodes are divided from a starting node to obtain multiple groups of nodes, the number of each group of nodes is equal to the number of the channels between every two adjacent nodes, each node in each group of nodes uniquely designates one channel in the multiple channels as a data output channel of the node, and a path for carrying out data transmission between any two nodes in the ring network-on-chip is a data output channel of an upstream node between the two nodes;
the nodes comprise ip cores, the ip cores are connected with network adapters in a bidirectional mode, the network adapters are connected with routers in a bidirectional mode, and the routers are connected with upstream nodes and downstream nodes to conduct information transmission;
the router comprises a data packet scheduling unit, the input end of the data packet scheduling unit is connected with the upstream node to receive the data sent by the upstream node, one output end of the data packet scheduling unit is connected with the input end of the network adapter and is used for sending the data packet which is the current node in the destination node to the ip core through the network adapter for processing, the other output end of the data packet scheduling unit is connected with one input end of the data packet transmitting unit, the other input end of the data packet transmitting unit is connected with the output end of the network adapter to receive the data sent by the ip core, the output end of the data packet transmitting unit is connected with the upstream node to feed back the current node information to the upstream node, the data packet scheduling unit is also connected with the downstream node in a bidirectional way and used for sending data to the downstream node and receiving information fed back by the downstream node;
the data packet transmitting unit comprises an input buffer, the input end of the input buffer is connected with the output end of the data packet scheduling unit to receive the data packet transmitted by the upstream node, an output terminal of the input buffer is connected to the upstream node to feed back the self-stored information to the upstream node, the other output terminal of the input buffer is connected to the first input terminal of the transmission control unit to transmit the empty state information of the current input buffer and the stored packet, the second input end of the transmitting control unit is connected with the downstream node to receive the information fed back by the downstream node, a first output of said transmission control unit is connected to said input buffer for sending a signal for selecting a data packet to be stored in the input buffer, a second output of the transmission control unit is connected to a downstream node for transmitting data packets to the downstream node,
the output end of the data packet scheduling unit is also directly connected with the third input end of the transmission control unit, and the data packet scheduling unit is used for directly sending the data packet sent by the upstream node to the downstream node through the transmission control unit when the input buffer is stored as empty so as to reduce the data packet transmission delay.
2. The ring network-on-chip with multiple lanes as claimed in claim 1, wherein the packet transmitter further includes a local buffer, one input of the local buffer is connected to the output of the network adaptor for receiving the packet sent by the ip core, another input of the local buffer is connected to the third output of the transmit controller for selecting to store the data sent by the network adaptor into the local buffer, and an output of the local buffer is connected to the fourth input of the transmit controller for sending the empty/full status information of the local buffer and the buffered packet.
3. The ring type network on chip with multiple channels as claimed in claim 1, wherein said input buffer includes a register I, an input terminal of said register I is connected to an output terminal of said packet scheduling unit through a selector I for storing data transmitted from the packet scheduling unit when a downstream node cannot receive data and a register II is full, an output terminal of said register I is connected to an input terminal of a register II through a selector II, an output terminal of said register II is connected to said transmission control unit,
the input end of the register II is also connected with the output end of the data packet scheduling unit through a selector II and is used for storing data sent by the data packet scheduling unit when a downstream node cannot receive the data,
the output end of the register I is also connected with the selector I and used for keeping the stored data packet unchanged when the data of the data packet scheduling unit is not required to be stored, the output end of the register I is also connected with the transmission control unit and used for sending the stored data packet and the empty and full state information of the register I to the transmission control unit to generate a selection signal of the selector I,
the output end of the register is also connected with a selector II for keeping the data of the register I and the data packet scheduling unit unchanged when the data of the register I and the data packet scheduling unit are not required to be received,
the selector I and the selector II are also connected with the output end of the transmission control unit, and the transmission control unit respectively sends selection signals to the selector I and the selector II to select whether to continuously maintain the data packet in the register or receive the data packet sent by the data packet scheduling unit.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497411A (en) * | 2011-12-08 | 2012-06-13 | 南京大学 | Intensive operation-oriented hierarchical heterogeneous multi-core on-chip network architecture |
| CN104796343A (en) * | 2015-03-21 | 2015-07-22 | 西安电子科技大学 | Communication structure based on network-on-chip |
| CN106453109A (en) * | 2016-10-28 | 2017-02-22 | 南通大学 | Network-on-chip communication method and network-on-chip router |
| CN106603442A (en) * | 2016-12-14 | 2017-04-26 | 东北大学 | Cross-clock-domain high-speed data communication interface circuit of network on chip |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100561924C (en) * | 2007-10-10 | 2009-11-18 | 山东大学 | Network-on-chip digital router and parallel data transmission method thereof |
| CN101789892B (en) * | 2010-03-11 | 2012-05-09 | 浙江大学 | All-node virtual-channel network-on-chip ring topology data exchange method and system |
| US20190089619A1 (en) * | 2017-09-21 | 2019-03-21 | Qualcomm Incorporated | Self-test engine for network on chip |
-
2019
- 2019-05-31 CN CN201910471952.4A patent/CN110191069B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497411A (en) * | 2011-12-08 | 2012-06-13 | 南京大学 | Intensive operation-oriented hierarchical heterogeneous multi-core on-chip network architecture |
| CN104796343A (en) * | 2015-03-21 | 2015-07-22 | 西安电子科技大学 | Communication structure based on network-on-chip |
| CN106453109A (en) * | 2016-10-28 | 2017-02-22 | 南通大学 | Network-on-chip communication method and network-on-chip router |
| CN106603442A (en) * | 2016-12-14 | 2017-04-26 | 东北大学 | Cross-clock-domain high-speed data communication interface circuit of network on chip |
Non-Patent Citations (3)
| Title |
|---|
| X_DSP多通道多链路双向环形片上网络及网络接口的设计;化迎召;《CNKI硕士学位论文》;20160331;第二、三章 * |
| 多链路层无阻塞环形片上网络研究;李晨;《CNKI硕士学位论文》;20170331;全文 * |
| 无数据缓存的容错环形NoC;张丽果等;《计算机科学》;20090331;全文 * |
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