CN1921309A - Synchronizing signal detecting device - Google Patents
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- CN1921309A CN1921309A CN 200610122115 CN200610122115A CN1921309A CN 1921309 A CN1921309 A CN 1921309A CN 200610122115 CN200610122115 CN 200610122115 CN 200610122115 A CN200610122115 A CN 200610122115A CN 1921309 A CN1921309 A CN 1921309A
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Abstract
The invention relates to a synchronous signal detector, which comprises: edge detector for detecting the edge of input synchronous signal; clock generator for generating internal clock signal; impulse signal detector for generating set signal when receiving the impulse signal output by the edge detector and generating reset signal when receiving the voltage signal output by the edge detector; an output selector for selectively output the impulse signal or the internal clock signal based on the output signal of impulse signal detector. The invention has wide frequency width of detectable external synchronous signal and low demand on the internal clock signal.
Description
Technical field
The present invention relates to a kind of synchronization signal detection technology, relate in particular to a kind of sync signal detection apparatus.
Background technology
Sync signal detection apparatus can be with synchronizing signal as output when input sync signal; The clock signal that can produce with internal clock generator when (fixing high level or low level signal) at input fixed level signal is as output.
Existing a kind of sync signal detection apparatus as depicted in figs. 1 and 2, Fig. 1 is the synchronization signal detection module of prior art sync signal detection apparatus, Fig. 2 is the gating module of prior art sync signal detection apparatus.Whole device comprises signal input part 21, signal output part 26, delayer and XOR gate, trigger 1, trigger 2, clock generator 24, counter 25, phase inverter, NAND gate 1, NAND gate 2 and NAND gate 3, wherein, trigger 1 and trigger 2 are d type flip flop, and the D1 end 22 of trigger 1 is input high level " 1 " all the time.
The synchronization signal detection detailed process that this device carries out is:
What receive when external input signal end 21 is level signal (fixing high level or low level signal), and when not having the synchronizing signal input, the input of delayer is consistent with output end signal, two input end signal unanimities of XOR gate, XOR gate output low level.The clock signal of trigger 1 and trigger 2 is outputs of XOR gate, because the low level of XOR gate output, so trigger 1 and trigger 2 will keep current output state.At this moment, the clock signal that clock generator 24 produces is sent in the counter 25, and counter 25 is at a plurality of clock cycle Q3 end of counting output high level, and the in-phase output end of trigger 1 and trigger 2 is reset to low level simultaneously.Then the input 23 of phase inverter is a low level, and phase inverter output high level is to an input of NAND gate 1.Make the output of NAND gate 1 can output clock generator 24 clock signals that produce.Simultaneously, an input of NAND gate 2 is identical with phase inverter input 23, and this input also is a low level, and this moment, no matter what signal another input of NAND gate 2 imports NAND gate 2 was all exported the input of high level to NAND gate 3.The output state of NAND gate 3 is just determined by the output state of NAND gate 1.At this moment, the clock signal that produces of internal clock generator 24 exports the output 26 of entire circuit after through twice gating to.
When external input signal end 21 receive be synchronizing signal the time, when the upset edge of synchronizing signal (turn to low level or turn to high level from low level from high level) arrives, because it is inconsistent that the effect of delayer causes at two the input end signal level of moment XOR gate that overturn, be the pulse signal of the delay of delayer generation in pulse duration of synchronizing signal upset XOR gate output constantly.This pulse signal is counter O reset, and the Q1 end output high level that makes trigger 1 is to trigger 2.When second upset edge of synchronizing signal arrives, XOR gate will be exported a pulse signal again with counter O reset, simultaneously the Q2 of trigger 2 end output high level.At this moment, the input 23 of phase inverter is a high level, and the output that an input of NAND gate 1 is a phase inverter then is low level, makes that no matter what signal NAND gate 1 another input imports NAND gate 1 is all exported high level to NAND gate 3.Then the output of NAND gate 3 can be followed the output variation of NAND gate 2.An input of NAND gate 2 is all high level mutually with the input 23 of phase inverter, makes the output of NAND gate 2 can follow another input 21 variations.That is NAND gate 2 can export synchronizing signal, and at this moment, the synchronizing signal that outside input sync signal end 21 receives exports the output 26 of entire circuit after through twice gating to.
The chip area that this sync signal detection apparatus adopts the mode of Digital Logic to take is little, can input low level or high level or synchronizing signal at a pin, can realize the multi-functional effect of a pin, but there is following shortcoming in the prior art:
At first, the annexation of clock generator, counter and XOR gate causes the frequency of the internal clock signal that clock generator produces to be at least the twice of the synchronous signal frequency of outside input, has limited the frequency range of the synchronizing signal to be detected of input;
Secondly, the input D that this sync signal detection apparatus defines trigger 1 is a high level, makes circuit lack flexibility and expansion.
Summary of the invention
Technical problem to be solved by this invention is, a kind of sync signal detection apparatus is provided, and can enlarge the frequency range of synchronizing signal to be detected.
In order to solve the problems of the technologies described above, the present invention proposes following technical scheme, and a kind of sync signal detection apparatus of this scheme comprises:
Edge detecting unit is used to detect institute's edge of input synchronous signal, when detecting the synchronizing signal edge, produces pulse signal, otherwise, produce level signal;
Clock generator is used to produce internal clock signal;
The pulse signal detecting unit links to each other with described clock generator with described edge detecting unit respectively; When receiving the pulse signal of described edge detecting unit output, under described pulse signal control, produce asserts signal, when receiving the level signal of described edge detecting unit output, under the driving of the internal clock signal that described clock generator is exported, produce reset signal;
Output select unit is used for exporting described pulse signal when receiving the asserts signal of described pulse signal detecting unit output, when receiving the reset signal of described pulse signal detecting unit output, exports described internal clock signal.
Wherein, described pulse signal detecting unit comprises:
The asserts signal generation unit is used for when receiving the pulse signal of described edge detecting unit generation, under described pulse signal control, produces also output asserts signal;
The reset signal generation unit, be used for when receiving the level signal of described edge detecting unit output, under the driving of the internal clock signal that described clock generator is exported, make arbitrary initial output state become stable output reset signal state, and export described reset signal.
Further, described asserts signal generation unit is first trigger, the asynchronous set end of described first trigger links to each other with the output of described edge detecting unit, receive the pulse signal of described edge detecting unit output, in-phase output end links to each other with the input of described output select unit, and the output asserts signal is to the input of described output select unit.
Accordingly, described reset signal generation unit comprises the logical AND not gate, second trigger and the 3rd trigger; An input of described logical AND not gate links to each other with the described second trigger in-phase output end, and another input links to each other with described the 3rd trigger in-phase output end, and the output of logical AND not gate links to each other with the signal input part of described second trigger; The asynchronous set end of described second trigger links to each other with the output of described edge detecting unit with the asynchronous set end of described the 3rd trigger, receive the level signal of described edge detecting unit output, the input end of clock of described second trigger links to each other with the output of described clock generator, and the input end of clock of described the 3rd trigger links to each other with the in-phase output end of described second trigger; The signal input part of described the 3rd trigger links to each other with the inverse output terminal of described the 3rd trigger, and the in-phase output end of described the 3rd trigger links to each other with the input of described output select unit, and the output reset signal is to the input of described output select unit.
Perhaps, described reset signal generation unit comprises logic sum gate, second trigger and the 3rd trigger; An input of described logic sum gate links to each other with the described second trigger reversed-phase output, and another input links to each other with described the 3rd trigger reversed-phase output, and the output of logic sum gate links to each other with the signal input part of described second trigger; The asynchronous set end of described second trigger links to each other with the output of described edge detecting unit with the asynchronous set end of described the 3rd trigger, receive the level signal of described edge detecting unit output, the input end of clock of described second trigger links to each other with the output of described clock generator, and the input end of clock of described the 3rd trigger links to each other with the in-phase output end of described second trigger; The signal input part of described the 3rd trigger links to each other with the inverse output terminal of described the 3rd trigger, and the in-phase output end of described the 3rd trigger links to each other with the input of described output select unit, and the output reset signal is to the input of described output select unit.
Wherein, described first trigger and described the 3rd trigger are same trigger.
Wherein, described same trigger is the trigger with latch function.
Wherein, described edge detecting unit is rising edge testing circuit or trailing edge testing circuit or bilateral along testing circuit.
The present invention compared with prior art has following beneficial effect:
At first, not directly effect of the synchronizing signal of outside input and internal clock signal in the sync signal detection apparatus of the present invention, can not influence each other, so sync signal detection apparatus of the present invention is low to the internal clock signal requirement, the frequency range of detectable outer synchronous signal is big;
Secondly, each functional module of sync signal detection apparatus of the present invention does not all have the initial condition restriction, makes that the device flexibility is big, expansion is strong.
Description of drawings
Fig. 1 and Fig. 2 are that the prior art sync signal detection apparatus is formed structure chart;
Fig. 3 is the composition schematic diagram of sync signal detection apparatus of the present invention;
Fig. 4 is the composition structure chart of first embodiment of sync signal detection apparatus of the present invention;
Fig. 5 is that the pulse signal of first embodiment shown in Figure 4 produces schematic diagram;
Fig. 6 be embodiment illustrated in fig. 5 trigger 1 and trigger 2 in-phase output ends initially all during output low level reset signal produce schematic diagram;
Fig. 7 be embodiment illustrated in fig. 5 trigger 1 and trigger 2 in-phase output ends initially respectively when output low level and high level reset signal produce schematic diagram;
Fig. 8 be embodiment illustrated in fig. 5 when trigger 1 and trigger 2 in-phase output ends are initially exported high level and low level respectively reset signal produce schematic diagram;
Fig. 9 be embodiment illustrated in fig. 5 when trigger 1 and trigger 2 in-phase output ends are initially all exported high level reset signal produce schematic diagram;
Figure 10 is the composition structure chart of second embodiment of sync signal detection apparatus of the present invention;
Figure 11 is that the pulse signal of second embodiment shown in Figure 10 produces schematic diagram;
Figure 12 is the composition structure chart of the 3rd embodiment of sync signal detection apparatus of the present invention;
Figure 13 is that the pulse signal of the 3rd embodiment shown in Figure 12 produces schematic diagram;
Embodiment
For making purpose of the present invention, technical scheme and effect express clear more completely, the present invention is further described in detail again below in conjunction with drawings and Examples.
Fig. 3 is the composition schematic diagram of sync signal detection apparatus of the present invention, and this device mainly comprises edge detecting unit 11, clock generator 12, asserts signal generation unit 131, reset signal generation unit 132 and output select unit 14.Particularly:
Asserts signal generation unit 131 is used for producing asserts signal when receiving the pulse signal of described edge detecting unit 11 generations.
Reset signal generation unit 132, be used for when receiving the level signal of described edge detecting unit 11 outputs, under the driving of the internal clock signal of described clock generator 12 outputs that receive, with this unit arbitrarily init state be transferred to stable output reset signal state.
Output select unit 14, link to each other with described edge detecting unit 11, asserts signal generation unit 131, reset signal generation unit 132 and described clock generator 12 respectively, be used for when receiving the asserts signal of described asserts signal generation unit 131 outputs, export described pulse signal, when receiving the reset signal of described reset signal generation unit 132 outputs, export described internal clock signal.Output select unit 14 adopts the combination pulse signals and the output of internal clock signal gating of at least a gate.Output select unit 14 also can adopt being combined in of at least a gate to force described internal clock signal and described pulse signal synchronous when receiving pulse signal, then, exports described internal clock signal after synchronously.
Above-mentioned is the basic logic composition of sync signal detection apparatus of the present invention, below in conjunction with embodiment the present invention is specifically described.
With reference to figure 4, be the composition structure chart of first embodiment of sync signal detection apparatus of the present invention.Edge detecting unit is a trailing edge testing circuit among this embodiment, and it comprises phase inverter and NOR gate.One of them input of phase inverter input and NOR gate is connected synchronous signal input end 31, and the output of phase inverter connects another input of NOR gate.One end of NOR gate directly connects outer synchronous signal input 31, and the other end is the signal after the paraphase of synchronous signal input end 31 input signals process phase inverter, when detecting the synchronizing signal of input, and the output output pulse signal of NOR gate; When the signal that detects input was level signal (fixing high level or low level), the signal that two inputs of NOR gate receive was just in time anti-phase, the fixing low level of NOR gate output.
Be same trigger with reference to the trigger 2 of scheming in the asserts signal generation unit and reset signal generation unit as can be known, these two unit comprise two d type flip flops in this enforcement profit---trigger 1, trigger 2 and or; As shown in the figure, or two inputs of door be respectively reversed-phase output Q1 end, the Q2 end of trigger 1 and trigger 2.The signal input part D1 of trigger 1 end for or the output of door, the internal clock signal that the input end of clock receive clock generator of trigger 1 produces, the signal of the in-phase output end Q1 of trigger 1 end output is sent into the input end of clock of trigger 2 as clock signal, for trigger 2 provides clock signal.The asynchronous set end SET end of two d type flip flops connects the NOR gate output.When receiving the pulse signal of NOR gate output, SET end set under the control of pulse signal of trigger 1, trigger 2, and latch this asserts signal; When receiving the level signal of NOR gate output, trigger 1, trigger 2 or door are all under the internal clock signal of clock generator output drives, constantly regulate output state, the in-phase output end Q2 end of final trigger 2 can reset, and till this reset signal is latched into next external signal input 31 input sync signals.
Output select unit is made up of three NAND gate.An input of NAND gate 1 connects the output of NOR gate, is used to receive the signal of edge detecting unit output, and another input connects the in-phase output end Q2 end of trigger 2.An input of NAND gate 2 connects the output of clock generator, and another input connects the reversed-phase output Q2 end of trigger 2.The output of NAND gate 1 and NAND gate 2 is connected two inputs of NAND gate 3 respectively, and the output of NAND gate 3 is the output 33 of whole device.When external input signal is synchronizing signal, the in-phase output end Q2 end output high level of trigger 2 is to NAND gate 1, reversed-phase output Q2 section output low level makes NAND gate 2 output high level to NAND gate 3 to NAND gate 2, and the output that the output of NAND gate 3 will be followed NAND gate 1 changes.Through behind twice gating, the synchronizing signal that outer synchronous signal input 31 receives be converted to behind the pulse signal will be as entire circuit export output port 33 to; When external input signal is level signal, the in-phase output end Q2 end output low level of trigger 2 is to NAND gate 1, make NAND gate 1 output high level to NAND gate 3, the reversed-phase output Q2 end output high level of trigger 2 is to an end of NAND gate 2, the output that makes the output of NAND gate 3 will follow NAND gate 2 changes, and the internal clock signal of clock-signal generator output can pass through NAND gate 2.Through behind twice gating, the clock signal of clock-signal generator output exports output port 33 to as entire circuit.
The concrete operation principle of this embodiment synchronization signal detection is as follows:
With reference to figure 5, be the process that the first embodiment of the invention pulse signal produces.When outer synchronous signal input 31 received synchronizing signal, phase inverter and NOR gate were converted to pulse signal with the trailing edge of synchronizing signal.Input signal is represented the synchronizing signal that synchronizing signal receiving terminal 31 receives in Fig. 5, and NOR gate has only when two inputs and just exports high level simultaneously when the low level.When the synchronizing signal trailing edge that receives when synchronizing signal receiving terminal 31 arrives, an input of NOR gate directly connects synchronizing signal receiving terminal 31 and is low level from the high level upset at once, and another input is the output that connects phase inverter, because the relation of phase inverter time-delay can not be high level from the low level upset at once, so, two inputs of NOR gate will have an of short duration moment to occur low level simultaneously, high level pulse of NOR gate output.
In-phase output end Q1, Q2 end was exported high level at once after the SET termination of two d type flip flops was received high level pulse.The reversed-phase output Q2 end output low level of trigger 2 makes NAND gate 2 output high level to NAND gate 3 to NAND gate 2, and the output that the output of NAND gate 3 will be followed NAND gate 1 changes.The in-phase output end Q2 end output high level of trigger 2 is to an end of NAND gate 1, the pulse signal that NOR gate produces can be by NAND gate 1 so, through behind twice gating, the synchronizing signal that outer synchronous signal input 31 receives be converted to behind the pulse signal will be as entire circuit export output port 33 to.
When not having the synchronizing signal input, the level signal of NOR gate output, trigger 1, trigger 2 or door are under the internal clock signal of clock generator output drives, constantly regulate output state, the in-phase output end Q2 end of final trigger 2 can reset, and till this reset signal is latched into next external input terminals 31 input sync signals.The in-phase output end Q2 end output low level of trigger 2 is to NAND gate 1, make NAND gate 1 output high level to NAND gate 3, the reversed-phase output Q2 end output high level of trigger 2 is to an end of NAND gate 2, the output that makes the output of NAND gate 3 will follow NAND gate 2 changes, and the internal clock signal of clock-signal generator output can pass through NAND gate 2.Through behind twice gating, the clock signal of clock-signal generator output exports output port 33 to as entire circuit.
Externally during the incoming level signal, the in-phase output end of trigger 1, trigger 2 and the initial condition of inverse output terminal are uncertain.When synchronous signal input end 31 just being discussed below not receiving synchronizing signal, the in-phase output end of trigger 1 and trigger 2 and reversed-phase output are in the process that trigger 2 under the various initial conditions produces reset signals:
With reference to figure 6, be first embodiment of the invention trigger 1 and trigger 2 in-phase output ends initially all during output low level reset signal produce schematic diagram;
Before the internal clock signal rising edge that clock-signal generator produces arrived, because the reversed-phase output Q2 of trigger 2 end is high level, the D1 termination of trigger 1 was received high level so.When the internal clock signal rising edge arrived, the in-phase output end Q1 of trigger 1 holds the assignment of the D1 end that will accept trigger 1 and upset takes place was high level.It is the clock signal of trigger 2 that the in-phase output end Q1 of trigger 1 rectifies, and therefore, trigger 2 also will overturn, its in-phase output end Q2 end upset back output high level.So, this moment trigger 1 and trigger 2 reversed-phase output Q2 end all be low level, or goalkeeper's output low level is held to the D1 of trigger 1.
When second rising edge of internal clock signal signal arrives, trigger 1 will overturn once more, the in-phase output end Q1 end output low level of trigger 1.Because what the homophase of current T-flip flop 1 output Q1 end produced is trailing edge, the in-phase output end Q2 end of trigger 2 will can not overturn.The reversed-phase output Q2 of trigger 1 end is high level, passes through so or behind the door, the D1 of trigger 1 end will receive high level.
When the 3rd rising edge of internal clock signal arrived, the D1 end of trigger 1 was inconsistent with the in-phase output end Q1 end level of trigger 1, and trigger 1 will overturn again, the in-phase output end Q1 end output high level of trigger 1.The clock signal terminal of trigger 2 receives the rising edge of the D1 end output of trigger 1, will overturn, and the in-phase output end Q2 end output low level of trigger 2 produces reset signal.After this, the D1 of trigger 1 end is consistent with the in-phase output end Q1 end level signal of trigger 1, and circuit state is latched, and whole testing circuit can not overturn before receiving synchronizing signal.
With reference to figure 7, be first embodiment of the invention trigger 1 and trigger 2 in-phase output ends initially respectively when output low level and high level reset signal produce schematic diagram;
Before first rising edge of internal clock signal signal arrived, the in-phase output end Q2 end of trigger 2 was high level, and the in-phase output end Q1 end of trigger 1 is low level.Or the signal that two inputs of door receive comprises a high level, a low level, first or goalkeeper export the D1 end of high level to trigger 1.
When first rising edge of internal clock signal arrives, the in-phase output end Q1 end of trigger 1 and the D1 end of trigger 1 are inconsistent, trigger 1 will overturn, and the in-phase output end Q1 end of trigger 1 turn to high level from low level, exports the clock signal terminal of a rising edge to trigger 2.Trigger 2 will overturn, and the in-phase output end Q2 end of trigger 2 turn to low level from high level.After this, the reversed-phase output Q2 of trigger 2 end output high level to or door, the D1 termination of trigger 1 is received high level, the D1 end level signal of the in-phase output end Q1 end of trigger 1 and trigger 1 is consistent, the short maintenance of the in-phase output end Q2 of trigger 2 low level.Circuit state is latched, and whole testing circuit can not overturn before receiving synchronizing signal.
With reference to figure 8, being first embodiment of the invention when trigger 1 and trigger 2 in-phase output ends are initially exported high level and low level respectively, reset signal produces schematic diagram;
In this case, or an input of door receives the high level of the reversed-phase output Q2 end output of trigger 2, or goalkeeper exports the D1 end of high level to trigger 1.The in-phase output end Q1 end level signal of the D1 end of trigger 1 and trigger 1 is consistent, and the in-phase output end Q2 end of trigger 2 remains low level, and circuit state is latched, and whole testing circuit can not overturn before receiving synchronizing signal.
With reference to figure 9, being first embodiment of the invention when trigger 1 and trigger 2 in-phase output ends are initially all exported high level, reset signal produces schematic diagram;
Before first rising edge of internal clock signal arrives, or two inputs of door all receive low level, with the D1 end of output low level to trigger 1.The in-phase output end Q1 end level signal of the D1 end of trigger 1 and trigger 1 is inconsistent, and when first rising edge of internal clock signal arrives, trigger 1 will overturn.Because what the in-phase output end Q1 of current T-flip flop 1 end produced is trailing edge, fellow villager's output Q2 end of trigger 2 will can not overturn.The reversed-phase output Q2 of trigger 1 end is high level, passes through so or behind the door, the D1 of trigger 1 end will receive high level.
When second rising edge of internal clock signal arrived, the in-phase output end Q1 end level of the D1 end of trigger 1 and trigger 1 was inconsistent, and trigger 1 will overturn again, the in-phase output end Q1 end output high level of trigger 1.The clock signal terminal of trigger 2 receives the rising edge of the in-phase output end Q1 end output of trigger 1, will the in-phase output end Q2 end output low level of T-flip flop 2 take place.After this, the in-phase output end Q1 end level signal of the D1 of trigger 1 end and trigger 1 is consistent, and circuit state is latched, and the in-phase output end Q2 end of trigger 2 keeps low level, and whole testing circuit can not overturn before receiving synchronizing signal.
With reference to figure 6 to four kinds of initial conditions with reference to figure 9, the in-phase output end Q2 end of trigger 2 is all stablized output low level at last, the in-phase output end of trigger 2 produces reset signal, the in-phase output end Q2 end output low level of trigger 2 is to NAND gate 1, make NAND gate 1 output high level to NAND gate 3, the reversed-phase output Q2 end output high level of trigger 2 is to an end of NAND gate 2, the output that makes the output of NAND gate 3 will follow NAND gate 2 changes, and the internal clock signal of clock-signal generator output can pass through NAND gate 2.Through behind twice gating, the clock signal of clock-signal generator output exports output port 33 to as entire circuit.
Above with reference to figure 6 to four processes with reference to figure 9 are full probability incidents, therefore, and though the technical solution of the present invention example can not have synchronizing signal when input select internal clock signal as output and the trigger initial condition how.
At this, it may be noted that a bit that in addition whole device will be reselected internal clock signal as output after outer synchronous signal disappears, program process produces the process of reset signal with identical with reference to figure 9 with previously described no synchronizing signal input at that time.
With reference to Figure 10, be the composition structure chart of second embodiment of sync signal detection apparatus of the present invention.The edge detecting unit of this embodiment is a rising edge testing circuit, it comprise phase inverter and with door.The phase inverter input be connected synchronous signal input end 31 with one of them input of door, the output of phase inverter connects another input with door.Directly be connected outer synchronous signal input 31 with an end of door, other end input be the signal of the synchronous signal input end 31 inputs signal after through the phase inverter paraphase, when detecting the synchronizing signal of input, with the output output pulse signal of door; When the signal that detects input is level signal (fixing high level or low level), just in time anti-phase with the signal that two inputs of door receive, with the fixing low level of door output.
Trigger 2 in the present embodiment in asserts signal generation unit and the reset signal generation unit is same trigger, and these two unit comprise two T triggers in this enforcement profit---trigger 1, trigger 2 and or door; Wherein, or two inputs of door are respectively reversed-phase output Q1 end, the Q2 end of trigger 1 and trigger 2, the signal input part T1 of trigger 1 end for or the output of door, the internal clock signal that the input end of clock receive clock generator of trigger 1 produces, the signal of the in-phase output end Q1 of trigger 1 end output is sent into the input end of clock of trigger 2 as clock signal, for trigger 2 provides clock signal.The asynchronous set end SET end of two T triggers connects the NOR gate output.When receiving the pulse signal of NOR gate output, SET end set under the control of pulse signal of trigger 1, trigger 2, and latch this asserts signal; When receiving the level signal of NOR gate output, trigger 1, trigger 2 or door are all under the internal clock signal of clock generator output drives, constantly regulate output state, the in-phase output end Q2 end of final trigger 2 can reset, and with this reset signal be latched into remain to next external input terminals 31 input sync signals till.
Output select unit is made up of three NOR gate in the present embodiment.An input of NOR gate 1 connects the output with door, is used to receive the signal of edge detecting unit output, and another input connects the reversed-phase output Q2 end of trigger 2.An input of NOR gate 2 connects the output of clock generator, and another input connects the in-phase output end Q2 end of trigger 2.The output of NOR gate 1 and NOR gate 2 is connected two inputs of NOR gate 3 respectively, and the output of NOR gate 3 is the output 33 of whole device.
The concrete operation principle of this embodiment synchronization signal detection is as follows:
With reference to Figure 11, be that the pulse signal of the present invention second embodiment shown in Figure 10 produces schematic diagram.When the figure illustrates synchronous signal input end 31 and receiving synchronizing signal, phase inverter and be converted to the process of pulse signal with the rising edge of goalkeeper's synchronizing signal.Input signal is represented the synchronizing signal that synchronizing signal receiving terminal 31 receives in Figure 11, has only with door and just export high level when two inputs are high level simultaneously.When the synchronizing signal rising edge that receives when synchronizing signal receiving terminal 31 arrives, directly be connected synchronizing signal receiving terminal 31 with an input of door, be high level, and another input is the output that connects phase inverter, because the relation of phase inverter time-delay can not be low level from the high level upset at once, so, will there be an of short duration moment to occur high level simultaneously, with high level pulse of door output with two inputs of door.
Present embodiment asserts signal generation unit is with the difference of reset signal generation unit with embodiment one: the trigger of use is different, asserts signal generation unit and reset signal generation unit comprise two T triggers---trigger 1, trigger 2 in the present embodiment.But the effect of T trigger is identical with the action effect of d type flip flop among the embodiment one, therefore, embodiment two and embodiment one be not when synchronous signal input end 31 receives synchronizing signal, the process that trigger 2 produces reset signals is the same, at this repeated description not.
Output select unit is made up of three NOR gate in the present embodiment.An input of NOR gate 1 connects the output with door, is used to receive the signal of edge detecting unit output, and another input connects the reversed-phase output Q2 end of trigger 2.An input of NOR gate 2 connects the output of clock generator, and another input connects the in-phase output end Q2 end of trigger 2.The output of NOR gate 1 and NOR gate 2 is connected two inputs of NOR gate 3 respectively, and the output of NOR gate 3 is the output 33 of whole device.
When external input signal is synchronizing signal, the reversed-phase output Q2 end output low level of trigger 2 is to NOR gate 1, in-phase output end Q2 end output high level is to NOR gate 2, make NOR gate 2 output low levels to NOR gate 3, at this moment, the output that the output of NOR gate 3 will be followed NAND gate 1 changes, through behind twice gating, the synchronizing signal that outer synchronous signal input 31 receives be converted to behind the pulse signal will be as entire circuit export output port 33 to; When external input signal is level signal, the reversed-phase output Q2 end output high level of trigger 2 is to NOR gate 1, make NOR gate 1 output low level to NOR gate 3, the in-phase output end Q2 end output low level of trigger 2 is to an end of NOR gate 2, the output that makes the output of NOR gate 3 will follow NOR gate 2 changes, and the internal clock signal of clock-signal generator output can pass through NOR gate 2.Through behind twice gating, the clock signal of clock-signal generator output exports output port 33 to as entire circuit.
With reference to Figure 12, be the circuit structure diagram of the 3rd embodiment of sync signal detection apparatus of the present invention; This embodiment edge detecting unit be one bilateral along testing circuit, it comprises delayer and XOR gate.One of them input of delayer input and XOR gate is connected synchronous signal input end 31, and the output of delayer connects another input of XOR gate.One end of XOR gate directly connects outer synchronous signal input 31, and the other end is the signal after synchronous signal input end 31 input signals are delayed time through delayer, when detecting the synchronizing signal of input, and the output output pulse signal of XOR gate; When the signal that detects input was level signal (fixing high level or low level), the signal that two inputs of XOR gate receive was identical, the fixing low level of XOR gate output.
Trigger 2 in the present embodiment in asserts signal generation unit and the reset signal generation unit is same trigger, and these two unit comprise two JK flip-flop in this enforcement profit---trigger 1, trigger 2 and NAND gate; Two inputs of NAND gate are respectively the in-phase output end Q1 end of trigger 1 and the reversed-phase output Q2 end of trigger 2.The JK end of two triggers is connected together (following table is shown the J1K1 end), and the J1K1 end of trigger 1 is the output of NAND gate.The internal clock signal that the clock signal terminal receive clock generator of trigger 1 produces, the signal of the in-phase output end Q1 end output of trigger 1 is sent into the clock signal terminal of trigger 2 as clock signal, for trigger 2 provides clock signal.The SET end of two JK flip-flop connects the NOR gate output.When receiving the pulse signal of NAND gate output, SET end set under the control of pulse signal of trigger 1, trigger 2, and latch this asserts signal; When receiving the level signal of NAND gate output, trigger 1, trigger 2 or door are all under the internal clock signal of clock generator output drives, constantly regulate output state, the in-phase output end Q2 end of final trigger 2 can reset, and till this reset signal is latched into next external input terminals 31 input sync signals.
In the present embodiment output select unit by two with one at door or form.An input of NOR gate 1 connects the output with door, is used to receive the signal of edge detecting unit output, and another input connects the reversed-phase output Q2 end of trigger 2.An input of NOR gate 2 connects the output of clock generator, and another input connects the in-phase output end Q2 end of trigger 2.The output of NOR gate 1 and NOR gate 2 is connected two inputs of NOR gate 3 respectively, and the output of NOR gate 3 is the output 33 of whole device.
The concrete operation principle of this embodiment synchronization signal detection is as follows:
With reference to Figure 13, be that the pulse signal of the present invention the 3rd embodiment shown in Figure 15 produces schematic diagram.When synchronous signal input end 31 received synchronizing signal, delayer and XOR gate were converted to the bilateral edge of synchronizing signal the process of pulse signal.Input signal is represented the synchronizing signal that synchronizing signal receiving terminal 31 receives in Figure 13, just exports high level when XOR gate has only the signal of importing when two inputs opposite.When the synchronizing signal rising edge that receives when synchronizing signal receiving terminal 31 arrives, an input of XOR gate directly connects synchronizing signal receiving terminal 31, be high level, and another input is the output that connects delayer, because the relation of time-delay can not be high level from the low level upset at once, so, it is high level that two inputs of XOR gate will have of short duration moment input, another input is a low level, high level pulse of the opposite output of two input signals of XOR gate; When the trailing edge of the synchronizing signal that receives when synchronizing signal receiving terminal 31 arrives, an input of XOR gate directly connects synchronizing signal receiving terminal 31, be low level, and another input is the output that connects delayer, because the relation of time-delay can not be low level from the high level upset at once, so, it is high level that two inputs of XOR gate will have of short duration moment input, another input is a low level, high level pulse of the opposite output of two input signals of XOR gate.
The difference of asserts signal generation unit and reset signal generation unit and embodiment one is in the present embodiment: trigger is two JK flip-flop---trigger 1, trigger 2, gate are NAND gate.The JK end of two triggers is connected together (following table is shown the J1K1 end), and the J1K1 end of trigger 1 is the output of NAND gate.The effect of JK flip-flop is identical with the action effect of d type flip flop among the embodiment one in the present embodiment, the effect of NAND gate also with embodiment in or the door effect identical, therefore present embodiment three and embodiment one be not when synchronous signal input end 31 receives synchronizing signal, the process that trigger 2 produces reset signals is the same, at this repeated description not.
Output select unit by two with one at door or form.An input of NOR gate 1 connects the output with door, is used to receive the signal of edge detecting unit output, and another input connects the reversed-phase output Q2 end of trigger 2.An input of NOR gate 2 connects the output of clock generator, and another input connects the in-phase output end Q2 end of trigger 2.The output of NOR gate 1 and NOR gate 2 is connected two inputs of NOR gate 3 respectively, and the output of NOR gate 3 is the output 33 of whole device.
When external input signal is synchronizing signal, the in-phase output end Q2 of trigger 2 end output high level to door 1, reversed-phase output Q2 end output low level and door 2, make with door 2 output low levels to or door 3, at this moment, or the output that door 3 output will be followed with door 1 changes, through behind twice gating, the synchronizing signal that outer synchronous signal input 31 receives be converted to behind the pulse signal will be as entire circuit export output port 33 to; When external input signal is level signal, the in-phase output end Q2 of trigger 2 end output low level to door 1, make with door 1 output low level to or door 3, the reversed-phase output Q2 of trigger 2 end output high level to an end of door 2, make or output that door 3 output will be followed with door 2 changes, the internal clock signal of clock-signal generator output can by with door 2.Through behind twice gating, the clock signal of clock-signal generator output exports output port 33 to as entire circuit.
In these three embodiment, the pulse signal of edge detecting unit output can be high level pulse, also can be low level pulse, if when being high level pulse, the SET of trigger is that high level is effective, if when being low level pulse, the SET of trigger is that low level is effective.
In specific implementation, the present invention can also use rest-set flip-flop etc. to produce asserts signal under pulse signal control and can latch all triggers of asserts signal, and the triggering mode of trigger can be level triggers, rising edge triggers or trailing edge triggers.Gate can use or door, with door, NOR gate, NAND gate, XOR gate, biconditional gate, phase inverter, with or, same NOR gate, and the combination of above-mentioned gate etc. can cooperate in-phase output end the arithmetic logic unit from arbitrary initial state transitions to stable output reset signal of the internal clock signal of clock generator output with trigger 2 when receiving level signal.
Above disclosed only is preferred embodiment of the present invention, can not limit the present invention's interest field certainly with this, and therefore the equivalent variations of doing according to claim of the present invention still belongs to the scope that the present invention is contained.
Claims (8)
1, a kind of sync signal detection apparatus is characterized in that, comprising:
Edge detecting unit is used to detect institute's edge of input synchronous signal, when detecting the synchronizing signal edge, produces pulse signal, otherwise, produce level signal;
Clock generator is used to produce internal clock signal;
The pulse signal detecting unit links to each other with described clock generator with described edge detecting unit respectively; When receiving the pulse signal of described edge detecting unit output, under described pulse signal control, produce asserts signal, when receiving the level signal of described edge detecting unit output, under the driving of the internal clock signal that described clock generator is exported, produce reset signal;
Output select unit is used for exporting described pulse signal when receiving the asserts signal of described pulse signal detecting unit output, when receiving the reset signal of described pulse signal detecting unit output, exports described internal clock signal.
2, sync signal detection apparatus as claimed in claim 1 is characterized in that, described pulse signal detecting unit comprises:
The asserts signal generation unit is used for when receiving the pulse signal of described edge detecting unit generation, under described pulse signal control, produces also output asserts signal;
The reset signal generation unit, be used for when receiving the level signal of described edge detecting unit output, under the driving of the internal clock signal that described clock generator is exported, make arbitrary initial output state become stable output reset signal state, and export described reset signal.
3, sync signal detection apparatus as claimed in claim 2, it is characterized in that, described asserts signal generation unit is first trigger, the asynchronous set end of described first trigger links to each other with the output of described edge detecting unit, receive the pulse signal of described edge detecting unit output, in-phase output end links to each other with the input of described output select unit, and the output asserts signal is to the input of described output select unit.
4, sync signal detection apparatus as claimed in claim 3 is characterized in that, described reset signal generation unit comprises the logical AND not gate, second trigger and the 3rd trigger; An input of described logical AND not gate links to each other with the described second trigger in-phase output end, and another input links to each other with described the 3rd trigger in-phase output end, and the output of logical AND not gate links to each other with the signal input part of described second trigger; The asynchronous set end of described second trigger links to each other with the output of described edge detecting unit with the asynchronous set end of described the 3rd trigger, receive the level signal of described edge detecting unit output, the input end of clock of described second trigger links to each other with the output of described clock generator, and the input end of clock of described the 3rd trigger links to each other with the in-phase output end of described second trigger; The signal input part of described the 3rd trigger links to each other with the inverse output terminal of described the 3rd trigger, and the in-phase output end of described the 3rd trigger links to each other with the input of described output select unit, and the output reset signal is to the input of described output select unit.
5, sync signal detection apparatus as claimed in claim 3 is characterized in that, described reset signal generation unit comprises logic sum gate, second trigger and the 3rd trigger; An input of described logic sum gate links to each other with the described second trigger reversed-phase output, and another input links to each other with described the 3rd trigger reversed-phase output, and the output of logic sum gate links to each other with the signal input part of described second trigger; The asynchronous set end of described second trigger links to each other with the output of described edge detecting unit with the asynchronous set end of described the 3rd trigger, receive the level signal of described edge detecting unit output, the input end of clock of described second trigger links to each other with the output of described clock generator, and the input end of clock of described the 3rd trigger links to each other with the in-phase output end of described second trigger; The signal input part of described the 3rd trigger links to each other with the inverse output terminal of described the 3rd trigger, and the in-phase output end of described the 3rd trigger links to each other with the input of described output select unit, and the output reset signal is to the input of described output select unit.
As claim 4 or 5 described sync signal detection apparatus, it is characterized in that 6, described first trigger and described the 3rd trigger are same trigger.
7 sync signal detection apparatus as claimed in claim 6 is characterized in that, described same trigger is the trigger with latch function.
8, sync signal detection apparatus as claimed in claim 1 is characterized in that, described edge detecting unit is rising edge testing circuit or trailing edge testing circuit or bilateral along testing circuit.
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| CN108964638B (en) * | 2018-05-29 | 2023-08-25 | 苏州大学 | Novel signal rising edge detection circuit |
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