CN104345264B - Clock edge arrangement for detecting and method - Google Patents

Clock edge arrangement for detecting and method Download PDF

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Publication number
CN104345264B
CN104345264B CN201310323106.0A CN201310323106A CN104345264B CN 104345264 B CN104345264 B CN 104345264B CN 201310323106 A CN201310323106 A CN 201310323106A CN 104345264 B CN104345264 B CN 104345264B
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CN
China
Prior art keywords
detecting
measured
negative edge
clock pulses
clock
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CN201310323106.0A
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Chinese (zh)
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CN104345264A (en
Inventor
罗宇诚
陈莹晏
曾昭文
李日农
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瑞昱半导体股份有限公司
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Abstract

The invention discloses a kind of clock edge arrangement for detecting, can detect positive edge and the negative edge of a clock pulses to be measured, including:One delay circuit, including multiple concatenated delay cells, for receiving the clock pulses to be measured and being transmitted;One buffer circuit, including multiple buffers, couple the delay circuit, for according to a work clock pulse recording and exporting multiple levels of the clock pulses to be measured, wherein often the buffer includes a data input pin, a data output end and a work clock pulse receiving terminal, the work clock pulse receiving terminal is used for receiving the work clock pulse, which is coupled between two adjacent delay cells;One just along circuit for detecting, including it is multiple just along detecting unit, those data output ends of the buffer circuit are coupled, for detecting the positive edge of the clock pulses to be measured;And a negative edge circuit for detecting, including multiple negative edge detecting units, couple those data output ends, for detecting the negative edge of the clock pulses to be measured.

Description

Clock edge arrangement for detecting and method

Technical field

The present invention relates to level arrangement for detecting and methods, especially with respect to clock edge arrangement for detecting and method.

Background technology

General electronic circuit is needed according to a pulse reference clock to allow individual elements to be operated or allowed different components same Step running.The pulse reference clock is usually generated by a frequency synthesizer according to a source clock pulses.In order to ensure the ginseng It examines clock pulses there is impartial high levle to hold time and held time with low level to avoid accidentally operating(malfunction), The pulse reference clock that it is 50% work period that the frequency synthesizer, which should ideally generate,.However, due to process drift(process variation)Relationship, the work period of pulse reference clock caused by the frequency synthesizer may be totally different in 50%, and by Limitation in design resource, the frequency synthesizer may not have enough preset calibration functions to correct the work period Deviation.Therefore, the factor of process drift and design resource efficiently use in order to balance, and the art needs one kind can The technology of the work period of pulse reference clock is detected, the influence of process drift is thereby understood and provides relevant parameter for correction Or it is utilized for design in the future.

More following documents are can refer to about the prior art of this field:The United States Patent (USP) of the patent No. 6671652;The patent No. 7400555 United States Patent (USP);And the United States Patent (USP) of the patent No. 7403055.

Invention content

In view of above-mentioned, of the invention one is designed to provide a kind of clock edge arrangement for detecting and a kind of clock pulses Edge method for detecting, thereby detects positive edge and the negative edge of a clock pulses to be measured, and generates a detecting result for later use.

Another object of the present invention is to provide a kind of clock edge arrangement for detecting to detect with a kind of clock edge Survey method thereby calculates the work period of a clock pulses to be measured for correction or design reference.

The invention discloses a kind of clock edge arrangement for detecting, can detect a clock pulses to be measured it is positive along with it is negative Edge.An embodiment according to the present invention, the clock edge arrangement for detecting include:One delay circuit, including multiple concatenated Delay cell, for receiving the clock pulses to be measured and being transmitted;One buffer circuit, including multiple buffers, coupling should Delay circuit, for according to a work clock pulse recording and exporting multiple levels of the clock pulses to be measured, wherein often this is temporarily Storage includes a data input pin, a data output end and a work clock pulse receiving terminal, which receives End is used for receiving the work clock pulse, which is coupled between the two adjacent delay units;One is positive along detecting electricity Road, including it is multiple just along detecting unit, those data output ends of the buffer circuit are coupled, for detecting the clock arteries and veins to be measured The positive edge of punching couples the number of the two adjacent buffers wherein often this just includes one positive along detecting logic unit along detecting unit According to output end, a positive edge detecting is generated for the level of the clock pulses to be measured recorded respectively according to the two adjacent buffer Value;And a negative edge circuit for detecting, including multiple negative edge detecting units, couple those data output ends of the buffer circuit, For detecting the negative edge of the clock pulses to be measured, wherein often the negative edge detecting unit includes that a negative edge detects logic unit, coupling Data output end of the two adjacent buffers, for the clock pulses to be measured recorded respectively according to the two adjacent buffer Level generate a negative edge detecting value.

In above-described embodiment, which can further include:One counting circuit couples the positive edge Circuit for detecting and the negative edge circuit for detecting, for just calculating the clock to be measured along detecting value and those negative edge detecting values according to those The work period of pulse.

Also disclosed is a kind of clock edge method for detecting, can detect a clock pulses to be measured it is positive along with Negative edge is to be executed by the clock edge arrangement for detecting or its equivalent device of the present invention.An embodiment according to the present invention, The clock edge method for detecting comprises the steps of:It receives the clock pulses to be measured and prearranged is transmitted across according to one Journey transmits the clock pulses to be measured;Multiple reference position values according to the work clock pulse recording clock pulses to be measured;Foundation Multiple reference position value carries out a positive edge detecting logical operation, to detect the positive edge of the clock pulses to be measured, and generates multiple positive edges Detecting value;It stores multiple just along detecting value;A negative edge is carried out according to multiple reference position value and detects logical operation, is waited for detecting this The negative edge of clock pulses is surveyed, and generates multiple negative edge detecting values;And the multiple negative edge detecting value of storage, the wherein positive edge detecting Logical operation is different from negative edge detecting logical operation.

In above-described embodiment, which can further include the following steps:According to those positive edges Detecting value calculates the work period of the clock pulses to be measured with those negative edge detecting values.

Feature, implementation and effect for the present invention, hereby schema being coordinated to make preferred embodiment, detailed description are as follows.

Description of the drawings

Fig. 1 is the schematic diagram of an embodiment of the clock edge arrangement for detecting of the present invention;

Fig. 2 a are Fig. 1 just along the schematic diagram of an embodiment of circuit for detecting;

Fig. 2 b are Fig. 1 just along the schematic diagram of another embodiment of circuit for detecting;

Fig. 3 a are the schematic diagram of an embodiment of the negative edge circuit for detecting of Fig. 1;

Fig. 3 b are the schematic diagram of another embodiment of the negative edge circuit for detecting of Fig. 1;

Fig. 4 is the schematic diagram of another embodiment of the clock edge arrangement for detecting of the present invention;

Fig. 5 is the schematic diagram of the another embodiment of the clock edge arrangement for detecting of the present invention;

Fig. 6 is the flow chart of an embodiment of the clock edge method for detecting of the present invention;

Fig. 7 is the flow chart of another embodiment of the clock edge method for detecting of the present invention;

Fig. 8 is the flow chart of the another embodiment of the clock edge method for detecting of the present invention.

Wherein, the reference numerals are as follows:

100 clock edge arrangement for detecting

110 delay circuits

112 delay cells

120 buffering circuits

122 temporary storage locations

130 just along circuit for detecting

132 just along detecting unit

1322 is positive along detecting logic unit

1324 storage elements

140 negative edge circuit for detecting

142 negative edge detecting units

1422 negative edges detect logic unit

1424 storage elements

150 counting circuits

160 control circuits

400 clock edge arrangement for detecting

500 clock edge arrangement for detecting

S610 receives a clock pulses to be measured and transmits the clock pulses to be measured according to a prearranged transmission process

Multiple reference position values of the S620 according to the work clock pulse recording clock pulses to be measured

S630 carries out a positive edge detecting logical operation according to multiple reference position value, to detect the clock pulses to be measured just Edge, and generate multiple just along detecting value

S640 storages are multiple just along detecting value

S650 carries out a negative edge according to multiple reference position value and detects logical operation, to detect the negative of the clock pulses to be measured Edge, and generate multiple negative edge detecting values

S660 stores multiple negative edge detecting value

S670 is just calculating the work period of the clock pulses to be measured according to those along detecting value and those negative edge detecting values

S680 adjusts the work period of a clock pulses according to the work period of the clock pulses to be measured

Specific implementation mode

The technical terms of following description refer to the idiom of the art, if this specification is to part term Be illustrated or define, the part term explanation system be subject to this specification explanation or definition.

The disclosure includes clock edge arrangement for detecting and method, for detecting a clock pulses to be measured It is positive along and negative edge, thereby generate a detecting result for later use.The device and method can be applied to an integrated circuit or One system and device, under the premise of being embodied as possible, the art has usually intellectual can be according to the disclosure of this specification Content realizes the present invention to select equivalent component or step, that is, the implementation of the present invention be not limited to after the embodiment chatted. By the clock edge arrangement for detecting members that are included of the present invention it is independent for may be known tip assemblies, Under the premise of the abundant open and exploitativeness for not influencing the device inventions, illustrate that the details of known tip assemblies will be given below Memorandum.In addition, the present invention clock edge method for detecting can by the present invention clock edge arrangement for detecting or its Equivalent device is realized, under the premise of not influencing the abundant open and exploitativeness of this method invention, what following methods were invented Illustrate to will focus on step content and non-hardware.

Referring to Fig. 1, it is the schematic diagram of an embodiment of the clock edge arrangement for detecting of the present invention, the embodiment Can detect a clock pulses to be measured it is positive along and negative edge, and generate it is multiple just along detecting value and negative edge detecting value for utilizing, should Clock pulses to be measured may be derived from being easy in the part for being easy to happen clock pulses drift in an integrated circuit or the integrated circuit The part influenced by clock pulses drift.As shown in Figure 1, the clock edge arrangement for detecting 100 of the present embodiment includes:One Delay circuit 110, including multiple concatenated delay cells 112(Such as the group of phase inverter, buffer or phase inverter and buffer It closes), for receiving the clock pulses to be measured and being transmitted;One buffer circuit 120, including multiple buffers 122(Such as just Anti- device), the delay circuit 110 is coupled, for one work clock pulse recording of foundation and exports the multiple of the clock pulses to be measured Level receives wherein each buffer 112 includes a data input pin, a data output end and a work clock pulse End, the work clock pulse receiving terminal are used for receiving the work clock pulse, which is coupled to two adjacent delay lists Between member 112;One just along circuit for detecting 130, including it is multiple just along detecting unit 132, couple those of the buffer circuit 120 Data output end, for detecting the positive edge of the clock pulses to be measured, wherein each this is just detectd along detecting unit 132 comprising a positive edge Survey logic unit 1322(Such as the combination of logic gate or logic gate and phase inverter), couple two adjacent buffers 122 data it is defeated Outlet generates a positive edge detecting for the level of the clock pulses to be measured recorded respectively according to the two adjacent buffer 122 Value;And a negative edge circuit for detecting 140, including multiple negative edge detecting units 142(Such as logic gate or logic gate and phase inverter Combination), those data output ends of the buffer circuit 120 are coupled, for detecting the negative edge of the clock pulses to be measured, wherein often A negative edge detecting unit 142 includes that a negative edge detects logic unit 1422, the data output of two adjacent buffers 122 of coupling End generates a negative edge detecting value for the level of the clock pulses to be measured recorded respectively according to the two adjacent buffer 122. The above-mentioned work period that just can be used to define the clock pulses to be measured along detecting value and negative edge detecting value, this part illustrate after holding.

Please continue to refer to Fig. 1, delay circuit 110 can be made of one or more phase inverters and/or one or more buffers, And the number of the phase inverter passed through according to the clock pulses to be measured, often this is just along detecting unit 132 and often negative edge detecting list Member 142 can impose different disposal to the clock pulses to be measured received respectively, thereby carry out just edge and negative edge detecting.Citing comes It says, if one is just passed through along detecting unit 132 by two clock pulses to be measured that the data output end of two temporary storage locations 122 is received Odd number or even number(Including zero)Phase inverter, this just can be suitable by the transmission of two clock pulses to be measured along detecting unit 132 The later person of sequence imposes reverse phase processing, then executes a logical AND again(Logic AND)Processing(As shown in Figure 2 b);If a positive edge Two clock pulses to be measured that detecting unit 132 is received pass through odd number and even number of inverters respectively, this is just along detecting unit 132 belong to one just along the odd number person of the detecting unit order of connection two clock pulses to be measured can be imposed the reverse phase processing and Logical AND processing, and this just belongs to this along detecting unit 132 and two can just waited for this along the even number person of the detecting unit order of connection It surveys clock pulses and imposes logical AND processing(As shown in Figure 2 a);On the other hand, if a negative edge detecting unit 142 is temporary single by two Two clock pulses to be measured that the data output end of member 122 is received pass through the phase inverter of odd number or even number, which detects The transmission sequence earlier one of two clock pulses to be measured can be imposed reverse phase processing by surveying unit 142, then execute the logic again With processing(As shown in Figure 3b);And if two clock pulses to be measured that a negative edge detecting unit 142 is received pass through odd number respectively And the phase inverter of even number, the negative edge detecting unit 142 belong to a negative edge detecting unit order of connection odd number person can to this two Clock pulses to be measured imposes logical AND processing, and the negative edge detecting unit 142 belongs to the negative edge detecting unit order of connection Even number person then can impose two clock pulses to be measured reverse phase processing and logical AND processing(As shown in Figure 3a).

Fig. 2 a are please referred to, are Fig. 1 just along the schematic diagram of an embodiment of circuit for detecting 130, as shown, when this In clock edge arrangement for detecting 100, multiple delay cell 112 is phase inverter, this former two adjacent positive edge detectings One of unit 132 it can be utilized positive along detecting logic unit 1322 to the clock pulses to be measured make reverse phase processing and The processing of one logical AND, another just can then utilize its positive edge detecting logic unit 1322 to the clock to be measured along detecting unit 132 Logical AND processing is made in pulse, thereby generates those just along detecting value.Fig. 2 b separately are please referred to, are Fig. 1 just along circuit for detecting The schematic diagram of 130 another embodiment, as shown, in the clock edge arrangement for detecting 100, multiple delay cell 112 be buffer, those just can execute identical or equivalent place along detecting unit 132 to the clock pulses to be measured received at this time Reason, to generate those just along detecting value, more precisely, often this just can utilize it positive along detecting logic list along detecting unit 132 The transmission sequence earlier one of first 1322 pairs of two clock pulses to be measured received imposes logical AND processing, and to this two it is to be measured when The later person of transmission sequence of clock imposes reverse phase processing and is handled with the logical AND.

Please continue to refer to Fig. 2 a and Fig. 2 b, in this two embodiment, often this just additionally comprises a positive edge along detecting unit 132 and detects Measured value storage element 1324(A such as flip-flop), the positive edge detecting logic unit 1322 is coupled, when being used for according to the work Clock records this just along detecting value.However in another embodiment of the present invention, those are just coupled to one along detecting unit 132 Storage circuit(Non- icon), and those are just being stored in along detecting value in the storage circuit, wherein the storage circuit can pass through The technology known is realized.

On the other hand, Fig. 3 a are please referred to, are the schematic diagram of an embodiment of the negative edge circuit for detecting 140 of Fig. 1, as schemed institute Show, in the clock edge arrangement for detecting 100, multiple delay cell 112 is phase inverter, this former two adjacent One of negative edge detecting unit 142 can impose the clock pulses to be measured the processing of one logical AND, and the detecting of another negative edge is single Member 142 can then impose the clock pulses to be measured the processing of one reverse phase and logical AND processing, thereby generate the detecting of those negative edges Value.Fig. 3 b separately are please referred to, are the schematic diagram of another embodiment of the negative edge circuit for detecting 140 of Fig. 1, as shown, when this In clock edge arrangement for detecting 100, multiple delay cell 112 is buffer, at this time those 142 meetings of negative edge detecting unit Identical or equivalent process is executed to the clock pulses to be measured, to generate those negative edge detecting values, more precisely, often the negative edge is detectd Survey the transmission sequence earlier one that unit 142 can utilize its negative edge detecting logic unit 1422 to two clock pulses to be measured received It imposes reverse phase processing to handle with a logical AND, and the logical AND is imposed to the later person of transmission sequence of two clock pulses to be measured Processing.

Please continue to refer to Fig. 3 a and Fig. 3 b, in this two embodiment, often the negative edge detecting unit 142 additionally comprises a negative edge and detects Measured value storage element 1424(A such as flip-flop), negative edge detecting logic unit 1422 is coupled, when being used for according to the work Clock records the negative edge detecting value.However in another embodiment of the present invention, those negative edge detecting units 142 are coupled to one Storage circuit(Non- icon), and those negative edge detecting values are stored in the storage circuit, wherein the storage circuit can pass through The technology known is realized.Note that it is aforesaid plurality of just along detecting value need to record at least two it is positive along and multiple negative edge detecting values need to remember A record at least negative edge or those negative edge detecting values need to record at least two negative edges and those and just need to record at least one just along detecting value Edge thereby preserves enough clock edge information for utilization, in other words, the number of delay cell 112, temporary storage location 122 number, the number just along the number of detecting unit 132 and negative edge detecting unit 142 must be enough to record bottom line Clock edge information is for utilization.

Referring to Fig. 4, it is the schematic diagram of another embodiment of the clock edge arrangement for detecting of the present invention.Fig. 4 with Fig. 1's the difference is that the clock edge arrangement for detecting 400 of Fig. 4 further includes:One counting circuit 150 couples the positive edge Circuit for detecting 130 and the negative edge circuit for detecting 140, are waited for for just calculating this with those negative edge detecting values along detecting value according to those Survey the work period of clock pulses.More precisely, the counting circuit 150 according to those just along the positive edge that detecting value is recorded The molecule for being spaced the work period to determine the clock pulses to be measured of the negative edge recorded with those negative edge detecting values, and according to It determines according to the interval of those two negative edges just recorded along the interval on the two positive edges that detecting value is recorded or those negative edge detecting values The denominator of the work period of the fixed clock pulses to be measured, and then calculate the clock pulses to be measured according to the molecule and the denominator Work period.For example, it is assumed that those are just 0001000000000100000000 along detecting value, those negative edge detecting values are 0000000001000000000100, the counting circuit 150 can be by those just along first positive edge of detecting value and those at this time Molecule of the interval 6 of first negative edge of negative edge detecting value as the work period of the clock pulses to be measured, and by two it is adjacent just The denominator of edge or the interval 10 of two adjacent negative edges as the work period of the clock pulses to be measured, thereby by the molecule divided by this point Mother is to obtain the work period as 6/10, and also as 60%.In the present embodiment, which additionally comprises a storage element (Non- icon), for storing the work period for access.

Referring to Fig. 5, it is the schematic diagram of the another embodiment of the clock edge arrangement for detecting of the present invention.Fig. 5 with Fig. 4's the difference is that the clock edge arrangement for detecting 500 of Fig. 5 further includes:One control circuit 160, couples the calculating Circuit 150 is used for adjusting the work period of a clock pulses, wherein the clock arteries and veins according to the work period of the clock pulses to be measured Punching can be the clock pulses to be measured or its source clock pulses.Above-mentioned control circuit 160 can pass through known pulse width tune It is whole(pulse width modulation)Technology realizes to realize, or via other known work period adjustment technology, Since those skilled in the art can on demand or design specification uses the known work period adjustment technology to realize the control Circuit processed, not influencing the abundant openly and under the premise of exploitativeness of the present invention, it is not necessary to explanation omitted herein.

Referring to Fig. 6, in addition to clock edge arrangement for detecting above-mentioned, the present invention also provides a kind of clock edge Method for detecting, can detect positive edge and the negative edge of a clock pulses to be measured, and this method can be detectd by the clock edge of the present invention Device or its equivalent device are surveyed to execute, and is comprised the steps of:

Step S610:It receives a clock pulses to be measured and transmits the clock to be measured according to a prearranged transmission process Pulse.This step can be executed by the delay circuit 110 or its equivalent circuit of Fig. 1;

Step S620:Multiple reference position values according to the work clock pulse recording clock pulses to be measured.This step can be by It is executed by the buffering circuit 120 or its equivalent circuit of Fig. 1;

Step S630:A positive edge detecting logical operation is carried out according to multiple reference position value, to detect the clock pulses to be measured Positive edge, and generate multiple just along detecting value.This step can just holding along circuit for detecting 130 or its equivalent circuit by Fig. 1 Row;

Step S640:It stores multiple just along detecting value.This step can be by the storage element 1324 of Fig. 2 a and Fig. 2 b It executes;

Step S650:A negative edge is carried out according to multiple reference position value and detects logical operation, to detect the clock pulses to be measured Negative edge, and generate multiple negative edge detecting values, wherein negative edge detecting logical operation is different from aforementioned positive along detecting logical operation. This step can be executed by the negative edge circuit for detecting 140 or its equivalent circuit of Fig. 1;And

Step S660:Store multiple negative edge detecting value, wherein those negative edge detecting values record at least two negative edges and those Just at least one positive edge is recorded along detecting value or those just record at least two positive edges along detecting value and those negative edge detecting values record An at least negative edge.This step can be executed by the storage element 1424 of Fig. 3 a and Fig. 3 b.

From the above, when the prearranged transmission process system using multiple phase inverters come when executing(Such as Fig. 2 a with figure Shown in 3a), which imposes one first and handles, and to this three The latter two of a continuous reference position value impose a second processing, which detects logical operation then to three continuous reference position values The former two imposes the second processing, and imposes first processing to this three continuous reference position values the latter two, in the present embodiment, First processing system, one reverse phase processing is handled with a logical AND, the second processing system logical AND processing.In addition, working as the advance peace The transmission process system of row is using multiple buffers come when executing(Such as shown in Fig. 2 b and Fig. 3 b), this is positive along detecting logical operation system The processing of one third is imposed to wantonly two continuous reference position values, negative edge detecting logical operation system applies wantonly two continuous reference position values With a fourth process, in the present embodiment, the former of the two continuous reference position value of third processing system pair imposes logical AND processing, and Reverse phase processing is imposed to the latter to handle with the logical AND, to impose this anti-by the former of the two continuous reference position value of fourth process system pair Phase processor is handled with the logical AND, and imposes logical AND processing to the latter.

Referring to Fig. 7, it is the schematic diagram of another embodiment of the clock edge method for detecting of the present invention, this implementation Example and the difference of Fig. 6 are that the present embodiment further includes the following steps:

Step S670:The work week of the clock pulses to be measured is just being calculated along detecting value and those negative edge detecting values according to those Phase.For example, this step first can recorded just along the positive edge that detecting value is recorded with those negative edge detecting values according to those The interval of a negative edge determine the molecule of the work period of the clock pulses to be measured, then just recorded along detecting value according to those The interval on two positive edges or the interval of two negative edges that are recorded of those negative edge detecting values determine the work of the clock pulses to be measured The denominator in period then calculates the work period of the clock pulses to be measured according to the molecule and the denominator.Above-mentioned steps S670 It can be executed by the counting circuit 150 of Fig. 4.

Referring to Fig. 8, it is the schematic diagram of the another embodiment of the clock edge method for detecting of the present invention, this implementation Example and the difference of Fig. 7 are that the present embodiment further includes the following steps:

Step S680:The work period of a clock pulses is adjusted according to the work period of the clock pulses to be measured, wherein should Clock pulses can be the clock pulses to be measured or its source clock pulses.This step can be held by the control circuit 160 of Fig. 5 Row.

Due to the art, tool usually intellectual can understand by the disclosure of the device inventions of Fig. 1 to Fig. 5 Therefore the implementation detail of the method invention of Fig. 6 to Fig. 8 and variation to avoid superfluous text, are wanted in the disclosure for not influencing this method invention Ask and exploitativeness under the premise of, repeat and the explanation of redundancy will give memorandum.It is taken off in icon before note that, the shape of component, Sequence of size, ratio and step etc. is only to illustrate, and is to understand the present invention for the art tool usually intellectual to be used, It is non-limiting the present invention.In addition, the art personage can disclosure under this invention and the demand of itself selectively Implement some or all of any embodiment technical characteristic, or selectively implements some or all of multiple embodiments technology The combination of feature thereby increases the elasticity when present invention is implemented.

In conclusion clock edge arrangement for detecting disclosed in this invention can detect a clock arteries and veins to be measured with method The positive edge of punching and negative edge, thereby judge process drift or operating condition(Such as operating voltage)Etc. factors whether to the clock to be measured The work period of pulse impacts, and can be according to detecting result progress timing corrections or using the detecting result as subsequent design Reference.

Although the embodiment of the present invention is as described above, however those embodiments are not to be used for limiting the present invention, this field skill Art personnel can be according to the present invention the content expressed or implied to the present invention technical characteristic impose variation, all this kind variation The patent protection scope sought by the present invention may be belonged to, in other words, scope of patent protection of the invention must regard this specification Subject to as defined in claim.

Claims (19)

1. a kind of clock edge arrangement for detecting can detect positive edge and the negative edge of a clock pulses to be measured, including:
One delay circuit, including multiple concatenated delay cells, for receiving the clock pulses to be measured and being transmitted;
One buffer circuit is used for according to a work clock pulse recording simultaneously including multiple buffers, couple the delay circuit Multiple levels of the clock pulses to be measured are exported, wherein each buffer includes a data input pin, data output End and a work clock pulse receiving terminal, the work clock pulse receiving terminal are used for receiving the work clock pulse, institute Data input pin is stated to be coupled between two adjacent delay cells;
One just along circuit for detecting, including multiple couple the data output end of the buffer circuit just along detecting unit, uses It detects the positive edge of the clock pulses to be measured, described just includes along detecting unit wherein each:
One is positive along detecting logic unit, and the data output end of two adjacent buffers of coupling is used for according to two phases The level for the clock pulses to be measured that the adjacent buffer records respectively generates one just along detecting value;And
One negative edge circuit for detecting is used including multiple negative edge detecting units, couple the data output end of the buffer circuit The negative edge of the clock pulses to be measured is detected, wherein each negative edge detecting unit includes:
One negative edge detects logic unit, couples the data output end of two adjacent buffers, is used for according to two phases The level for the clock pulses to be measured that the adjacent buffer records respectively generates a negative edge detecting value;
Frequency, described just along circuit for detecting and institute of the frequency of the wherein described work clock pulse higher than the clock pulses to be measured It states negative edge circuit for detecting and detects the positive edge and the negative edge respectively;And
It is described just along detecting value record at least two it is positive along and the negative edge detecting value record at least one negative edge or the negative edge Detecting value records at least two negative edges and described just records at least one positive edge along detecting value.
2. clock edge arrangement for detecting according to claim 1, wherein the multiple delay cell is phase inverter, Adjacent described of any two just makees along one of detecting unit clock pulses to be measured described to received two at this time The processing of one reverse phase and a logical AND (Logic AND) processing;It is described two adjacent just along the other in which pair of detecting unit Two clock pulses to be measured received make the logical AND processing;The adjacent negative edge detecting unit of any two One of them is made the logical AND to two clock pulses to be measured received and handles;And described two adjacent negative edges are detectd The other in which for surveying unit makees the reverse phase processing and the logical AND to two clock pulses to be measured received Processing, thereby generates described just along detecting value and the negative edge detecting value.
3. clock edge arrangement for detecting according to claim 1, wherein the multiple delay cell is buffer, this Shi Suoshu just executes identical or equivalent process along detecting unit, and the negative edge detecting unit executes identical or equivalent process.
4. clock edge arrangement for detecting according to claim 3, wherein it is described just along detecting unit execute it is identical or Equivalent process includes:It is each described just more early to the transmission sequence of two clock pulses to be measured received along detecting unit Person imposes logical AND processing, is imposed at a reverse phase to the later person of transmission sequence of two clock pulses to be measured received Reason is handled with the logical AND;The negative edge detecting unit executes identical or equivalent process:Each negative edge detecting unit Reverse phase processing is imposed to the transmission sequence earlier one of two clocks to be measured received to handle with a logical AND, to being connect The later person of transmission sequence for two clock pulses to be measured received imposes logical AND processing.
5. clock edge arrangement for detecting according to claim 1, wherein
Described just pass through odd number along two clock pulses to be measured that detecting unit is received or even number is anti-if each Phase device, it is described that the later person of transmission sequence of described two clock pulses to be measured is just imposed into reverse phase processing along detecting unit, so After execute a logical AND processing;
If each described just pass through odd number and even number respectively along two clock pulses to be measured that detecting unit is received Phase inverter, it is described just to belong to one just along the odd number person of the detecting unit order of connection by described two clock arteries and veins to be measured along detecting unit Punching imposes reverse phase processing and is handled with the logical AND, and described just belong to described along detecting unit and just connecting along detecting unit Described two clock pulses to be measured are imposed the logical AND processing by the even number person for connecing sequence;
If two clock pulses to be measured that each negative edge detecting unit is received pass through odd number or even number Phase inverter, the negative edge detecting unit impose the transmission sequence earlier one of described two clock pulses to be measured at the reverse phase Reason then executes the logical AND processing;And
If two clock pulses to be measured that each negative edge detecting unit is received pass through odd number and even number respectively Phase inverter, the negative edge detecting unit belongs to the odd number person of a negative edge detecting unit order of connection to described two clocks to be measured Pulse imposes the logical AND processing, and the negative edge detecting unit belongs to the even number person of the negative edge detecting unit order of connection Described two clock pulses to be measured are imposed into the reverse phase processing and logical AND processing.
6. clock edge arrangement for detecting according to claim 1, wherein the buffer is flip-flop.
7. clock edge arrangement for detecting according to claim 1, wherein
It is each described just to be further included along detecting unit:
One just along detecting value storage element, and coupling is described positive along detecting logic unit, is used for remembering according to the work clock pulse It records described just along detecting value;And
Each negative edge detecting unit further includes:
One negative edge detecting value storage element couples the negative edge detecting logic unit, is used for remembering according to the work clock pulse Record the negative edge detecting value.
8. clock edge arrangement for detecting according to claim 1, wherein further include:
One counting circuit, coupling is described just along circuit for detecting and the negative edge circuit for detecting, is used for according to described just along detecting value The work period of the clock pulses to be measured is calculated with the negative edge detecting value.
9. clock edge arrangement for detecting according to claim 8, wherein the counting circuit is detectd according to the positive edge What measured value was recorded one positive determines the clock pulses to be measured along the interval of the negative edge recorded with the negative edge detecting value Work period molecule, and according to described just along the interval on two positive edges that detecting value is recorded or negative edge detecting value institute The denominator for being spaced the work period to determine the clock pulses to be measured of two negative edges of record, and then according to the molecule The work period of the clock pulses to be measured is calculated with denominator.
10. clock edge arrangement for detecting according to claim 8, wherein further include:
One control circuit couples the counting circuit, is used for adjusting a clock according to the work period of the clock pulses to be measured The work period of pulse.
11. a kind of clock edge method for detecting can detect positive edge and the negative edge of a clock pulses to be measured, by a clock arteries and veins Trimming is executed along arrangement for detecting, is comprised the steps of:
It receives the clock pulses to be measured and transmits the clock pulses to be measured according to a prearranged transmission process;
Multiple reference position values according to clock pulses to be measured described in a work clock pulse recording;
A positive edge detecting logical operation is carried out according to the multiple reference position value, to detect the positive edge of the clock pulses to be measured, and It generates multiple just along detecting value;
It stores the multiple just along detecting value;
A negative edge, which is carried out, according to the multiple reference position value detects logical operation, to detect the negative edge of the clock pulses to be measured, and Generate multiple negative edge detecting values;And
The multiple negative edge detecting value is stored,
The wherein described positive edge detecting logical operation is different from the negative edge detecting logical operation;
Frequency, described just along circuit for detecting and institute of the frequency of the wherein described work clock pulse higher than the clock pulses to be measured It states negative edge circuit for detecting and detects the positive edge and the negative edge respectively;And
It is described just along detecting value record at least two it is positive along and the negative edge detecting value record at least one negative edge or the negative edge Detecting value records at least two negative edges and described just records at least one positive edge along detecting value.
12. clock edge method for detecting according to claim 11, wherein the prearranged transmission process is It is realized using multiple phase inverters, the positive edge detecting logical operation described at this time is the former two to three continuous reference position values One first processing is imposed, and a second processing is imposed to the described three continuous reference position values the latter two, the negative edge is detectd It surveys logical operation and the second processing then is imposed to the former two of three continuous reference position values, and it is continuous to described three The latter two of the reference position value impose first processing.
13. clock edge method for detecting according to claim 12, wherein first processing is that a reverse phase is handled With logical AND processing, the second processing is logical AND processing.
14. clock edge method for detecting according to claim 11, wherein the prearranged transmission process is It is realized using multiple buffers, the positive edge detecting logical operation described at this time is that continuously the reference position value imposes to any two The processing of one third, the negative edge detecting logical operation is that continuously the reference position value imposes a fourth process to any two.
15. clock edge method for detecting according to claim 14, wherein the third processing is continuous to two The reference position value the former impose a logical AND processing, and to the latter impose a reverse phase processing with the logical AND handle;Institute It is that the former of two continuous reference position values is imposed reverse phase processing and handled with the logical AND to state fourth process, and right The latter imposes the logical AND processing.
16. clock edge method for detecting according to claim 11, wherein storage it is described just along detecting value the step of And the step of storing the negative edge detecting value, is executed according to the work clock pulse.
17. clock edge method for detecting according to claim 11, wherein further include the following steps:
According to the work period for just calculating the clock pulses to be measured along detecting value and the negative edge detecting value.
18. clock edge method for detecting according to claim 11, wherein calculate the work of the clock pulses to be measured The step of making the period include:
It determines according to the interval of the negative edge just recorded with the negative edge detecting value along the positive edge that detecting value is recorded The molecule of the work period of the fixed clock pulses to be measured;
According to two negative edges just recorded along the interval on two positive edges that detecting value is recorded or the negative edge detecting value Interval come determine the clock pulses to be measured work period denominator;And
The work period of the clock pulses to be measured is calculated according to the molecule and the denominator.
19. clock edge method for detecting according to claim 17, wherein further include the following steps:
The work period of a clock pulses is adjusted according to the work period of the clock pulses to be measured.
CN201310323106.0A 2013-07-29 2013-07-29 Clock edge arrangement for detecting and method CN104345264B (en)

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US6404833B1 (en) * 1997-07-31 2002-06-11 Komatsu Ltd. Digital phase synchronizing apparatus
WO2005001891A2 (en) * 2003-06-17 2005-01-06 Atmel Corporation Regenerative clock repeater
CN1921309A (en) * 2006-09-13 2007-02-28 华为技术有限公司 Synchronizing signal detecting device
CN101303887A (en) * 2007-05-08 2008-11-12 茂德科技股份有限公司(新加坡子公司) Perfect alignment and duty ratio control of data output of memory device

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