CN111384947A - Method, circuit and clock generating device for preventing clock overshoot - Google Patents

Abstract

The invention relates to a method, a circuit and a clock generation device for preventing clock overshoot, wherein the method for preventing clock overshoot comprises the following steps: acquiring a post-frequency-division control signal of a phase-locked loop, and judging whether the post-frequency-division control signal changes; when the post-frequency-division control signal changes, acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state; when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal. By implementing the technical scheme of the invention, the available clock can be provided more reliably and quickly at lower cost, the software running efficiency can be improved, and the power consumption can be saved.

Description

Method, circuit and clock generation device for preventing clock overshoot

technical field

The present invention relates to the field of phase-locked loops, and in particular, to a method, a circuit and a clock generating device for preventing clock overshoot.

Background technique

A phase-locked loop is a feedback control circuit called a phase-locked loop (Phase-Locked Loop, PLL for short). He uses the external input reference signal to control the frequency and phase of the oscillating signal inside the loop. In the process of processing electronic signals, because the phase-locked loop can automatically track the frequency of the output signal to the frequency of the input signal, the phase-locked loop is usually widely used in closed-loop tracking circuits. In the field of clocks, clock phase-locked loops are widely used in clock generation.

As shown in Figure 1, the clock phase-locked loop usually consists of several parts: phase detector PD, loop filter LPF, voltage-controlled oscillator VCO, loop divider LPDIV and post-divider PSTDIV. The frequency converter PSTDIV can make the clock output range wider, or greatly reduce the working range of the voltage controlled oscillator VCO, so it can reduce the design difficulty and improve the reliability.

The phase detector PD is a unit that completes phase comparison. Its function is to compare the phase difference between the input signal Fin and the feedback signal Fback. Its output voltage is proportional to the phase difference between the two input signals.

Low-pass filter LPF, is an active or passive low-pass filter. Its function is to filter out the high-frequency components (including mixing and other high-frequency noises) in the output voltage of the phase detector, play the role of smoothing and filtering, and finally output the control signal Vc. Usually consists of resistors, capacitors or inductors, etc., and sometimes includes operational amplifiers.

The voltage controlled oscillator VCO is an oscillator whose oscillation frequency is controlled by a control voltage, and there is a linear relationship between the oscillation frequency and the control voltage. The oscillator VCO outputs the corresponding oscillation frequency Fosc according to the control signal Vc.

The loop divider LPDIV determines the multiplier of the input and oscillation clock, but the integer can also be a decimal. The relationship is Fosc=N(lpdiv)*Fin.

The post-scaler PSTDIV, re-determines how the Fosc needs to be adjusted before outputting, which can be an integer or a decimal, and the final clock output Fout=[N(lpdiv)/N(pstdiv)]*Fin.

Generally speaking, after the PLL clock is locked, since the phase difference between the feedback clock and the input clock is stable, a stable clock can be output. When we want to change the output frequency Fout of the PLL, we only need to change the frequency division coefficient REG_LOOP corresponding to the loop divider and the frequency division coefficient REG_POST corresponding to the post divider.

It is well known that the equation describing a second-order phase-locked loop is a second-order nonlinear differential equation. The voltage-controlled oscillator VCO in the second-order phase-locked loop system can be regarded as an ideal integrator. So from the system point of view, if the low-pass filter LPF is first-order, the phase-locked loop PLL can be regarded as a second-order system. For a second-order system, there are natural frequencies ωn and damping coefficients ξ. If the parameters inside the system are suddenly changed, an intrinsic damping oscillation will occur according to the characteristics of the system. Under the same LPF conditions, the higher the VCO sensitivity, the smaller the ξ, the faster the locking, but the larger the amplitude of the damping oscillation; the larger the ξ, the smaller the amplitude of the damping oscillation, and when it is greater than 1, there is no damping oscillation, but The lock time becomes very long. Since the damping factor cannot be accurately controlled, and usually the PLL needs to lock as quickly as possible, there is a certain amplitude of oscillation damping oscillation in the output.

When the system changes the frequency division ratio, the PLL needs to be locked again, and the locking behavior takes a certain time. In general PLLs, their second-order response characteristics in the locked range are characterized by a damping factor. The faster the locking, the smaller the damping factor, the larger the overshoot occurs; even if the common damping factor is selected from 0.45 to 0.7, there is still a certain degree of overshoot.

Theoretically and in practice, the conventional overshoot will not be larger than very large, such as 10%-20%. Therefore, if the system provides enough safety margin, it will not bring too much problem.

The post-frequency divider has a very obvious feature: because it is not in the loop and does not have the loop bandwidth characteristics of the second-order system, the relative output Fout is an impulsive instantaneous response, so it directly affects the output, and in many cases will bring serious overshoot problem.

Combined with Figure 2, it is assumed: the input clock is 12.5MHz, the clock generation relationship is: Fout=[N(lpdiv)/N(pstdiv)]*Fin, the system requires the clock to be increased from 375MHz to 387.5MHz, and only needs to be increased by 12.5MHz, and the frequency switching is It is realized by changing the frequency division coefficients of the loop divider and the post divider: before switching, the loop frequency division coefficient is 60, and the post frequency division coefficient is 2; after switching, the loop frequency division coefficient becomes 31, and the latter The frequency division factor becomes 1. In the process of frequency switching, the frequency of Fosc can only be gradually changed through the loop. The loop filter has a fixed bandwidth, and the Vc controlled oscillator gradually changes from 750MHz to 387.5MHz; however, the post-division coefficient can instantly change from 2 to 2. 1, which causes Fout to directly change from the current 375MHz to 750MHz, thus causing a serious overshoot, and the system stabilizes to 387.5MHz after a long period of huge overshoot. If the post-level CPU cannot run at such a high frequency, for example, it can only work at a frequency of 500MHz at most, it will directly lead to a crash.

If the CPU is under 1V, the maximum operating frequency is only 500MHz (although there is already a very large margin for 375MHz), then the overshoot frequency of the above PLL of 750MH will inevitably lead to system errors. In order to prevent the system from crashing, a large voltage increase is required. However, in many cases, even if the voltage is increased, the running speed of the CPU cannot be improved all the time, for example, it cannot be 100% faster.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is that, in view of the defect in the prior art that overshoot occurs when the PLL output clock is adjusted by changing the frequency division coefficients of the loop frequency divider and the post-frequency divider, a method to prevent the clock from overshooting is provided. The method, circuit and clock generation device for overshoot can reduce the risk of overshoot.

The technical solution adopted by the present invention to solve the technical problem is: constructing a method for preventing clock overshoot, which is applied in a phase-locked loop with post-frequency division, and the phase-locked loop includes a phase detector, a low-pass filter, The voltage controlled oscillator, the loop frequency divider and the post frequency divider are used to change the frequency of the output signal of the phase-locked loop by changing the frequency division coefficient of the loop frequency divider and the frequency division coefficient of the post frequency divider. The following steps:

Obtain the post-frequency division control signal of the phase-locked loop, and determine whether the post-frequency division control signal changes;

When the post-frequency division control signal changes, the input signal and feedback signal of the phase-locked loop are acquired, and the current state of the phase-locked loop is determined according to the input signal and the feedback signal, and the state of the phase-locked loop includes: Locked state and unlocked state;

When the current state is an out-of-lock state, the output signal of the phase-locked loop is subjected to frequency reduction processing, and the signal after frequency reduction processing is used as a clock signal;

When the current state is the locked state, the output signal of the phase-locked loop is directly used as the clock signal.

Preferably, acquiring the post-frequency division control signal of the phase-locked loop, and judging whether the post-frequency division control signal has changed, includes:

Obtain the post-frequency division control signal and the loop frequency division control signal of the phase-locked loop, and determine whether the post-frequency division control signal and the loop frequency division control signal change.

Preferably, the current state of the phase-locked loop is determined according to the input signal and the feedback signal, including:

Comparing the input signal with the feedback signal, and judging whether the difference between the two is less than a threshold;

If the difference between the two within the preset period is less than the threshold, it is determined that the current state of the phase-locked loop is the locked state;

If the difference between the two within the preset time period is not less than the threshold, it is determined that the current state of the phase-locked loop is an out-of-lock state.

Preferably, frequency reduction processing is performed on the output signal of the phase-locked loop, including:

The output signal of the phase-locked loop is subjected to frequency reduction processing by the frequency reduction device, and the following conditions are met:

N(safdiv)≥N(lpdiv)/N(lpdiv_new),

Wherein, N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the frequency division coefficient before the loop frequency divider is changed, and N(lpdiv_new) is the frequency division coefficient after the loop frequency divider is changed .

The invention also constructs a circuit for preventing clock overshoot, which is applied in a phase-locked loop with post-frequency division, and the phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, and a loop frequency divider and a postscaler, the circuit for preventing clock overshoot includes:

a control detection module, used for acquiring the post-frequency division control signal of the phase-locked loop, and judging whether the post-frequency division control signal changes;

The state detection module is used to obtain the input signal and feedback signal of the phase-locked loop when the post-frequency division control signal changes, and determine the current state of the phase-locked loop according to the input signal and the feedback signal, and the The state of the phase-locked loop includes a locked state and an unlocked state;

The safety frequency reduction module is used to perform frequency reduction processing on the output signal of the phase-locked loop when the current state is the loss-of-lock state, and use the frequency-reduced signal as the clock signal; when the current state is the locked state, directly convert the The output signal of the phase-locked loop is used as the clock signal.

Preferably, the control and detection module includes a third delay device and an OR gate, wherein the input end of the third delay device is connected to the control end of the post-frequency divider for inputting the post-frequency divider control signal, the output end of the third delay device is connected to the first input end of the XOR gate, the second input end of the XOR gate is connected to the control end of the post-frequency divider, the XOR gate The output end is connected to the state detection module.

Preferably, the state detection module includes: a first delay device, a second delay device, a first D flip-flop, a second D flip-flop and an AND gate, wherein the input end of the first delay device is connected to The input terminal of the phase-locked loop is used to input the input signal of the phase-locked loop, the output terminal of the first delay device is connected to the clock terminal of the first D flip-flop, and the data input of the first D flip-flop is The terminal is connected to the feedback terminal of the phase-locked loop for inputting the feedback signal of the phase-locked loop, the data output terminal of the first D flip-flop is connected to the first input terminal of the AND gate; The input end is connected to the feedback end of the phase-locked loop for inputting the feedback signal of the phase-locked loop, the output end of the second delay device is connected to the clock end of the second D flip-flop, the second D flip-flop The data input end of the second D flip-flop is connected to the input end of the phase-locked loop for inputting the input signal of the phase-locked loop, the data output end of the second D flip-flop is connected to the second input end of the AND gate, the The output terminal is used for outputting a state signal, and the reset terminals of the first D flip-flop and the second D flip-flop are respectively connected to the output terminal of the XOR gate. Preferably, the safety frequency reduction module includes a frequency reduction device and a switch, and the input terminal of the frequency reduction device and the first input terminal of the switch switch are both connected to the output terminal of the phase-locked loop for inputting the phase-locked loop. The output signal of the loop, the output terminal of the frequency reduction device is connected to the second input terminal of the switch, the control terminal of the switch switch is connected to the output terminal of the AND gate, and the output terminal of the switch switch is used for output clock signal.

Preferably, it also includes:

The frequency reduction control module is used to obtain the frequency division coefficient changed by the loop frequency divider according to the loop frequency division control signal of the phase-locked loop when the post frequency division control signal changes, and according to the loop frequency divider The frequency division coefficient before the change and the frequency division coefficient after the change determine the frequency reduction coefficient of the frequency reduction device, and the frequency reduction coefficient of the frequency reduction device satisfies the following conditions:

N(safdiv)≥N(lpdiv)/N(lpdiv_new),

Wherein, N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the frequency division coefficient before the loop frequency divider is changed, and N(lpdiv_new) is the frequency division coefficient after the loop frequency divider is changed .

The present invention also constructs a clock generation device, comprising a phase-locked loop, the phase-locked loop comprising a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop frequency divider and a post-frequency divider, characterized in that: The clock generating apparatus further includes the above-mentioned circuit for preventing clock overshoot.

Implementing the technical scheme of the present invention, when adjusting the frequency of the phase-locked loop output signal by changing the frequency division coefficients of the loop frequency divider and the post-frequency divider, if it is detected that the frequency-division coefficient of the post-frequency divider is changed, it can be adjusted. According to the input signal and the feedback signal, it is judged whether it is currently in an out-of-lock state or in a locked state, and in the out-of-lock state, the output signal of the phase-locked loop is frequency-reduced to eliminate the risk of overshoot. Once it is judged that it is in the locked state, the stable target frequency signal is output. Therefore, each frequency switching time is self-adaptive and the shortest in the system. Moreover, during the switching period, the highest-speed safe clock currently available can be provided to the system at zero cost, and the processing power of the CPU can be used to achieve the highest speed. , Run subsequent software programs at a safe frequency. Therefore, compared with the prior art, a usable clock can be provided at a lower cost, more reliably, and faster, the software running efficiency can be improved, and power consumption can be saved.

Description of drawings

In order to illustrate the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, which are common in the art. As far as technical personnel are concerned, other drawings can also be obtained based on these drawings without any creative effort. In the attached picture:

Fig. 1 is the logical structure diagram of a kind of phase-locked loop of the prior art;

Fig. 2 is the simulation diagram of clock signal and time in the process of re-locking of the phase-locked loop in Fig. 1;

3 is a flowchart of Embodiment 1 of the method for preventing clock overshoot according to the present invention;

Fig. 4 is the simulation diagram of clock signal and time in the process of relocking after adopting the method in Fig. 3;

FIG. 5 is a logical structure diagram of Embodiment 1 of the clock generating apparatus of the present invention;

Fig. 6 is the logical structure diagram of the first embodiment of the control detection module in Fig. 5;

Fig. 7 is the logical structure diagram of the first embodiment of the state detection module in Fig. 5;

Fig. 8 is the logical structure diagram of the second embodiment of the state detection module in Fig. 5;

Fig. 9 is the logical structure diagram of the third embodiment of the state detection module in Fig. 5;

Fig. 10 is the logical structure diagram of the fourth embodiment of the state detection module in Fig. 5;

Fig. 11 is the logical structure diagram of the fifth embodiment of the state detection module in Fig. 5;

FIG. 12 is a logical structural diagram of Embodiment 1 of the safety frequency reduction module in FIG. 5 .

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The specific implementations/examples described herein are specific implementations of the present invention, and are used to illustrate the concept of the present invention. They are all illustrative and exemplary, and should not be construed as limiting the implementation of the present invention and the scope of the present invention. limit. In addition to the embodiments described herein, those skilled in the art can also adopt other obvious technical solutions based on the contents disclosed in the claims and the description of the present application, and these technical solutions include any obvious technical solutions to the embodiments described herein. The technical solutions of replacement and modification are all within the protection scope of the present invention.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict.

3 is a flowchart of Embodiment 1 of the method for preventing clock overshoot according to the present invention. The method of this embodiment is applied to a phase-locked loop with post-frequency division. The phase-locked loop includes a phase detector, a low-pass filter, a voltage controlled oscillator, loop divider and postscaler. In this embodiment, when changing the frequency of the phase-locked loop output signal by changing the frequency dividing coefficient of the loop frequency divider and the frequency dividing coefficient of the post-frequency divider, the following steps are performed:

Step S10. Obtain the post-frequency division control signal of the phase-locked loop, and determine whether the post-frequency division control signal changes;

In this step, if a change in the post-frequency division control signal is monitored, a simple pulse signal can be sent out.

Step S20. When the post-frequency division control signal changes, obtain the input signal and the feedback signal of the phase-locked loop, and determine the current state of the phase-locked loop according to the input signal and the feedback signal, and the phase-locked loop The state includes locked state and unlocked state;

In this step, it should be noted first that when the phase-locked loop is in a locked state, the rising edges of the input signal and the feedback signal are aligned (the phase difference is constant). When the frequency division coefficient of the loop frequency divider is changed, the feedback signal of the phase-locked loop will change. in an out-of-lock state.

Step S30. When the current state is an out-of-lock state, down-frequency processing is performed on the output signal of the phase-locked loop, and the down-frequency processed signal is used as a clock signal;

In this step, since overshoot will occur in the phase-locked loop in the out-of-lock state, the output signal of the phase-locked loop in the out-of-lock state can be down-frequency processed, that is, the damped oscillation frequency is forcibly reduced, and then used as clock signal to reduce the risk of overshoot.

Step S30. When the current state is the locked state, the output signal of the phase-locked loop is directly used as the clock signal.

Combining with Figure 4, first, assuming that the frequency of the input signal of the phase-locked loop is 12.5MHz, the clock generation relationship is: Fout=[N(lpdiv)/N(pstdiv)]*Fin, the system requires the clock to be increased from 375MHz to 387.5MHz, and the frequency The switching is achieved by changing the frequency division coefficients of the loop divider and the post divider: before switching, the frequency division coefficient of the loop divider is 60, and the frequency division coefficient of the post divider is 2; The division factor of the loop divider becomes 31, and the division factor of the post divider becomes 1. It can be seen from the figure that in the loss-of-lock state, the original overshoot frequency of 750MHz does not appear due to the frequency reduction of the output signal. Moreover, the output frequency of the phase-locked loop is 387.5MHz after re-stabilization output signal.

Implementing the technical solution of this embodiment, when adjusting the frequency of the phase-locked loop output signal by changing the frequency division coefficients of the loop frequency divider and the post frequency divider, if it is detected that the frequency division coefficient of the post frequency divider changes, then According to the input signal and the feedback signal, it can be judged whether it is currently in an out-of-lock state or in a locked state, and in the out-of-lock state, the output signal of the phase-locked loop is frequency-reduced to eliminate the risk of overshoot. Once it is judged that it is in the locked state, the stable target frequency signal is output. Therefore, each frequency switching time is self-adaptive and the shortest in the system. Moreover, during the switching period, the highest-speed safe clock currently available can be provided to the system at zero cost, and the processing power of the CPU can be used to achieve the highest speed. , Run subsequent software programs at a safe frequency. Therefore, compared with the prior art, a usable clock can be provided at a lower cost, more reliably, and faster, the software running efficiency can be improved, and power consumption can be saved.

In an optional embodiment, step S10 is: acquiring the post-frequency division control signal and the loop frequency division control signal of the phase-locked loop, and judging whether the post-frequency division control signal and the loop frequency division control signal occur Variety. In this embodiment, the post-frequency division control signal and the loop frequency division control signal can be obtained at the same time, and it is determined whether these two signals change, because in general, the post-frequency division control signal and the loop frequency division control signal are at the same time dispatched. Of course, in other embodiments, only the post-frequency division control signal may be acquired and detected, because even if the loop frequency division control signal is not captured, it can be determined by detecting the input signal and the feedback signal of the phase-locked loop in step S20. Whether the loop frequency division control signal changes.

In an optional embodiment, in step S20, the current state of the phase-locked loop may be determined according to the following methods: comparing the input signal with the feedback signal, and judging whether the difference between the two is less than a threshold; if preset If the difference between the two during the period is less than the threshold, the current state of the phase-locked loop is determined to be the locked state; if the difference between the two within the preset time period is not less than the threshold, the current state of the phase-locked loop is determined to be the out-of-lock state.

It should be noted that the determination of the threshold is related to the characteristics of the PLL and the requirements for locking accuracy, etc., and can be set as required, for example, one clock cycle of the oscillator.

In an optional embodiment, in step S30, frequency reduction processing may be performed in the following manner: frequency reduction processing is performed on the output signal of the phase-locked loop by a frequency reduction device, and the following conditions are met:

N(safdiv)≥N(lpdiv)/N(lpdiv_new),

Wherein, N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the frequency division coefficient before the loop frequency divider is changed, and N(lpdiv_new) is the frequency division coefficient after the loop frequency divider is changed .

In this embodiment, due to the existence of the post-frequency divider in the phase-locked loop, according to Fout=[N(lpdiv)/N(pstdiv)]*Fin, where Fin is the frequency of the input signal of the phase-locked loop, and Fout is The frequency of the output signal of the phase-locked loop, N(lpdiv) is the frequency division coefficient of the loop frequency divider, and N(pstdiv) is the frequency division coefficient of the post-frequency divider. When the frequency division coefficient of the post-scaler is adjusted to N(pstdiv_new), the output frequency Fosc of the voltage-controlled oscillator does not change immediately, and is still Fosc=N(lpdiv)*Fin. Therefore, the frequency of the output signal changes instantaneously as Fout_over=[N(lpdiv)/N(pstdiv_new)]*Fin, and the ratio of the overshoot frequency to the final output frequency is K=Fout_over/Fout_new=N(lpdiv)/N(lpdiv_new) . When the frequency reduction coefficient N (safdiv) is greater than or equal to K, there is just no overshoot. Since the numerical range of the frequency division coefficient of the loop frequency divider is different each time it is switched, the corresponding K value can be calculated each time. Of course, the K value can also be simply set as: lpdiv(max)/ lpdiv(min).

In addition, it should be noted that for a phase-locked loop with post-frequency division, if the frequency of the output signal is changed only by changing the frequency-division coefficient of its loop frequency divider, that is, the frequency-division coefficient of the post-frequency divider does not In theory, the frequency of the output signal should be reduced by X times. According to the actual circuit, the conventional overshoot will only be between 10% and 20%. Therefore, it is only necessary to set X greater than 1.1 to eliminate the risk of overshoot. Preferably, X can be selected as 1.5. Therefore, for a phase-locked loop with post-frequency division, if some application scenarios require it to change the frequency of the output signal only by changing the frequency division coefficient of its loop divider, while other application scenarios require it to change the frequency of its loop simultaneously The frequency division coefficient of the frequency divider and the post-frequency divider is used to change the frequency of the output signal. As for the frequency reduction coefficient N (safdiv) of the frequency reduction device, it is only necessary to ensure that it is greater than the larger of X and K.

FIG. 5 is a logical structure diagram of Embodiment 1 of the clock generation apparatus of the present invention. The clock generation apparatus of this embodiment includes a phase-locked loop 10 and a circuit for preventing clock overshoot. The phase-locked loop 10 is a phase-locked loop with post-frequency division, and specifically includes a phase detector 11, a low-pass filter 12, a voltage-controlled oscillator 13, a loop frequency divider 14 and a post-frequency divider 15, It should be understood that the functions, specific implementations and logical relationships of the phase detector 11, the low-pass filter 12, the voltage-controlled oscillator 13, the loop frequency divider 14 and the post-frequency divider 15 in the phase-locked loop 10 can be adopted in the art The known practice is not repeated here. The circuit for preventing clock overshoot specifically includes a control detection module 40, a state detection module 20 and a safety frequency reduction module 30, and the control detection module 40 is used to obtain the post-frequency division control signal of the phase-locked loop, and determine the post-frequency division. Whether the control signal has changed; the state detection module 20 is used to obtain the input signal and feedback signal of the phase-locked loop when the post-frequency division control signal changes, and determine the phase-locked loop according to the input signal and the feedback signal The current state of the phase-locked loop includes a locked state and an out-of-lock state; the safety frequency reduction module 30 is used to reduce the frequency of the output signal of the phase-locked loop when the current state is an out-of-lock state, and reduce the frequency The frequency-processed signal is used as the clock signal; when the current state is the locked state, the output signal of the phase-locked loop is directly used as the clock signal.

In this embodiment, with reference to FIG. 5 , the control detection module 40 receives the post-divider control signal REG_POST; if a change in the signal is detected, it sends a signal to the state detection module 20, such as a simple pulse signal, the state The detection module 20 compares the input signal Fin with the feedback clock Fback, and outputs a status signal LCK according to the difference between the two. For example, LCK 0 represents a lock-out state, and LCK 1 represents a lock state. The safety frequency reduction module 30 determines whether to perform frequency reduction processing on the output signal of the post-scaler 15 according to the lock state signal LCK, and directly outputs the output signal of the post-scaler 15 after re-locking.

In an optional embodiment, the state detection module 20 is configured to compare the input signal with the feedback signal, and determine whether the difference between the two is less than a threshold. That is, if the requirement has been met within a certain period of time, it means locking. At this time, the current state of the phase-locked loop is determined to be the locked state; if the difference between the two within the preset period is not less than the threshold, it is determined that the current state of the phase-locked loop is out of lock. state.

In an optional embodiment, referring to FIG. 6 , the control detection module includes a third delay device 41 and an OR gate 42 , wherein the input end of the third delay device 41 is connected to the control end of the post-scaler, so as to use In the input post-frequency division control signal REG_POST, the output end of the third delay device 41 is connected to the first input end of the XOR gate 42, the second input end of the XOR gate 42 is connected to the control end of the post-frequency divider, and the XOR gate The output terminal of 42 is used to output the reset signal Rst, and is connected to the state detection module. In this embodiment, as long as the post-frequency division control signal REG_POST changes, the XOR gate 42 will generate a negative pulse with a time width equal to the delay time of the third delay device 42 .

In an optional embodiment, with reference to FIG. 7 , the state detection module of this embodiment is implemented by a cross-delayed latch structure. Specifically, the state detection module includes: a first delay device 21 , a second delay device 22. The first D flip-flop 23, the second D flip-flop 24 and the AND gate 25. Regarding the first delayer 21 and the second delayer 22, it should be noted that the delay time should be greater than the delay time of the D flip-flop. The settling time is smaller than the period of the output signal. In practical applications, the delay time of the two delay devices can be designed within a reasonable range. In this embodiment, the input end of the first delay device 21 is connected to the input end of the phase-locked loop for inputting the input signal Fin of the phase-locked loop, and the output end of the first delay device 21 is connected to the first D flip-flop The clock terminal of 23, the data input terminal of the first D flip-flop 23 is connected to the feedback terminal of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop, and the data output terminal of the first D flip-flop 23 is connected to the AND gate 25. The first input end; the input end of the second delay device 22 is connected to the feedback end of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop, and the output end of the second delay device 22 is connected to the second D flip-flop 24 The clock terminal of the second D flip-flop 24 is connected to the input terminal of the phase-locked loop for inputting the input signal Fin of the phase-locked loop, and the data output terminal of the second D flip-flop 24 is connected to the first terminal of the AND gate 25. Two input terminals, the output terminal of the AND gate 25 is used for outputting the status signal LCK, and the reset terminals of the first D flip-flop 23 and the second D flip-flop 24 are respectively connected to the output terminal of the AND gate 42 for inputting the reset signal.

It should be noted that the connection relationship in this application includes, but is not limited to, the connection relationship between the two input ends based on receiving the same input signal, the connection relationship between the output end and the input end, and the like.

The state detection process of the phase-locked loop is described below in conjunction with Figure 5-7: the rising edge of the input signal Fin and the feedback signal Fback of the phase-locked loop are aligned during the locking period (the phase difference is constant), and the rising edge of either side can be delayed. When the high level of the other side is obtained, the output signals of the two D flip-flops 23 and 24 are always 1. When the frequency division coefficient of the postscaler is changed, that is, when the postscaler control signal is changed, the two D flip-flops 23, 24 are reset briefly below, and then, since the frequency division coefficient of the loop divider is changed, so , the output signal Fback of the phase-locked loop changes, and its new rising edge will differ from the input signal Fin by one or more cycles of the output signal Fosc. If the output frequency of the phase-locked loop is increased, that is, the frequency division coefficient is increased (for example, from N to N+K), then Fback will be delayed by K cycles compared to Fin. At this time, the first D flip-flop 23 will output 0, thereby The LCK signal output from the AND gate 25 is made 0, that is, an unlock signal is issued. Then, the output signal Fosc is gradually accelerated under the action of the loop until overshoot occurs. At this time, the edge of the feedback signal Fback will lead the edge of the input signal Fin, and the second D flip-flop 24 will output 0 again, thus making the AND gate 25 The LCK signal that continues to output is 0. Only when the edges of the feedback signal Fback and the input signal Fin are realigned within a certain range, the two D flip-flops 23 and 24 output 1 again, so that the LCK signal output by the AND gate is 1, that is, a lock signal is issued.

In an optional embodiment, referring to FIG. 8 , the state detection module of this embodiment includes: an XOR gate 221 , a pulse phagocytosis module 222 and an inverter 223 , and the first input terminal of the XOR gate 221 is used for input The input signal Fin of the phase-locked loop, the second input terminal of the XOR gate 221 is used to input the feedback signal Fback of the phase-locked loop, and the output terminal of the XOR gate 221 is connected to the pulse phagocytosis module 222 The input end of the pulse phagocytosis module 222 is connected to the input end of the inverter 223, and the output end of the inverter 223 is connected to the control end of the safety frequency reduction module 30, for A status signal LCK is output to the safe frequency reduction module 30 .

In an optional embodiment, referring to FIG. 9 , the state detection module of this embodiment includes: an exclusive OR gate 231 , a resistor R1 , a capacitor C1 and an inverter 232 , and the first input terminal of the exclusive OR gate 231 is used for Input the input signal Fin of the phase-locked loop, the second input terminal of the XOR gate 231 is used to input the feedback signal Fback of the phase-locked loop, and the output terminal of the XOR gate 231 is connected to the resistance R1. one end of the resistor R1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1 and the input end of the inverter 232, the other end of the capacitor C1 is grounded, and the output end of the inverter 232 is connected to the The control terminal of the safety frequency reduction module 30 is connected to output a status signal LCK to the safety frequency reduction module 30 .

In an optional embodiment, referring to FIG. 10 , the state detection module of this embodiment includes: an XOR gate 241 , a delay unit 242 , an AND gate 243 and an inverter 244 , the first input of the XOR gate 241 is The terminal is used to input the input signal Fin of the phase-locked loop, the second input terminal of the XOR gate 241 is used to input the feedback signal Fback of the phase-locked loop, and the output terminals of the XOR gate 241 are respectively connected to the The input of the delay unit 242 is connected to the first input of the AND gate 243, the output of the delay unit 242 is connected to the second input of the AND gate 243, and the output of the AND gate 243 The terminal is connected to the input terminal of the inverter 244 , and the output terminal of the inverter 244 is connected to the control terminal of the safety frequency reduction module 30 for outputting the status signal LCK to the safety frequency reduction module 30 .

In an optional embodiment, referring to FIG. 11 , the state detection module of this embodiment includes: an exclusive OR gate 251 , a PMOS transistor M1 , an NMOS transistor M2 , a capacitor C2 and a delay unit 252 . An input terminal is used to input the input signal Fin of the phase-locked loop, the second input terminal of the XOR gate 251 is used to input the feedback signal Fback of the phase-locked loop, and the output terminals of the XOR gate 251 are respectively It is connected to the gates of the PMOS transistor M1 and the NMOS transistor M2, the source of the PMOS transistor M1 is respectively connected to the power supply terminal and one end of the capacitor C2, and a constant current is connected between the source of the NMOS transistor M2 and the ground. source, after the drains of the PMOS transistor M1 and the NMOS transistor M2 are connected, they are respectively connected to the other end of the capacitor C2 and the input end of the delay unit 252, and the output end of the delay unit 252 is used as the output end of the state detection module. The output terminal is connected to the control terminal of the safety frequency reduction module, and is used for outputting the status signal LCK to the safety frequency reduction module. The delay unit 252 may be implemented by a cache. In this embodiment, optionally, the delay unit 252 can be omitted, that is, the drain of the PMOS transistor M1, the drain of the NMOS transistor M2 and the other end of the capacitor C2 are connected as the output end of the state detection module , for outputting the status signal LCK to the safety frequency reduction module.

In an optional embodiment, with reference to FIG. 12 , the safety frequency reduction module of this embodiment includes a frequency reduction device 31 and a switch 32 , wherein the input terminal of the frequency reduction device 31 and the first input terminal of the switch switch 32 are both connected The output terminal of the phase-locked loop is used to input the output signal of the phase-locked loop, that is, the output signal Fpst of the post-frequency divider, and the output terminal of the frequency reduction device 31 is connected to the second input terminal of the switch 32. The control terminal is connected to the output terminal of the AND gate 25, and the output terminal of the switch 32 is used for outputting the clock signal Fout.

Further, the circuit for preventing clock overshoot of the present invention may further include a frequency reduction control module, and the frequency reduction control module is used to divide the frequency of the control signal according to the loop frequency of the phase-locked loop when the post-frequency division control signal changes. Obtain the frequency division coefficient after the loop frequency divider is changed, and determine the frequency reduction coefficient of the frequency reduction device according to the frequency division coefficient before the loop frequency divider is changed and the frequency division coefficient after the change, and the frequency reduction The frequency reduction factor of the device meets the following conditions:

N(safdiv)≥N(lpdiv)/N(lpdiv_new),

Wherein, N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the frequency division coefficient before the loop frequency divider is changed, and N(lpdiv_new) is the frequency division coefficient after the loop frequency divider is changed .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims (10)

1. A method of preventing clock overshoot, applied in a phase locked loop with postdivider, said phase locked loop comprising a phase detector, a low pass filter, a voltage controlled oscillator, a loop divider and a postdivider, characterized in that, when changing the frequency of the output signal of the phase locked loop by changing the division factor of the loop divider and the division factor of the postdivider, the following steps are performed:

acquiring a post-frequency-division control signal of a phase-locked loop, and judging whether the post-frequency-division control signal changes;

when the post-frequency-division control signal changes, acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;

when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal;

when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.

2. The method of claim 1, wherein obtaining a post-divide control signal of a phase-locked loop and determining whether the post-divide control signal changes comprises:

and acquiring a post-frequency-division control signal and a loop-frequency-division control signal of the phase-locked loop, and judging whether the post-frequency-division control signal and the loop-frequency-division control signal are changed.

3. The method of claim 1, wherein determining the current state of the phase locked loop based on the input signal and the feedback signal comprises:

comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value;

if the difference between the two is smaller than the threshold value within the preset time period, determining that the current state of the phase-locked loop is a locked state;

and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.

4. The method of claim 1, wherein down-converting the output signal of the phase-locked loop comprises:

the output signal of the phase-locked loop is subjected to frequency reduction processing by a frequency reduction device, and the following conditions are met:

N(safdiv)≥N(lpdiv)/N(lpdiv_new)，

wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.

5. A circuit for preventing clock overshoot, for use in a phase locked loop with postdivider, the phase locked loop including a phase detector, a low pass filter, a voltage controlled oscillator, a loop divider, and a postdivider, the circuit comprising:

the control detection module is used for acquiring a post-frequency-division control signal of the phase-locked loop and judging whether the post-frequency-division control signal changes;

the state detection module is used for acquiring an input signal and a feedback signal of the phase-locked loop when the post-frequency-division control signal changes, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;

the safety frequency reduction module is used for performing frequency reduction processing on an output signal of the phase-locked loop when the current state is an unlocked state, and taking the signal subjected to the frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.

6. The circuit of claim 5, wherein the control detection module comprises a third delay and an exclusive-nor gate, wherein an input terminal of the third delay is connected to the control terminal of the postscaler for inputting a postscaler control signal, an output terminal of the third delay is connected to the first input terminal of the exclusive-nor gate, a second input terminal of the exclusive-nor gate is connected to the control terminal of the postscaler, and an output terminal of the exclusive-nor gate is connected to the state detection module.

7. The circuit of claim 6, wherein the state detection module comprises: the phase-locked loop comprises a first delayer, a second delayer, a first D trigger, a second D trigger and an AND gate, wherein the input end of the first delayer is connected with the input end of a phase-locked loop so as to be used for inputting an input signal of the phase-locked loop, the output end of the first delayer is connected with the clock end of the first D trigger, the data input end of the first D trigger is connected with the feedback end of the phase-locked loop so as to be used for inputting a feedback signal of the phase-locked loop, and the data output end of the first D trigger is connected with the first input end of the AND gate; the input end of the second time delay is connected with the feedback end of the phase-locked loop so as to input a feedback signal of the phase-locked loop, the output end of the second time delay is connected with the clock end of the second D trigger, the data input end of the second D trigger is connected with the input end of the phase-locked loop so as to input an input signal of the phase-locked loop, the data output end of the second D trigger is connected with the second input end of the AND gate, the output end of the AND gate is used for outputting a state signal, and the reset ends of the first D trigger and the second D trigger are respectively connected with the output end of the AND gate.

8. The circuit for preventing clock overshoot according to claim 7, wherein the safety down-conversion module comprises a down-conversion device and a switch, an input terminal of the down-conversion device and a first input terminal of the switch are both connected to an output terminal of the phase-locked loop for inputting the output signal of the phase-locked loop, an output terminal of the down-conversion device is connected to a second input terminal of the switch, a control terminal of the switch is connected to an output terminal of the and gate, and an output terminal of the switch is used for outputting the clock signal.

9. The circuit of claim 8, further comprising:

the frequency reduction control module is used for acquiring the frequency division coefficient after the change of the loop frequency divider according to the loop frequency division control signal of the phase-locked loop when the post-frequency division control signal changes, and determining the frequency reduction coefficient of the frequency reduction device according to the frequency division coefficient before the change of the loop frequency divider and the frequency division coefficient after the change, wherein the frequency reduction coefficient of the frequency reduction device meets the following conditions:

N(safdiv)≥N(lpdiv)/N(lpdiv_new)，

wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.

10. A clock generation arrangement comprising a phase locked loop comprising a phase detector, a low pass filter, a voltage controlled oscillator, a loop divider and a post divider, characterized in that the clock generation arrangement further comprises a circuit for preventing clock overshoots as claimed in any of the claims 5-9.

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