CN111384947A - Method, circuit and clock generating device for preventing clock overshoot - Google Patents
Method, circuit and clock generating device for preventing clock overshoot Download PDFInfo
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Abstract
The invention relates to a method, a circuit and a clock generation device for preventing clock overshoot, wherein the method for preventing clock overshoot comprises the following steps: acquiring a post-frequency-division control signal of a phase-locked loop, and judging whether the post-frequency-division control signal changes; when the post-frequency-division control signal changes, acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state; when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal. By implementing the technical scheme of the invention, the available clock can be provided more reliably and quickly at lower cost, the software running efficiency can be improved, and the power consumption can be saved.
Description
Technical Field
The present invention relates to the field of phase-locked loops, and in particular, to a method, a circuit, and a clock generating apparatus for preventing clock overshoot.
Background
The Phase-Locked Loop is a feedback control circuit, and is called a Phase-Locked Loop (PLL). He uses an externally input reference signal to control the frequency and phase of the oscillating signal inside the loop. In the process of processing electronic signals, the phase-locked loop can realize automatic tracking of the frequency of an output signal to the frequency of an input signal, so the phase-locked loop is widely applied to a closed-loop tracking circuit. In the field of clocks, clock phase-locked loops are widely used for clock generation.
As shown in fig. 1, a clock phase-locked loop generally consists of several parts: phase discriminator PD, loop filter LPF, voltage controlled oscillator VCO, loop frequency divider LPDIV and back frequency divider PSTDIV, this back frequency divider PSTDIV can let the clock output range more extensive, or reduce voltage controlled oscillator VCO's working range by a wide margin, consequently can reduce the design degree of difficulty, improve the reliability.
The phase detector PD is a unit that performs phase comparison. The function of which is to compare the phase difference between the input signal Fin and the feedback signal Fback. Its output voltage is proportional to the phase difference between the two input signals.
The low pass filter LPF is an active or passive low pass filter. The function of the phase discriminator is to filter out high-frequency components (including mixing frequency and other high-frequency noises) in the output voltage of the phase discriminator, play a role of smoothing filtering, and finally output a control signal Vc. Usually consisting of a resistor, a capacitor, an inductor, or the like, and sometimes including an operational amplifier.
The VCO is an oscillator whose oscillation frequency is controlled by a control voltage, and the oscillation frequency of the oscillator is linearly related to the control voltage. The oscillator VCO outputs a corresponding oscillation frequency Fosc according to the control signal Vc.
The loop divider LPDIV determines the multiplying factor of the input and oscillation clocks, but may be an integer or a decimal. The relationship is Fosc ═ n (lpdiv) × Fin.
The post-divider PSTDIV re-determines how much Fosc needs to be adjusted and then outputs the adjusted post-divider PSTDIV, which may be an integer or a decimal, and the final clock output Fout [ [ n (lpduv)/n (PSTDIV) ] ] Fin.
Generally, after the PLL clock is locked, the phase difference between the feedback clock and the input clock is stable, and therefore a stable clock can be output. When we want to change the output frequency Fout of the PLL, only the frequency division coefficient REG _ LOOP corresponding to the LOOP frequency divider and the frequency division coefficient REG _ POST corresponding to the POST frequency divider need to be changed.
The VCO is a second-order nonlinear differential equation, so that if the low-pass filter LPF is first-order, the phase-locked loop VCO can be regarded as a second-order system from the system perspective, the natural frequency omega n and the damping coefficient ξ exist for the second-order system, if parameters in the system are suddenly changed, intrinsic damping oscillation occurs according to the characteristics of the system, under the same LPF condition, the higher the VCO sensitivity is, the smaller ξ the faster the locking is, but the larger the amplitude of the damping oscillation is, the smaller the amplitude of the damping oscillation is, the larger the ξ the larger the damping oscillation is, the larger the locking time is, and the longer the locking time is, because the damping factor cannot be accurately controlled, the PLL generally needs to be locked as soon as possible, and therefore the output of the damping oscillation with a certain amplitude exists.
When the system changes the frequency dividing ratio, the PLL needs to be locked again, and the locking action needs a certain time. In general, a PLL has its second order response characteristic in the lock range characterized by a damping factor. The locking is fast, the damping factor is small, and large overshoot occurs; even with the usual damping factor of 0.45 to 0.7, there is still some degree of overshoot.
Theoretically and practically, the conventional overshoot is not much larger, e.g. 10% -20%. It is not too problematic if the system provides sufficient safety margin.
The postdivider has a very distinct feature: since the output Fout is not in the loop and does not have the loop bandwidth characteristic of a second-order system, the relative output Fout is an impulse type instant response, so that the output is directly influenced, and a serious overshoot problem is caused in many cases.
In connection with fig. 2, assume: input clock 12.5MHz, clock generation relationship: fout [ n (lpdiv))/n (pstdiv)) ] Fin, the system requires the clock to be increased from 375MHz to 387.5MHz, only 12.5MHz is needed, and the frequency switching is realized by changing the frequency division coefficients of the loop frequency divider and the post frequency divider: before switching, the loop frequency division coefficient is 60, and the back frequency division coefficient is 2; after switching, the loop division factor becomes 31 and the post division factor becomes 1. In the process of frequency switching, the frequency of the Fosc can only be gradually changed through a loop, a loop filter has a fixed bandwidth, and the Vc controls the oscillator to gradually change from 750MHz to 387.5 MHz; then the division factor can be changed from 2 to 1 instantly, which causes Fout to be changed from 375MHz to 750MHz directly, thus causing serious overshoot, and the system is stabilized to 387.5MHz after a long time of huge overshoot. If the latter stage CPU cannot operate at such a high frequency, for example, it can only operate at a frequency of 500MHz at most, it will directly cause a crash.
If the CPU is at 1V and the highest operating frequency is only 500MHz (although there is already a very large margin for 375 MHz), then the overshoot frequency 750MH of the above PLL will inevitably cause system errors. In order to prevent the system from collapsing, the voltage needs to be adjusted high. However, in many cases, even if the voltage is increased, the CPU operating speed cannot be increased all the time, for example, cannot be increased by 100%.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method, a circuit and a clock generation apparatus for preventing clock overshoot, which can reduce the overshoot risk, aiming at the defect that the overshoot occurs when the PLL output clock is adjusted by changing the frequency division coefficients of the loop frequency divider and the post frequency divider in the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: a method for preventing clock overshoot is constructed and applied to a phase-locked loop with post-frequency division, wherein the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator, a loop frequency divider and a post-frequency divider, and when the frequency of an output signal of the phase-locked loop is changed by changing the frequency division coefficient of the loop frequency divider and the frequency division coefficient of the post-frequency divider, the following steps are carried out:
acquiring a post-frequency-division control signal of a phase-locked loop, and judging whether the post-frequency-division control signal changes;
when the post-frequency-division control signal changes, acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal;
when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
Preferably, the obtaining a post-frequency division control signal of the phase-locked loop, and determining whether the post-frequency division control signal changes includes:
and acquiring a post-frequency-division control signal and a loop-frequency-division control signal of the phase-locked loop, and judging whether the post-frequency-division control signal and the loop-frequency-division control signal are changed.
Preferably, determining the current state of the phase-locked loop according to the input signal and the feedback signal comprises:
comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value;
if the difference between the two is smaller than the threshold value within the preset time period, determining that the current state of the phase-locked loop is a locked state;
and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
Preferably, the down-converting the output signal of the phase-locked loop includes:
the output signal of the phase-locked loop is subjected to frequency reduction processing by a frequency reduction device, and the following conditions are met:
N(safdiv)≥N(lpdiv)/N(lpdiv_new)，
wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.
The invention also constructs a circuit for preventing clock overshoot, which is applied in a phase-locked loop with post-division, wherein the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator, a loop frequency divider and a post-divider, and the circuit for preventing clock overshoot comprises:
the control detection module is used for acquiring a post-frequency-division control signal of the phase-locked loop and judging whether the post-frequency-division control signal changes;
the state detection module is used for acquiring an input signal and a feedback signal of the phase-locked loop when the post-frequency-division control signal changes, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
the safety frequency reduction module is used for performing frequency reduction processing on an output signal of the phase-locked loop when the current state is an unlocked state, and taking the signal subjected to the frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
Preferably, the control detection module includes a third delay and an exclusive nor gate, wherein an input end of the third delay is connected to the control end of the post-divider for inputting a post-division control signal, an output end of the third delay is connected to the first input end of the exclusive nor gate, a second input end of the exclusive nor gate is connected to the control end of the post-divider, and an output end of the exclusive nor gate is connected to the state detection module.
Preferably, the state detection module includes: the phase-locked loop comprises a first delayer, a second delayer, a first D trigger, a second D trigger and an AND gate, wherein the input end of the first delayer is connected with the input end of a phase-locked loop so as to be used for inputting an input signal of the phase-locked loop, the output end of the first delayer is connected with the clock end of the first D trigger, the data input end of the first D trigger is connected with the feedback end of the phase-locked loop so as to be used for inputting a feedback signal of the phase-locked loop, and the data output end of the first D trigger is connected with the first input end of the AND gate; the input end of the second time delay is connected with the feedback end of the phase-locked loop so as to input a feedback signal of the phase-locked loop, the output end of the second time delay is connected with the clock end of the second D trigger, the data input end of the second D trigger is connected with the input end of the phase-locked loop so as to input an input signal of the phase-locked loop, the data output end of the second D trigger is connected with the second input end of the AND gate, the output end of the AND gate is used for outputting a state signal, and the reset ends of the first D trigger and the second D trigger are respectively connected with the output end of the AND gate. Preferably, the safety frequency-reducing module comprises a frequency-reducing device and a switch, an input end of the frequency-reducing device and a first input end of the switch are both connected with an output end of the phase-locked loop for inputting an output signal of the phase-locked loop, an output end of the frequency-reducing device is connected with a second input end of the switch, a control end of the switch is connected with an output end of the and gate, and an output end of the switch is used for outputting a clock signal.
Preferably, the method further comprises the following steps:
the frequency reduction control module is used for acquiring the frequency division coefficient after the change of the loop frequency divider according to the loop frequency division control signal of the phase-locked loop when the post-frequency division control signal changes, and determining the frequency reduction coefficient of the frequency reduction device according to the frequency division coefficient before the change of the loop frequency divider and the frequency division coefficient after the change, wherein the frequency reduction coefficient of the frequency reduction device meets the following conditions:
N(safdiv)≥N(lpdiv)/N(lpdiv_new)，
wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.
The invention also constructs a clock generating device, which comprises a phase-locked loop, wherein the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator, a loop frequency divider and a post-divider.
By implementing the technical scheme of the invention, when the frequency of the output signal of the phase-locked loop is adjusted by changing the frequency division coefficients of the loop frequency divider and the post frequency divider, if the change of the frequency division coefficient of the post frequency divider is detected, the current state of the phase-locked loop can be judged to be in the unlocked state or the locked state according to the input signal and the feedback signal, and the output signal of the phase-locked loop is subjected to frequency reduction treatment in the unlocked state so as to eliminate the risk of overshoot. Once it is judged that the lock state is present, the target frequency signal that has been stabilized is output. Therefore, each frequency switching time is self-adaptive and the system is shortest, and the highest-speed safe clock which can be provided currently can be provided to the system at zero cost during the switching period, so that the CPU processing capacity is exerted, and the subsequent software programs can be operated at the highest-speed and safe frequency. Therefore, compared with the prior art, the method can provide the available clock with lower cost, more reliability and higher speed, can improve the software running efficiency and save the power consumption.
Drawings
In order to illustrate the embodiments of the invention more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being apparent that the drawings in the following description are only some embodiments of the invention, and that other drawings may be derived from those drawings by a person skilled in the art without inventive effort. In the drawings:
FIG. 1 is a logical block diagram of a phase locked loop of the prior art;
FIG. 2 is a simulated graph of clock signal versus time during relocking for the phase locked loop of FIG. 1;
FIG. 3 is a flow chart of a first embodiment of a method for preventing clock overshoot according to the present invention;
FIG. 4 is a simulation of clock signal versus time during relocking of a phase locked loop using the method of FIG. 3;
FIG. 5 is a logic structure diagram of a first embodiment of the clock generation apparatus of the present invention;
FIG. 6 is a logical block diagram of a first embodiment of the control detection module of FIG. 5;
FIG. 7 is a logical block diagram of a first embodiment of the status detection module of FIG. 5;
FIG. 8 is a logical block diagram of a second embodiment of the status detection module of FIG. 5;
FIG. 9 is a logical block diagram of a third embodiment of the status detection module of FIG. 5;
FIG. 10 is a logical block diagram of a fourth embodiment of the status detection module of FIG. 5;
FIG. 11 is a logical block diagram of a fifth embodiment of the status detection module of FIG. 5;
fig. 12 is a logic structure diagram of the first embodiment of the secure down-conversion module in fig. 5.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
The embodiments/examples described herein are specific embodiments of the present invention, are intended to be illustrative of the concepts of the present invention, are intended to be illustrative and exemplary, and should not be construed as limiting the embodiments and scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Fig. 3 is a flowchart of a first embodiment of a method of preventing clock overshoot according to the present invention, which is applied to a phase locked loop with postdivider, the phase locked loop including a phase detector, a low pass filter, a voltage controlled oscillator, a loop divider, and a postdivider. In this embodiment, when the frequency of the phase-locked loop output signal is changed by changing the frequency division coefficient of the loop divider and the frequency division coefficient of the postdivider, the following steps are performed:
s10, acquiring a post frequency division control signal of the phase-locked loop, and judging whether the post frequency division control signal changes or not;
in this step, a simple pulse signal may be issued if a change in the post-divide control signal is detected.
S20, when the post-frequency division control signal changes, acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
in this step, it should be noted first that the rising edges of the input signal and the feedback signal of the phase-locked loop are aligned (the phase difference is constant) in the locked state. When the frequency division coefficient of the loop frequency divider is changed, the feedback signal of the phase-locked loop changes, and whether the current state is in a locked state or an unlocked state can be determined by detecting the change of the feedback signal (the frequency of the input signal is unchanged).
S30, when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to the frequency reduction processing as a clock signal;
in this step, the phase-locked loop may overshoot in the out-of-lock state, so that the output signal of the phase-locked loop in the out-of-lock state may be subjected to a frequency reduction process, that is, the damped oscillation frequency is forcibly reduced and then used as the clock signal, thereby reducing the overshoot risk.
And S30, when the current state is the locking state, directly taking the output signal of the phase-locked loop as a clock signal.
Referring to fig. 4, first, assuming that the frequency of the input signal of the phase-locked loop is 12.5MHz, the clock generation relationship: fout [ [ n (lpdiv)/n (pstdiv) ] ] Fin, the system requires the clock to be raised from 375MHz to 387.5MHz, and the frequency switching is realized by changing the division coefficients of the loop divider and the post-divider: before switching, the frequency division coefficient of the loop frequency divider is 60, and the frequency division coefficient of the rear frequency divider is 2; after switching, the division factor of the loop divider becomes 31 and the division factor of the post-divider becomes 1. As is apparent from the figure, in the out-of-lock state, since the output signal is down-converted, the original overshoot frequency point of 750MHz does not appear, and the phase-locked loop outputs the output signal with 387.5MHz after being re-stabilized.
By implementing the technical scheme of the embodiment, when the frequency of the output signal of the phase-locked loop is adjusted by changing the frequency division coefficients of the loop frequency divider and the post frequency divider, if the change of the frequency division coefficient of the post frequency divider is detected, whether the output signal of the phase-locked loop is in the out-of-lock state or the locked state at present can be judged according to the input signal and the feedback signal, and in the out-of-lock state, the output signal of the phase-locked loop is subjected to frequency reduction processing to eliminate the risk of overshoot. Once it is judged that the lock state is present, the target frequency signal that has been stabilized is output. Therefore, each frequency switching time is self-adaptive and the system is shortest, and the highest-speed safe clock which can be provided currently can be provided to the system at zero cost during the switching period, so that the CPU processing capacity is exerted, and the subsequent software programs can be operated at the highest-speed and safe frequency. Therefore, compared with the prior art, the method can provide the available clock with lower cost, more reliability and higher speed, can improve the software running efficiency and save the power consumption.
In an alternative embodiment, step S10 is: and acquiring a post-frequency-division control signal and a loop-frequency-division control signal of the phase-locked loop, and judging whether the post-frequency-division control signal and the loop-frequency-division control signal are changed. In this embodiment, the post-division control signal and the loop-division control signal can be obtained at the same time, and whether the two signals are changed or not can be determined, because the post-division control signal and the loop-division control signal are generally sent out at the same time. Of course, in other embodiments, only the post-division control signal may be acquired and detected, because even if the loop-division control signal is not captured, whether the loop-division control signal has changed or not can be determined in step S20 by detecting the input signal and the feedback signal of the phase-locked loop.
In an alternative embodiment, in step S20, the current state of the phase-locked loop may be determined according to the following: comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value; if the difference between the two is smaller than the threshold value within the preset time period, determining that the current state of the phase-locked loop is a locked state; and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
It should be noted that the threshold is determined according to the characteristics of the PLL and the requirement of locking accuracy, and may be set according to the requirement, for example, one clock cycle of the oscillator.
In an alternative embodiment, in step S30, the down-conversion process may be performed according to the following manner: the output signal of the phase-locked loop is subjected to frequency reduction processing by a frequency reduction device, and the following conditions are met:
N(safdiv)≥N(lpdiv)/N(lpdiv_new)，
wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.
In this embodiment, due to the presence of the post-divider in the phase-locked loop, Fout [ [ n (lpdiv)/n (pstdiv) ] ] Fin is used, where Fin is the frequency of the input signal of the phase-locked loop, Fout is the frequency of the output signal of the phase-locked loop, n (lpdiv) is the division coefficient of the loop-divider, and n (pstdiv) is the division coefficient of the post-divider. When the frequency division coefficient of the post-divider is adjusted to N (pstdiv _ new), the output frequency Fosc of the vco does not change immediately, and is still Fosc (N) (lpdiv) Fin. Therefore, the frequency transient of the output signal is Fout _ over [ N (lpdiv)/N (pstdiv _ new) ] × Fin, and the ratio of the overshoot frequency to the final output frequency is K Fout _ over/Fout _ new ═ N (lpdiv)/N (lpdiv _ new). When the downconversion coefficient n (safdiv) is equal to or greater than K, there is just no overshoot. Since the numerical range of the frequency division coefficient of the loop frequency divider is different at each switching, the corresponding K value can be calculated at each time, and of course, the possible K value can also be simply set as: lpdiv (max)/lpdiv (min).
In addition, it should be noted that, for a phase locked loop with post-division, if the frequency of the output signal is changed by changing the division coefficient of its loop divider, that is, the division coefficient of the post-divider is not changed, it is theoretically only necessary to reduce the frequency of the output signal by X times, and according to the actual circuit, the conventional overshoot is only between 10% and 20%, so that the overshoot risk can be eliminated by setting X to be greater than 1.1, and preferably, X can be selected to be 1.5. Therefore, for a phase-locked loop with postdivision, if some application scenarios require that it only changes the frequency of the output signal by changing the division factor of its loop divider, while other application scenarios require that the frequency of the output signal is changed by changing the division factors of its loop divider and postdivider simultaneously, then with respect to the frequency reduction factor n (safdiv) of the frequency reducing means, it is sufficient to ensure that it is greater than the larger of both X and K.
Fig. 5 is a logical block diagram of a first embodiment of the clock generation apparatus according to the present invention, which includes a phase-locked loop 10 and a circuit for preventing clock overshoot. The phase-locked loop 10 is a phase-locked loop with post-frequency division, and specifically includes a phase detector 11, a low-pass filter 12, a voltage-controlled oscillator 13, a loop frequency divider 14, and a post-frequency divider 15, it should be understood that the functions, specific implementations, and logical relationships of the phase detector 11, the low-pass filter 12, the voltage-controlled oscillator 13, the loop frequency divider 14, and the post-frequency divider 15 in the phase-locked loop 10 may adopt well-known methods in the art, and are not described herein again. The circuit for preventing clock overshoot specifically comprises a control detection module 40, a state detection module 20 and a safety frequency reduction module 30, wherein the control detection module 40 is used for acquiring a post-frequency-division control signal of a phase-locked loop and judging whether the post-frequency-division control signal changes; the state detection module 20 is configured to obtain an input signal and a feedback signal of the phase-locked loop when the post-frequency-division control signal changes, and determine a current state of the phase-locked loop according to the input signal and the feedback signal, where the state of the phase-locked loop includes a locked state and an unlocked state; the safety frequency-reducing module 30 is configured to, when the current state is an unlocked state, perform frequency-reducing processing on an output signal of the phase-locked loop, and use the signal subjected to the frequency-reducing processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
In this embodiment, in conjunction with fig. 5, the control detection module 40 receives the POST-divider control signal REG _ POST; if the signal is detected to be changed, a signal, for example, a simple pulse signal, is sent to the status detection module 20, and the status detection module 20 compares the input signal Fin with the feedback clock Fback and outputs a status signal LCK according to the difference between the input signal Fin and the feedback clock Fback, for example, LCK is 0 to represent an out-of-lock status, and LCK is 1 to represent a lock status. The safety frequency-reducing module 30 determines whether to perform frequency-reducing processing on the output signal of the post-frequency divider 15 according to the lock state signal LCK, and directly outputs the output signal of the post-frequency divider 15 after re-locking.
In an optional embodiment, the state detection module 20 is configured to compare the input signal with the feedback signal, and determine whether a difference between the input signal and the feedback signal is smaller than a threshold, and if the difference between the input signal and the feedback signal is smaller than the threshold within a preset time period, that is, if the difference meets a requirement within a certain time, it indicates locking, and at this time, it determines that the current state of the phase-locked loop is a locked state; and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
In an alternative embodiment, referring to fig. 6, the control detection module includes a third delay 41 and an exclusive or gate 42, wherein an input terminal of the third delay 41 is connected to the control terminal of the POST-divider for inputting the POST-division control signal REG _ POST, an output terminal of the third delay 41 is connected to a first input terminal of the exclusive or gate 42, a second input terminal of the exclusive or gate 42 is connected to the control terminal of the POST-divider, and an output terminal of the exclusive or gate 42 is used for outputting the reset signal Rst and is connected to the status detection module. In this embodiment, the exclusive-or gate 42 generates a negative pulse having a time width equal to the delay time of the third delay 42 whenever the POST-division control signal REG _ POST changes.
In an alternative embodiment, with reference to fig. 7, the state detection module of this embodiment is implemented by using a cross-delay latch structure, and specifically, the state detection module includes: regarding the first delay unit 21 and the second delay unit 22, it should be noted that the delay time of the first delay unit 21 and the second delay unit 22 should be longer than the setup time of the D flip-flop and shorter than the period of the output signal, and in practical applications, the delay times of the two delay units can be designed within a reasonable range. In this embodiment, the input terminal of the first delay unit 21 is connected to the input terminal of the phase-locked loop for inputting the input signal Fin of the phase-locked loop, the output terminal of the first delay unit 21 is connected to the clock terminal of the first D flip-flop 23, the data input terminal of the first D flip-flop 23 is connected to the feedback terminal of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop, and the data output terminal of the first D flip-flop 23 is connected to the first input terminal of the and gate 25; the input end of the second delay 22 is connected to the feedback end of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop, the output end of the second delay 22 is connected to the clock end of the second D flip-flop 24, the data input end of the second D flip-flop 24 is connected to the input end of the phase-locked loop for inputting the input signal Fin of the phase-locked loop, the data output end of the second D flip-flop 24 is connected to the second input end of the and gate 25, the output end of the and gate 25 is used for outputting the status signal LCK, and the reset ends of the first D flip-flop 23 and the second D flip-flop 24 are respectively connected to the output end of the or gate 42 for inputting the reset signal.
It should be noted that the connection relationship in the present application includes, but is not limited to, a connection relationship generated by connecting two input terminals based on the input signals for receiving the same input signals, a connection relationship generated by connecting output terminals and input terminals, and the like.
The phase-locked loop state detection operation is described below with reference to fig. 5-7: the phase-locked loop aligns the rising edges of the input signal Fin and the feedback signal Fback (phase difference is constant) during locking, the rising edge of either delay can capture the high level of the other, and the output signals of the two D flip- flops 23 and 24 are always 1. When the division factor of the post-divider changes, i.e. the post-division control signal changes, both D-flip- flops 23, 24 will be briefly reset below, and then, due to the change of the division factor of the loop-divider, the output signal Fback of the phase locked loop changes, the new rising edge of which will differ from the input signal Fin by one or more cycles of the output signal Fosc. If the phase-locked loop increases the output frequency, i.e. the frequency division factor increases (e.g. from N to N + K), Fback will be delayed by K cycles from Fin, at which time the first D flip-flop 23 will output 0, so that the LCK signal output by the and gate 25 is 0, i.e. an out-of-lock signal is issued. Then, the output signal Fosc is gradually increased under the loop action until the overshoot occurs, at which time, the edge of the feedback signal Fback will lead the edge of the input signal Fin, and the second D flip-flop 24 will output 0 again, so that the and gate 25 continues to output the LCK signal of 0. Only when the edges of the feedback signal Fback and the input signal Fin are realigned within a certain range, the two D flip- flops 23 and 24 output 1 again, so that the LCK signal output by the and gate is 1, i.e., a lock signal is sent out.
In an alternative embodiment, referring to fig. 8, the status detection module of this embodiment comprises: module 222 and phase inverter 223 are engulfed to exclusive-or gate 221, pulse, the first input of exclusive-or gate 221 is used for the input signal Fin of phase-locked loop, the second input of exclusive-or gate 221 is used for the input the feedback signal Fback of phase-locked loop, the output of exclusive-or gate 221 with the input that module 222 was engulfed to the pulse is connected, the output that module 222 was engulfed to the pulse with the input of phase inverter 223 is connected, the output of phase inverter 223 with the control end of safety module 30 that falls is connected for output status signal LCK extremely safety module 30 that falls.
In an alternative embodiment, referring to fig. 9, the status detection module of this embodiment comprises: the phase-locked loop comprises an exclusive-or gate 231, a resistor R1, a capacitor C1 and a phase inverter 232, wherein a first input end of the exclusive-or gate 231 is used for inputting an input signal Fin of the phase-locked loop, a second input end of the exclusive-or gate 231 is used for inputting a feedback signal Fback of the phase-locked loop, an output end of the exclusive-or gate 231 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the capacitor C1 and an input end of the phase inverter 232 respectively, the other end of the capacitor C1 is grounded, and an output end of the phase inverter 232 is connected with a control end of the safety frequency-down module 30 and used for outputting a state signal LCK to the safety frequency-.
In an alternative embodiment, referring to fig. 10, the status detection module of this embodiment comprises: the phase-locked loop comprises an exclusive-or gate 241, a delay unit 242, an and gate 243 and a phase inverter 244, wherein a first input end of the exclusive-or gate 241 is used for inputting an input signal Fin of the phase-locked loop, a second input end of the exclusive-or gate 241 is used for inputting a feedback signal Fback of the phase-locked loop, an output end of the exclusive-or gate 241 is respectively connected with an input end of the delay unit 242 and a first input end of the and gate 243, an output end of the delay unit 242 is connected with a second input end of the and gate 243, an output end of the and gate 243 is connected with an input end of the phase inverter 244, and an output end of the phase inverter 244 is connected with a control end of the safety frequency-down module 30 and is used for outputting a state signal.
In an alternative embodiment, referring to fig. 11, the status detection module of this embodiment comprises: the phase-locked loop control circuit comprises an exclusive-or gate 251, a PMOS transistor M1, an NMOS transistor M2, a capacitor C2 and a delay unit 252, wherein a first input end of the exclusive-or gate 251 is used for inputting an input signal Fin of the phase-locked loop, a second input end of the exclusive-or gate 251 is used for inputting a feedback signal Fback of the phase-locked loop, an output end of the exclusive-or gate 251 is respectively connected with gates of the PMOS transistor M1 and the NMOS transistor M2, a source of the PMOS transistor M1 is respectively connected with a power supply end and one end of the capacitor C2, a constant current source is connected between a source of the NMOS transistor M2 and the ground, after being connected with drains of the PMOS transistor M1 and the NMOS transistor M2, the constant current source is respectively connected with the other end of the capacitor C2 and an input end of the delay unit 252, and an output end of the delay unit 252 is used as an output end of a state detection module and is connected with a control end. The delay unit 252 may be implemented by a buffer. In this embodiment, optionally, the delay unit 252 may be omitted, that is, the drain of the PMOS transistor M1, the drain of the NMOS transistor M2, and the other end of the capacitor C2 are connected to serve as the output end of the state detection module, and are used to output the state signal LCK to the safety frequency reduction module.
In an alternative embodiment, referring to fig. 12, the safety down-conversion module of this embodiment includes a down-conversion device 31 and a switch 32, wherein an input terminal of the down-conversion device 31 and a first input terminal of the switch 32 are both connected to an output terminal of the phase-locked loop for inputting an output signal of the phase-locked loop, i.e., an output signal Fpst of the post-divider, an output terminal of the down-conversion device 31 is connected to a second input terminal of the switch 32, a control terminal of the switch 32 is connected to an output terminal of the and gate 25, and an output terminal of the switch 32 is used for outputting a clock signal Fout.
Furthermore, the circuit for preventing clock overshoot of the present invention may further include a frequency-reduction control module, where the frequency-reduction control module is configured to obtain a frequency-division coefficient after the change of the loop frequency divider according to the loop frequency-division control signal of the phase-locked loop, and determine the frequency-reduction coefficient of the frequency-reduction apparatus according to the frequency-division coefficient before the change of the loop frequency divider and the frequency-division coefficient after the change, and the frequency-reduction coefficient of the frequency-reduction apparatus satisfies the following conditions:
N(safdiv)≥N(lpdiv)/N(lpdiv_new)，
wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (10)
1. A method of preventing clock overshoot, applied in a phase locked loop with postdivider, said phase locked loop comprising a phase detector, a low pass filter, a voltage controlled oscillator, a loop divider and a postdivider, characterized in that, when changing the frequency of the output signal of the phase locked loop by changing the division factor of the loop divider and the division factor of the postdivider, the following steps are performed:
acquiring a post-frequency-division control signal of a phase-locked loop, and judging whether the post-frequency-division control signal changes;
when the post-frequency-division control signal changes, acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal;
when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
2. The method of claim 1, wherein obtaining a post-divide control signal of a phase-locked loop and determining whether the post-divide control signal changes comprises:
and acquiring a post-frequency-division control signal and a loop-frequency-division control signal of the phase-locked loop, and judging whether the post-frequency-division control signal and the loop-frequency-division control signal are changed.
3. The method of claim 1, wherein determining the current state of the phase locked loop based on the input signal and the feedback signal comprises:
comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value;
if the difference between the two is smaller than the threshold value within the preset time period, determining that the current state of the phase-locked loop is a locked state;
and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
4. The method of claim 1, wherein down-converting the output signal of the phase-locked loop comprises:
the output signal of the phase-locked loop is subjected to frequency reduction processing by a frequency reduction device, and the following conditions are met:
N(safdiv)≥N(lpdiv)/N(lpdiv_new)，
wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.
5. A circuit for preventing clock overshoot, for use in a phase locked loop with postdivider, the phase locked loop including a phase detector, a low pass filter, a voltage controlled oscillator, a loop divider, and a postdivider, the circuit comprising:
the control detection module is used for acquiring a post-frequency-division control signal of the phase-locked loop and judging whether the post-frequency-division control signal changes;
the state detection module is used for acquiring an input signal and a feedback signal of the phase-locked loop when the post-frequency-division control signal changes, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
the safety frequency reduction module is used for performing frequency reduction processing on an output signal of the phase-locked loop when the current state is an unlocked state, and taking the signal subjected to the frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
6. The circuit of claim 5, wherein the control detection module comprises a third delay and an exclusive-nor gate, wherein an input terminal of the third delay is connected to the control terminal of the postscaler for inputting a postscaler control signal, an output terminal of the third delay is connected to the first input terminal of the exclusive-nor gate, a second input terminal of the exclusive-nor gate is connected to the control terminal of the postscaler, and an output terminal of the exclusive-nor gate is connected to the state detection module.
7. The circuit of claim 6, wherein the state detection module comprises: the phase-locked loop comprises a first delayer, a second delayer, a first D trigger, a second D trigger and an AND gate, wherein the input end of the first delayer is connected with the input end of a phase-locked loop so as to be used for inputting an input signal of the phase-locked loop, the output end of the first delayer is connected with the clock end of the first D trigger, the data input end of the first D trigger is connected with the feedback end of the phase-locked loop so as to be used for inputting a feedback signal of the phase-locked loop, and the data output end of the first D trigger is connected with the first input end of the AND gate; the input end of the second time delay is connected with the feedback end of the phase-locked loop so as to input a feedback signal of the phase-locked loop, the output end of the second time delay is connected with the clock end of the second D trigger, the data input end of the second D trigger is connected with the input end of the phase-locked loop so as to input an input signal of the phase-locked loop, the data output end of the second D trigger is connected with the second input end of the AND gate, the output end of the AND gate is used for outputting a state signal, and the reset ends of the first D trigger and the second D trigger are respectively connected with the output end of the AND gate.
8. The circuit for preventing clock overshoot according to claim 7, wherein the safety down-conversion module comprises a down-conversion device and a switch, an input terminal of the down-conversion device and a first input terminal of the switch are both connected to an output terminal of the phase-locked loop for inputting the output signal of the phase-locked loop, an output terminal of the down-conversion device is connected to a second input terminal of the switch, a control terminal of the switch is connected to an output terminal of the and gate, and an output terminal of the switch is used for outputting the clock signal.
9. The circuit of claim 8, further comprising:
the frequency reduction control module is used for acquiring the frequency division coefficient after the change of the loop frequency divider according to the loop frequency division control signal of the phase-locked loop when the post-frequency division control signal changes, and determining the frequency reduction coefficient of the frequency reduction device according to the frequency division coefficient before the change of the loop frequency divider and the frequency division coefficient after the change, wherein the frequency reduction coefficient of the frequency reduction device meets the following conditions:
N(safdiv)≥N(lpdiv)/N(lpdiv_new)，
wherein, N (safdiv) is a frequency reduction coefficient of the frequency reducing device, N (lpdiv) is a frequency division coefficient before the loop frequency divider is changed, and N (lpdiv _ new) is a frequency division coefficient after the loop frequency divider is changed.
10. A clock generation arrangement comprising a phase locked loop comprising a phase detector, a low pass filter, a voltage controlled oscillator, a loop divider and a post divider, characterized in that the clock generation arrangement further comprises a circuit for preventing clock overshoots as claimed in any of the claims 5-9.
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