CN103714012B

CN103714012B - Data processing method and device

Info

Publication number: CN103714012B
Application number: CN201310746960.8A
Authority: CN
Inventors: 黄帅; 王焕东; 陈新科
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2013-12-30
Filing date: 2013-12-30
Publication date: 2016-08-17
Anticipated expiration: 2033-12-30
Also published as: CN103714012A

Abstract

The invention discloses a kind of data processing method and device.The method includes: generate the first address signal according to the first clock signal, according to the first clock signal, the first data signal is written to storage address corresponding with the first address signal in the first memory block；If the first clock signal is positioned at the first pre-set interval relative to the phase contrast of second clock signal, the rising edge of second clock signal is then used to gather the first address signal to generate the second address signal, and according to the storage address read-outing data corresponding with the second address signal from the first memory block of second clock signal；If this phase contrast is positioned at the second pre-set interval, then the trailing edge of second clock signal is used to gather the first address signal to generate the 3rd address signal, and according to the storage address read-outing data corresponding with the 3rd address signal from the first memory block of second clock signal；Using the data of reading as the second data signal.The present invention solves the problem that the timing margins deficiency in data cross clock domain transmission path is brought.

Description

Data processing method and device

Technical field

The present invention relates to sequential logical circuit field, in particular to a kind of data processing method and device.

Background technology

Existing data signal cross clock domain transmission scheme in, it will usually use a clock signal hopping edge go gather with The data signal that another clock signal is corresponding, to obtain the data signal corresponding with preceding clock signal.But in this scheme In, data signal timing margins on the transmission path that cross clock domain transmits is uncontrollable and uncertain, its timing margins Can be the biggest, it is also possible to the least, and when timing margins is less, due to as collection The persistent period of the value after the data signal renewal of object is shorter, and its data mode is relative and unstable, the number therefore collected According to being also inaccurate, thus have impact on the reliability of the cross clock domain transmission of data signal.In other words, existing scheme cannot be protected Card meets the requirement to timing margins, and its reason then can be attributed to owing to transmitting road at cross clock domain when gathering internal memory reading data The problem that cannot correctly gather that timing margins deficiency on footpath causes.

For above-mentioned problem, effective solution is the most not yet proposed.

Summary of the invention

Embodiments provide a kind of data processing method and device, with at least solve due to gather when internal memory reads data across The technical problem that cannot correctly gather that timing margins deficiency on clock zone transmission path causes.

An aspect according to embodiments of the present invention, it is provided that a kind of data processing method, including: obtain the first data signal, First clock signal and second clock signal, wherein, the first data signal is corresponding with the first clock signal, the first clock signal Clock cycle is identical with the clock cycle of second clock signal；The first address of mechanical periodicity is generated according to above-mentioned first clock signal Signal, and according to above-mentioned first clock signal, above-mentioned first data signal is written in the first memory block and above-mentioned first address letter Number corresponding storage address；If above-mentioned first clock signal is positioned at the first preset areas relative to the phase contrast of above-mentioned second clock signal In, then use the rising edge of above-mentioned second clock signal to gather above-mentioned first address signal to generate the second address signal, and root According to the storage address read-outing data that above-mentioned second clock signal is corresponding with above-mentioned second address signal from above-mentioned first memory block；If Above-mentioned first clock signal is positioned at the second pre-set interval relative to the phase contrast of above-mentioned second clock signal, then use above-mentioned second The trailing edge of clock signal gathers above-mentioned first address signal to generate the 3rd address signal, and according to above-mentioned second clock signal from Storage address read-outing data corresponding with above-mentioned 3rd address signal in above-mentioned first memory block；The data read are counted as second The number of it is believed that.

Another aspect according to embodiments of the present invention, additionally provides a kind of data processing method, including: obtain Memory Controller Hub pair The clock signal of system answered, obtains the reading data signal and read data strobe (RDS) signal returned by each in multiple memory chips, And above-mentioned read data strobe (RDS) signal is carried out time delay；According to data processing method pair above-mentioned as any one of Claims 1-4 The reading data signal of each correspondence in above-mentioned multiple memory chip processes, and will deposit from the first memory block or first The data read in storage area and the second memory block read data as the internal memory collected, and wherein, the first data signal is above-mentioned reading The number of it is believed that, the first clock signal is the read data strobe (RDS) signal after time delay, and second clock signal is said system clock signal；Right The above-mentioned internal memory of each correspondence in the above-mentioned multiple memory chips collected is read data and is synchronized, and the internal memory after synchronizing Read data and be sent to Memory Controller Hub.

Another aspect according to embodiments of the present invention, additionally provides a kind of data processing equipment, including: the first address generating circuit, Including the first triggering input and the first address output end, wherein, above-mentioned first address generating circuit is for according to from above-mentioned first The first clock signal triggering input input generates the first address signal of mechanical periodicity, and defeated from above-mentioned first address output end Go out above-mentioned first address signal；Second address generating circuit, including the second triggering input, the 3rd triggering input, the first ground Location input and the second address output end, above-mentioned first address input end directly or indirectly connects above-mentioned first address output end, its In, above-mentioned second address generating circuit for from above-mentioned second trigger input input above-mentioned first clock signal relative to from When the phase contrast of the above-mentioned 3rd second clock signal triggering input input is positioned at the first pre-set interval, when using above-mentioned second Rising edge above-mentioned first address signal of collection of clock signal is to generate the second address signal, and exports from above-mentioned second address output end Above-mentioned second address signal, is positioned at the second preset areas in above-mentioned first clock signal relative to the phase contrast of above-mentioned second clock signal In time, use above-mentioned second clock signal trailing edge gather above-mentioned first address signal to generate the 3rd address signal, and from Above-mentioned second address output end exports above-mentioned 3rd address signal；First storage circuit, triggers input, the second ground including the 4th Location input, the 3rd address input end, the first data input pin and the first data output end, above-mentioned second address input end connects Above-mentioned first address output end, above-mentioned 3rd address input end connects above-mentioned second address output end, wherein, above-mentioned first storage Circuit will be for inputting from above-mentioned first data input pin according to above-mentioned first clock signal triggering input input from the above-mentioned 4th Above-mentioned first data signal be written in the first memory block the storage address corresponding with above-mentioned first address signal, and according to upper State the storage ground that second clock signal is corresponding with above-mentioned second address signal or above-mentioned 3rd address signal from above-mentioned first memory block Location reads data, and the data read is exported from above-mentioned first data output end.

In embodiments of the present invention, the first clock signal is utilized the first data signal to be written in the first memory block and the first address The storage address that signal is corresponding, utilize second clock signal from the first memory block with the second address signal or the 3rd address signal pair The storage address read-outing data answered is as the second data signal, it is achieved that the transmission of the cross clock domain of the first data signal.Further Ground, in embodiments of the present invention, use carry out judging according to the phase contrast between the first clock signal and second clock signal, with The rising edge of Selection utilization second clock signal gathers the first address signal to generate above-mentioned second address signal or to utilize the The trailing edge of two clock signals gathers the first address signal in the way of generating above-mentioned 3rd address signal, it is ensured that the first address Timing margins on the cross clock domain transmission path of signal, and then ensure that first data signal clock zone from the first clock signal There is on the transmission path of the clock zone of second clock signal the timing margins of abundance, it is achieved thereby that correctly gather the first data The technique effect of signal, solves owing to the timing margins deficiency gathered when internal memory reads data on cross clock domain transmission path causes The technical problem that cannot correctly gather.

Accompanying drawing explanation

Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, and the present invention shows Meaning property embodiment and explanation thereof are used for explaining the present invention, are not intended that inappropriate limitation of the present invention.In the accompanying drawings:

Fig. 1 is the schematic diagram of a kind of optional data processing method according to embodiments of the present invention；

Fig. 2 is the schematic diagram of another kind of optional data processing method according to embodiments of the present invention；

Fig. 3 is the sequential chart of another kind of optional data processing method according to embodiments of the present invention；

Fig. 4 is the schematic diagram of the optional data processing method of according to embodiments of the present invention another；

Fig. 5 is the schematic diagram of the optional data processing method of according to embodiments of the present invention another；

Fig. 6 is the schematic diagram of the optional data processing method of according to embodiments of the present invention another；

Fig. 7 is the schematic diagram of a kind of optional data processing equipment according to embodiments of the present invention；

Fig. 8 is the schematic diagram of another kind of optional data processing equipment according to embodiments of the present invention.

Detailed description of the invention

Below with reference to accompanying drawing and describe the present invention in detail in conjunction with the embodiments.It should be noted that in the case of not conflicting, Embodiment in the application and the feature in embodiment can be mutually combined.

Embodiment 1

According to embodiments of the present invention, it is provided that a kind of data processing method, as it is shown in figure 1, the method includes:

S102: obtain the first data signal, the first clock signal and second clock signal, wherein, the first data signal and first Clock signal is corresponding, and the clock cycle of the first clock signal is identical with the clock cycle of second clock signal；

S104: generate the first address signal of mechanical periodicity according to the first clock signal, and according to the first clock signal by the first number The number of it is believed that is written to storage address corresponding with the first address signal in the first memory block；

S106: if the first clock signal is positioned at the first pre-set interval relative to the phase contrast of second clock signal, then use second The rising edge of clock signal gathers the first address signal to generate the second address signal, and according to second clock signal from the first storage Storage address read-outing data corresponding with the second address signal in district；

S108: if the first clock signal is positioned at the second pre-set interval relative to the phase contrast of second clock signal, then use second The trailing edge of clock signal gathers the first address signal to generate the 3rd address signal, and according to second clock signal from the first storage Storage address read-outing data corresponding with the 3rd address signal in district；

S110: using the data of reading as the second data signal.

It will be clear that, one of problem to be solved by this invention is to provide a kind of data processing method, at least to realize being The interior collection that internal memory is read data of system clock zone, thus in some embodiments of the invention, first obtained by step S102 Data signal, the first clock signal and second clock signal can represent reading data DQ returned by internal memory respectively, read data choosing Messenger DQS and the system clock sys_clk be given by Memory Controller Hub or CPU etc..For another angle, more one As, in embodiments of the present invention, it is also possible to reading DQS is summarised as a clock signal, reading DQ is summarised as this clock letter A number corresponding data signal, and sys_clk is summarised as identical with reading clock signal period that DQS represents but not necessarily with Another clock signal of step, this enforcement having no effect on technical solution of the present invention and the realization of technique effect thereof.Below for statement Convenient, above-mentioned " clock signal " is designated as the first clock signal, when above-mentioned " another clock signal " is designated as second Clock signal, is designated as the first data signal by above-mentioned " data signal ".

It should be appreciated that above-mentioned " first ", " second " are only used for distinguishing above-mentioned two clock signal, similarly, the present invention In the statement such as alleged " first ", " second " be only used for distinguishing between the two or many persons, and should not be construed as order or Restriction on person's corresponding relation.In addition it should be noted that for clock signal alleged in invention, it should be understood that for by can The pulse signal constituted by the interval rising that is alternately present of fixed cycle of the logic circuit component identifications such as depositor, trailing edge, Neither answer its implication of Conditions of Deliberate Misinterpretation, such as, be construed to arbitrary square wave, also should not be construed as the present invention is constituted any unnecessary Limit.

Implement the data processing method provided according to the present invention, step S104 may include that A, generates according to the first clock signal First address signal of mechanical periodicity；B, according to the first clock signal, the first data signal is written in the first memory block with first The storage address that address signal is corresponding.Wherein, it is however generally that, this first memory block can be considered as a storehouse, its concrete manifestation Form can be a memorizer, such as one caching, but this is not construed as limiting by the present invention, such as, in some of the present invention In embodiment, this first memory block can be used for representing a part of memory space in a memorizer, presets many in other words Individual storage address etc..

In step, the concrete generating mode of the first address signal can have multiple, such as, and the simplest mode of one of which Can be the rising edge according to the first clock signal or the first address signal is done cycle accumulor, that is, detecting by trailing edge When the rising edge of one clock signal or trailing edge, the first address signal is added 1, and when the first address signal increases to a preset value, When such as 7, again by its zero setting, thus the circulation that from 0 to 7 can be realized, as the first address signal.Certainly, This kind of preferably mode, not unique embodiment, such as, in some embodiments of the invention, above-mentioned cumulative Step-length can not also be 1, and then, can not also be for simply for generating or updating the logic of propositions of the first address signal Cumulative, but other calculation, the sequence such as successively decreased or the sequence etc. after Gray code conversion.

In stepb, according to the first clock signal, the first data signal can be written in the first memory block and the first address letter Number corresponding storage address.Wherein, most typically, the storage address that the first address signal is corresponding in the first memory block can be Address represented by the value of the first address signal, the such as first address signal is 0, then the storage address of its correspondence can be first to deposit [0] storage position in storage area, the first address signal is 1, then the storage address of its correspondence can be [1] storage in the first memory block Position, but in some embodiments of the invention, the two numerically can also show as difference, such as passing through Gray code The first address signal obtained after conversion, the first address signal is 3, then the numerical value before the storage address of its correspondence can also be conversion [2] storage position in the first indicated memory block.

In embodiments of the present invention, the data entrained by the first data signal can be write the first storage successively by step S104 These data are kept in by district to utilize the first memory block to realize, in case to these data in step S106 or step S108 Read operation, in other words, is written to the data of the first memory block by step S104 and can also be designated as being read out data, and by Sequential in write operation corresponds to the first clock signal, and the sequential read is corresponding to second clock signal, such that it is able to realize First data signal to the transmission of the clock zone of second clock signal, and then can adjust write from the clock zone of the first clock signal And the time delay between Du Chuing is to obtain the timing margins in more sufficient cross clock domain transmission path.

It should be noted that in embodiments of the present invention, the sequential embodied in step A and step B both corresponds to the first clock Signal, but the present invention is not required to limit the priority execution order of the two step, wherein, it is however generally that, for utilizing the The rising edge of one clock signal or trailing edge perform the situation of respective operations, it is contemplated that by this rising edge or decline in step A The generation triggering the first address signal just performed on edge updates operation in other words and typically requires the operation time that consumption is certain, at that time Sequence path to be generally longer than the storage circuit identification to this first address signal for the first data signal writes the first memory block, Therefore for the operation of renewal the first address signal triggered by rising edge or trailing edge and corresponding to the first address signal simultaneously The operation of write the first data signal of storage address, the address of write is typically the value of the first address signal before updating, and Value after non-update, thus it is presented as that step B performed before step A.

Further, in embodiments of the present invention, for the operation that in step B, the first data signal is written to the first memory block Also relate to according to the collection to the first data signal of first clock signal, thus the first data signal and the first clock signal is right Should be related to generally can be embodied in utilizes this corresponding relation to realize on accurate acquisition to the first clock signal, wherein, general and Speech, this first clock signal can be generally the clock signal designed for correct collection the first data signal, such as by interior Deposit for returning as the reading DQ of the first data signal, as the reading DQS of the first clock signal i.e. for adopting reading DQ Collection.But under this scene, the most right with the reading rising of DQS, trailing edge owing to meeting the readings DQ of DDR agreement regulation Together, therefore described in step S104 under this scene according to the first clock signal generating the first address signal and write first number The operation of the number of it is believed that, it is also possible to be not simply presented as directly utilizing the rising edge of the first clock signal or trailing edge performs accordingly Operation, but similar and prior art, first i.e. read DQS to the first clock signal and carry out delay process, after then utilizing time delay Read the rising edge of DQS or trailing edge realizes the generation of the first address signal and the collection of the first data signal and write.It follows that In one aspect, technical solution of the present invention can also be combined to reach further with prior art more excellent technique effect, it should Understanding, this type of embodiment is regarded as within protection scope of the present invention.On the other hand, technical solution of the present invention embodies Be a kind of inventive concept, the scope that the program is contained should be understood under this design, covers technical solution of the present invention, And meeting all embodiments of the reasonable prediction of those of ordinary skill, it will be appreciated that those of ordinary skill has the ability to get rid of those Obvious irrational embodiment, thus the counter productive that should not caused because of the irrational embodiment of some of the present invention and structure The improper explanation of the present invention in pairs.

On the basis of being described above, the data processing method provided according to embodiments of the present invention, it is different from prior art, permissible First the first clock signal is judged relative to the phase contrast of second clock signal, wherein, preset if this phase contrast is positioned at first In interval, then can pass through step S106, use the rising edge of second clock signal to gather the first address signal to generate the second ground Location signal, and according to the storage address read-outing data corresponding with the second address signal from the first memory block of second clock signal, if This phase contrast is positioned at the second pre-set interval, then can pass through step S108, uses the trailing edge of second clock signal to gather first Address signal to generate the 3rd address signal, and according to second clock signal from the first memory block corresponding with the 3rd address signal Storage address read-outing data.

Wherein, with step S104 accordingly, can deposit from first according to second clock signal in step S106 or step S108 Storage address read-outing data corresponding with the second address signal or the 3rd address signal in storage area, wherein, owing to this second address is believed Number or the 3rd address signal be derived from step S104 first address signal corresponding with the writing address of the first data signal, because of This can utilize the second address signal or the 3rd address signal to be a first new data signal by the data reconstruction of reading, is designated as Second data signal, wherein, the first data signal is identical with the content of the second data signal, but in sequential, the former is corresponding In the first clock signal, and the latter is corresponding to second clock signal, thus completes the transmission of the cross clock domain of data.

On the basis of the cross clock domain realizing data transmits, the embodiment of the present invention can be by step S106 and step S108 Between selection realize the timing margins in well-to-do cross clock domain transmission path, and then reach data are correctly gathered Technique effect.It is evidenced from the above discussion that, in embodiments of the present invention, it is similar to prior art, when again may be by first Clock signal realizes the accurate acquisition to the first data signal, and the only possible present invention that occurs in of defect that therefore timing margins is not enough implements In example other cross clock domain transmission during, namely occur in the first address signal from the clock zone of the first clock signal to On the transmission path of the clock zone of second clock signal.Wherein, for the first address signal, no matter it utilizes the first clock Rising edge or the trailing edge of signal are updated, and effective persistent period of each of which value is a clock cycle, due to The clock cycle of second clock signal and the first clock signal is identical, and differs between the rising edge of second clock signal and trailing edge Half clock cycle, therefore when the first address signal is acquired respectively by the rising edge utilizing second clock signal with trailing edge, Certainly exist its time point gathered of the one of which acquisition mode time difference relative to the starting point of above-mentioned effective persistent period, also I.e. first address signal carries out the sequential of cross clock domain transmission from the clock zone of the first clock signal to the clock zone of second clock signal Nargin, more than half clock cycle, otherwise there will be no any one second clock letter within the second half section of above-mentioned effective persistent period Number rising edge or trailing edge, this by cause rise/fall before this second half section along with this second half section after decline/rising edge Between interval more than half clock cycle, thus do not meet the sequential feature of the rising edge in second clock signal and trailing edge.

Further, in embodiments of the present invention, a kind of acquisition mode that timing margins is bigger can be selected the first address signal It is acquired, this acquisition mode or utilize the rising edge of second clock signal to gather the first address signal, or utilizes The trailing edge of two clock signals gathers the first address signal.Wherein, carry out more according to the first clock signal due to the first address signal Newly, thus effective persistent period of each value of the first address signal is corresponding with the first clock signal, the most specifically selects second The rising edge of clock signal or trailing edge gather the first address signal and are obtained in that bigger timing margins depends on the first clock letter Number and second clock signal between phase relation, phase contrast the most therebetween, more specifically, it can be determined that when first Whether clock signal is in the first pre-set interval or the second pre-set interval relative to the phase contrast of second clock signal, wherein, the One pre-set interval and the second pre-set interval generally could be arranged to mutually disjoint two intervals.

In sum, in embodiments of the present invention, the first clock signal is utilized the first data signal to be written in the first memory block The storage address corresponding with the first address signal, utilize second clock signal from the first memory block with the second address signal or the 3rd Storage address read-outing data corresponding to address signal is as the second data signal, it is achieved that the biography of the cross clock domain of the first data signal Defeated.Further, in embodiments of the present invention, use to enter according to the phase contrast between the first clock signal and second clock signal Row judge, gather with the rising edge of Selection utilization second clock signal the first address signal with generate above-mentioned second address signal or Person is to utilize the trailing edge of second clock signal to gather the first address signal in the way of generating above-mentioned 3rd address signal, it is ensured that Timing margins on the cross clock domain transmission path of the first address signal, and then ensure that the first data signal is believed from the first clock Number the timing margins that is transmitted to the clock zone of second clock signal of clock zone, it is achieved thereby that correctly gather the first data letter Number technique effect, solve owing to the timing margins deficiency gathered when internal memory reads data on cross clock domain transmission path causes The technical problem that cannot correctly gather.

Below in conjunction with a specific embodiment, the operation principle of technical solution of the present invention is illustrated in more detail.Wherein, Alternatively, as in figure 2 it is shown, in embodiments of the present invention, above-mentioned steps A may include that

S202: when the rising edge of the first clock signal being detected, updates the first address signal according to logic of propositions；

Wherein, above-mentioned steps B may include that

S204: when the rising edge of the first clock signal being detected, is written to the first numerical signal in the first memory block with first The storage address that address signal is corresponding is read out data as first, and wherein, the first memory block is for storage the first clock signal What multiple continuous print rising edges were corresponding multiple first is read out data, and multiple first each being read out in data is deposited first In storage area, correspondence uniquely stores address.

Under above-mentioned scene, the first pre-set interval described in step S106 could be arranged to (T/2, T), institute in step S108 The second pre-set interval stated could be arranged to (0, T/2), and wherein, T represents the clock cycle of second clock signal.By above-mentioned Setting, i.e. may insure that the first address signal to such an extent as to the first data signal at least has the timing margins that the cross clock domain of T/2 transmits.

Below with reference to the sequential chart shown in Fig. 3, this embodiment is further described.In the sequential chart shown in Fig. 3, the 1st Row can represent that the first clock signal, the 2nd row can represent the first data signal, and the 3rd row can represent the first address signal, 4th row can represent the storage address [0] in the first memory block, and the 5th row can represent the storage address [1] in the first memory block, 6th row can represent second clock signal, and the 7th row can represent the second address signal, and eighth row can represent a kind of 3rd ground Location signal, the 9th row can represent another kind of 3rd address signal.Wherein, as shown in the 1st and 6 every trades, the first clock signal Between the leading half period of second clock signal to the cycle, the first clock signal is believed relative to second clock in other words Number phase contrast between T/2 and T, namely this phase contrast is positioned at the first pre-set interval.

As shown in the 1st and 3 row in Fig. 3, in step S202, can when the rising edge of the first clock signal being detected, Updating the first address signal according to logic of propositions, wherein, for ease of describing, the logic of propositions shown in Fig. 3 is simply defined as The first address signal after renewal adds 1 equal to the first address signal before updating, certainly, in some other embodiment of the present invention, Other increasingly complex logic of propositions, this enforcement having no effect on technical solution of the present invention and the reality of technique effect thereof can also be defined Existing, this is not limited in any way by the present invention.

As shown in the 1st to 5 row in Fig. 3, in step S204, can when the rising edge of the first clock signal being detected, First numerical signal is written to storage address corresponding with the first address signal in the first memory block and is read out data as first. Wherein, when first rising edge of the first clock signal shown in the 1st row arrives, the first numerical signal shown in the 2nd row Value is a, and the value of the first address signal shown in the 3rd row is in by the renewal process of 0 to 1, in conjunction with foregoing teachings, due to this Updating operation needs certain time to complete, therefore when above-mentioned first rising edge arrives, and the first corresponding address signal Value remain as 0, therefore as shown in Fig. 3 the 4th row, numerical value a can be written in the first memory block by step S204 Storage address [0], the numerical value a being simultaneously stored in may act as being read out data, until data a are in step S106 or step S108 Middle read.Similarly, when second rising edge of the first clock signal arrives, numerical value b can be write by step S204 The storage address [1] entered in the first memory block, and after numerical value a, numerical value b also will become and be read out data until this is treated Read data to be read.

Further, as the 3rd in Fig. 3,6,7 and 8 are shown in row, in step S106 or step S108, it is possible to use First address signal is acquired by rising edge or the trailing edge of second clock signal, to obtain the second address signal or the 3rd address Signal.For the quality of both modes, by the collection that 0 is updated to the address value 1 after 1 can be with the first address signal Example compares.

If the rising edge using second clock signal gathers the first address signal, and by the first address signal of collecting directly as Second address signal, then the sequential of this second address signal can be as shown in the 7th row in Fig. 3.Wherein, believe in the first address After number being updated to 1 by 0, interval time arrives the rising edge of second clock signal after t1, the value 1 of the first address signal is collected, Second address signal shows as being updated to 1 by 0.By this process, it is achieved that the transmission of the cross clock domain of the first address signal, Its timing margins is t1.Being easily noted that, in embodiments of the present invention, t1 can also be considered as the first clock signal relative to second The phase contrast of clock signal, namely above-mentioned timing margins is equal to this phase contrast, therefore, if this phase contrast is more than T/2, in other words should Phase contrast is positioned at the first pre-set interval, then timing margins is more than T/2, so that gathering first with the rising edge of second clock signal Address signal can obtain the timing margins of more than half clock cycle.

If the trailing edge using second clock signal gathers the first address signal, and by the first address signal of collecting directly as 3rd address signal, then the sequential of the 3rd address signal can be as shown in the eighth row in Fig. 3.Wherein, believe in the first address After number being updated to 1 by 0, interval time arrives the rising edge of second clock signal after t2, the value 1 of the first address signal is collected, 3rd address signal shows as being updated to 1 by 0.By this process, it is achieved that the transmission of the cross clock domain of the first address signal, Its timing margins is t2.Be easily noted that, in embodiments of the present invention, t2=t1-T/2, therefore, if the first clock signal relative to The phase contrast of second clock signal is positioned at the first pre-set interval, then timing margins is less than T/2, but so that believes with second clock Number rising edge gather the first address signal and cannot obtain the timing margins of more than half clock cycle.

It follows that in embodiments of the present invention, relative to the phase contrast of second clock signal, is positioned at for the first clock signal Situation in one pre-set interval, uses the rising edge of second clock signal to gather the first address signal and can obtain more sufficient sequential Nargin, and this timing margins is at least half clock cycle.Can also be drawn by similar demonstration, in other realities of the present invention Execute in example, the first clock signal is positioned to the situation of the second pre-set interval relative to the phase contrast of second clock signal, use The trailing edge of second clock signal gathers the first address signal can obtain the timing margins of at least half clock cycle, and the present invention exists This does not make tired stating.And then be not required to carry out owing to step S106 or step S108 reading the operation of data from the first memory block The cross clock domain transmission of data, the most i.e. can ensure that first data signal clock zone from the first clock signal There is on the transmission path of the clock zone of second clock signal the timing margins of abundance, thus reach correctly to gather the first data letter Number effect.

It is said that in general, in embodiments of the present invention, it is contemplated that the response time of the memorizer that the first memory block is corresponding and first is deposited The process time of the storage circuit that storage area is corresponding, generally will not direct as shown in the 7th or 8 row in Fig. 3 will collect the One address signal is as the second address signal or the 3rd address signal, but the first address signal stagnant later or many that will collect The individual clock cycle forms the second address signal or the 3rd address signal.On the other hand, in some embodiments of the invention, Process for convenience of for the selection between the second address signal and the 3rd address signal, it is also possible under utilizing second clock signal After the first address signal that fall edge gathers, utilize the rising edge of second clock signal to be again acquired, and then obtain such as Fig. 3 In the 3rd address signal shown in the 9th row so that the 3rd address signal and the second address signal as shown in the 7th row Alignment, to facilitate the same process after selection.Wherein, due to the above-mentioned process again gathered only relate to second clock signal time The transmission of half clock cycle of interval in clock territory, therefore can't produce the problem that timing margins is not enough.

It should be noted that in the above-described embodiments, due to the periodicity of the first clock signal and second clock signal and the two Clock cycle is identical, and therefore the first pre-set interval both could be arranged to (T/2, T), it is also possible to using as comparison other second time Clock signal shifts to an earlier date or delayed one or more clock cycle, namely the border of the first pre-set interval can be added and subtracted any multiple of T, Such as can obtain a first new pre-set interval (-T/2,0) after reducing 1*T, similarly, the second pre-set interval can also be appointed Any multiple of meaning plus-minus T, such as obtain (-T ,-T/2) after reducing 1*T.It should be noted that the first pre-set interval and The above-mentioned change of two pre-set interval should be understood to its equivalent variations, makes this type of embodiment changed and is regarded as in the present invention Protection domain within.

The most still it should be noted that above-described embodiment is only used for the understanding to technical solution of the present invention, can't be to structure of the present invention Become any unnecessary restriction, such as in step S202, for trigger the first address signal update operation can also be the The trailing edge of one clock signal, under this scene, the scope of above-mentioned first pre-set interval and the second pre-set interval can be exchanged. Although additionally, in above-described embodiment, the first clock signal illustrated in fig. 3 illustrate only the situation continuing two clock cycle, so And it is to be appreciated by one skilled in the art that the first clock run signal to the most more clock cycle, technical solution of the present invention institute The effect played is similar with effect.

Give the present invention rising edge individually with the first clock signal by above example or trailing edge triggers and gathers single times The embodiment of the data signal of speed rates, wherein, as an optional application scenarios, these embodiments all can be fitted For SDR internal memory is read process and the collection of data, but this is not meant to the present invention is constituted restriction, such as, The rising edge and the trailing edge that utilize reading DQS trigger in the embodiment gathering the data signal that Double Data Rate transmits simultaneously, permissible It is respectively directed to read the rising edge of DQS and trailing edge uses symmetrical processing mode, thus in another optional application scenarios, Can realize the reading data of DDR internal memory are processed and gathered by the data processing method that the embodiment of the present invention provides, wherein, As shown in Figure 4, in embodiments of the present invention, after step s 102, above-mentioned data processing method can also include:

S402: when the trailing edge of the first clock signal being detected, is written to the first numerical signal in the second memory block with the 4th The storage address that address signal is corresponding is read out data as second, and according to logic of propositions renewal the 4th address signal, wherein, Second memory block for multiple continuous print trailing edges of storage the first clock signal corresponding multiple second be read out data, and multiple Second each being read out in data correspondence in the second memory block uniquely stores address；

S404: if the first clock signal is positioned at the first pre-set interval relative to the phase contrast of second clock signal, then use second Trailing edge collection the 4th address signal of clock signal is to generate the 5th address signal, and stores from second according to second clock signal Storage address read-outing data corresponding with the 5th address signal in district；

S406: if the first clock signal is positioned at the second pre-set interval relative to the phase contrast of second clock signal, then use second Rising edge collection the 4th address signal of clock signal is to generate the 6th address signal, and stores from second according to second clock signal Storage address read-outing data corresponding with the 6th address signal in district.

For this embodiment, the processing mode employed in it is similar with previous embodiment, and its difference is the first number The update cycle of the number of it is believed that can be the half of the clock cycle of second clock signal, namely the Double Data Rate transmission of data signal. Wherein it is possible to be utilized respectively the rising edge of the first clock signal and trailing edge to gather this first data signal, and it is respectively written into In first memory block and the second memory block, but for the sequential logic of address signal, still use single rising edge or The trailing edge that person is single triggers, the most in embodiments of the present invention, and the sequential logic of cross clock domain transmission and aforementioned reality It is consistent for executing example, equally ensure the first data signal from the clock zone of the first clock signal to the clock of second clock signal There is on the transmission path in territory the timing margins of abundance, and then reach correctly to gather the effect of the first data signal.

By above-mentioned embodiment, present invention achieves the correct of the data signal to Double Data Rate transmission and gather, but this is not Realize the sole mode of this purpose.On the other hand, although reached this purpose by the processing mode of above-mentioned symmetry, but Two symmetrical set sequential processing logics typically require circuit and the element arranging double scale in data processing equipment, thus cause More chip logic door number, the area of bigger chip and higher cost.For solving this problem, the present invention provides A kind of more excellent embodiment, as it is shown in figure 5, after step s 102, above-mentioned data processing method can also include:

S502: when the trailing edge of the first clock signal being detected, is written to the first numerical signal in the second memory block with the 4th The storage address that address signal is corresponding is read out data as second, and according to logic of propositions renewal the 4th address signal, wherein, Second memory block for multiple continuous print trailing edges of storage the first clock signal corresponding multiple second be read out data, and multiple Second each being read out in data correspondence in the second memory block uniquely stores address；Wherein,

S504: if the first clock signal is positioned at the first pre-set interval relative to the phase contrast of second clock signal, then using the The rising edge of two clock signals gathers the first address signal after generating the second address signal, and method also includes: during according to second The storage address read-outing data that clock signal is corresponding with the second address signal from the second memory block.

The invention provides a kind of preferred embodiment further the present invention to be explained, it will be appreciated that this is excellent Select embodiment to be intended merely to preferably and describe the present invention, be not intended that and the present invention is limited improperly.

Embodiment 2

According to embodiments of the present invention, additionally providing a kind of data processing method, as shown in Figure 6, the method includes:

S602: obtain the clock signal of system that Memory Controller Hub is corresponding, obtains the reading returned by each in multiple memory chips Data signal and read data strobe (RDS) signal, and read data strobe (RDS) signal is carried out time delay；

S604: according to such as the reading data signal to each correspondence in multiple memory chips of the data processing method in embodiment 1 Process, and using the data that read from the first memory block or the first memory block and the second memory block as in collecting Depositing reading data, wherein, the first data signal is reading data signal, and the first clock signal is the read data strobe (RDS) signal after time delay, Second clock signal is clock signal of system；

S606: the internal memory of each correspondence in the multiple memory chips collected is read data and synchronizes, and after synchronizing Internal memory is read data and is sent to Memory Controller Hub.

In embodiments of the present invention, utilizing will be as the first data as the read data strobe (RDS) signal after the time delay of the first clock signal The reading data signal of signal is written to storage address corresponding with the first address signal in the first memory block, utilizes as second clock The storage address that the clock signal of system of signal is corresponding with the second address signal or the 3rd address signal from the first memory block reads number According to as the second data signal, it is achieved that the transmission of the cross clock domain of reading data signal.Further, in embodiments of the present invention, Use and carry out judging, with Selection utilization system according to the phase contrast between the read data strobe (RDS) Signals & Systems clock signal after time delay The rising edge of clock signal gathers the first address signal to generate above-mentioned second address signal or to utilize clock signal of system Trailing edge gathers the first address signal to generate in the way of above-mentioned 3rd address signal, it is ensured that the first address signal across clock Timing margins on transmission path, territory, and then ensure that the clock zone of reading data signal read data strobe (RDS) signal after time delay is to being There is the timing margins of abundance, it is achieved thereby that correctly gather reading data signal on the transmission path of the clock zone of system clock signal Technique effect, solve due to gather internal memory read data time cross clock domain transmission path on timing margins deficiency cause cannot The correct technical problem gathered.

Furthermore it should be noted that the multiple improvement to its data processing method described in embodiment 1 may be equally applicable for root According to the data processing method of embodiment of the present invention offer, and these improve the effect that can reach similar, its concrete operation principle Being referred to the description in embodiment 1, the present invention does not make tired stating at this.

Embodiment 3

According to embodiments of the present invention, a kind of data processing equipment for implementing above-mentioned data processing method is additionally provided, such as Fig. 7 Shown in, this device includes:

1) the first address generating circuit 702, including the first triggering input and the first address output end, wherein, described first ground Location generative circuit 702 for generating the first ground of mechanical periodicity according to the first clock signal triggering input input from described first Location signal, and export described first address signal from described first address output end；

2) the second address generating circuit 704, including the second triggering input, the 3rd trigger input, the first address input end and Second address output end, described first address input end directly or indirectly connects described first address output end, wherein, described Double-address generative circuit 704 for triggering described first clock signal of input input relative to from described the from described second When the phase contrast of the three second clock signals triggering input input is positioned at the first pre-set interval, use described second clock signal Rising edge gather described first address signal to generate the second address signal, and from described second address output end output described the Double-address signal, when described first clock signal is positioned at the second pre-set interval relative to the phase contrast of described second clock signal, The trailing edge using described second clock signal gathers described first address signal to generate the 3rd address signal, and from described second Address output end exports described 3rd address signal；

3) first storage circuit 706, including the 4th trigger input, the second address input end, the 3rd address input end, first Data input pin and the first data output end, described second address input end connects described first address output end, described 3rd ground Location input connects described second address output end, and wherein, described first storage circuit 706 is for triggering according to from the described 4th Described first clock signal of input input will be written to the from described first data signal of described first data input pin input Storage address corresponding with described first address signal in one memory block, and deposit from described first according to described second clock signal Storage address read-outing data corresponding with described second address signal or described 3rd address signal in storage area, and the data that will read From described first data output end output.

It will be clear that, one of problem to be solved by this invention is to provide a kind of data processing equipment, at least to realize being In system clock zone, internal memory is read the collection of data, thus in some embodiments of the invention, above-mentioned first data signal, first Clock signal and second clock signal can represent respectively returned by internal memory reading data DQ, read data strobe (RDS) signal DQS with And the system clock sys_clk be given by Memory Controller Hub or CPU etc..For another angle, more generally, in the present invention In embodiment, it is also possible to reading DQS is summarised as a clock signal, it is summarised as, by reading DQ, the number that this clock signal is corresponding The number of it is believed that, and sys_clk is summarised as another clock that is identical with the clock signal period reading DQS representative but that not necessarily synchronize Signal, this enforcement having no effect on technical solution of the present invention and the realization of technique effect thereof.Below convenient for statement, by above-mentioned " one Individual clock signal " it is designated as the first clock signal, above-mentioned " another clock signal " is designated as second clock signal, by above-mentioned " one Individual data signal " it is designated as the first data signal.

Implement the data processing equipment provided according to the present invention, the first address generating circuit 702 may be used for according to the first clock letter Number generate mechanical periodicity first address letter, first storage circuit 706 may be used for the first data being believed according to the first clock signal Number it is written to storage address corresponding with the first address signal in the first memory block.Wherein, it is however generally that, this first memory block can To be considered as a storehouse, its concrete manifestation form can be a memorizer, such as one caching, but this is not made by the present invention Limiting, such as, in some embodiments of the invention, this first memory block can be used for representing in a memorizer Divide memory space, the multiple storage addresses etc. preset in other words.

In the first address generating circuit 702, the concrete generating mode of the first address signal can have multiple, such as, and Qi Zhongyi Kind of simplest mode can be the rising edge according to the first clock signal or the first address signal is done cycle accumulor, also by trailing edge That is, when rising edge or the trailing edge of the first clock signal being detected, the first address signal is added 1, and when the first address signal increases It is added to a preset value, when such as 7, again by its zero setting, thus the circulation that from 0 to 7 can be realized, as first Address signal.Certainly, this simply a kind of preferably mode, not unique embodiment, such as, real in some of the present invention Executing in example, above-mentioned cumulative step-length can not also be 1, and then, for generating or update the logic of propositions of the first address signal Can not also be for add up simply, but other calculation, the sequence such as successively decreased or the sequence after Gray code conversion Deng.

Fig. 8 gives the hardware implementation mode of a kind of the first feasible address generating circuit 702, and wherein, this first address generates Circuit 702 includes:

1) it is the first triggering input that the rising edge of the first depositor REG1, REG1 triggers end, and the data output end of REG1 is First address output end；

2) input of first adder ADD1, ADD1 connects the data input pin of REG1, another of ADD1 Input is used for inputting the digital signal representing numerical value " 1 ", and the outfan of ADD1 connects the data input pin of REG1.

Certainly, this kind of example, the present invention can't be constituted restriction, such as, in some other embodiment of the present invention In, the first address generating circuit 702 can also have increasingly complex address generating logic, and identical generation logic can also be right Should different hardware structure etc., this is not construed as limiting by the present invention, but in general, above-mentioned first address generating circuit 702 with The address generating logic of the second address generating circuit 704 is typically corresponding, in order to the first storage circuit 706 can directly by The address signal that first address generating circuit 702 and the 3rd address generating circuit are exported is respectively as write and reads address, and Without making further conversion.

In the first storage circuit 706, can according to the first clock signal the first data signal is written in the first memory block with The storage address that first address signal is corresponding.Wherein, most typically, the storage that the first address signal is corresponding in the first memory block Address can be the address represented by the value of the first address signal, and the such as first address signal is 0, then the storage address of its correspondence can To be [0] storage position in the first memory block, the first address signal is 1, then the storage address of its correspondence can be in the first memory block [1] storage position, but in some embodiments of the invention, the two numerically can also show as difference, such as logical The first address signal obtained after crossing Gray code conversion, the first address signal is 3, then the storage address of its correspondence can also be conversion [2] storage position in front the first memory block indicated by numerical value.

In embodiments of the present invention, the first data can be believed by the first address generating circuit 702 and the first storage circuit 706 Number entrained data write the first memory block successively, keep in these data to utilize the first memory block to realize, in case second Address generating circuit 704 and this first storage circuit 706 perform the read operation to these data, in other words, by first Storage circuit 706 is written to the data of the first memory block can also be designated as being read out data, and owing to the sequential of write operation is corresponding In the first clock signal, and the sequential read is corresponding to second clock signal, such that it is able to realize the first data signal from first time The clock zone of clock signal is to the transmission of the clock zone of second clock signal, and then can adjust the time delay between write and reading to obtain Obtain the timing margins in more sufficient cross clock domain transmission path.

It should be noted that in embodiments of the present invention, performed by the first address generating circuit 702 and the first storage circuit 706 Write operation embodied in sequential both correspond to the first clock signal, but the present invention is not required to limit the two step Successively execution order, wherein, it is however generally that, respective operations is performed for the rising edge or trailing edge utilizing the first clock signal Situation, it is contemplated that believe being triggered the first address just performed by this rising edge or trailing edge in the first address generating circuit 702 Number generation update operation in other words and typically require and consume certain operation time, its timing path to be generally longer than for by first Data signal writes the storage circuit identification to this first address signal of the first memory block, therefore for simultaneously by rising edge or Trailing edge trigger renewal the first address signal operation and to the first address signal corresponding storage address write the first data The operation of signal, the value of the first address signal before the typically renewal of the address of write, and the value after non-update, thus be presented as The renewal of the first address signal that first storage write operation performed by circuit 706 is exported at the first address generating circuit 702 Perform before operation.

Further, in embodiments of the present invention, the first data signal is written to performed by the first storage circuit 706 The operation of the first memory block also relates to according to the collection to the first data signal of first clock signal, thus the first data signal with The corresponding relation of the first clock signal generally can be embodied in utilize this corresponding relation realize to the accurate acquisition of the first clock signal it On, wherein, it is however generally that, this first clock signal can be generally for the correct clock gathering the first data signal and design letter Number, such as returned as the reading DQ of the first data signal by internal memory, the reading DQS as the first clock signal is For to the collection reading DQ.But under this scene, owing to meeting the upper of the reading DQ and reading DQS of DDR agreement regulation Rise, trailing edge aligns respectively, and therefore the first address generating circuit 702 and first under this scene stores performed by circuit 706 According to the first clock signal generate the first address signal and write the first data signal operation, it is also possible to be not simply presented as Directly utilize the rising edge of the first clock signal or trailing edge to perform corresponding operating, but similar and prior art, first to first Clock signal is i.e. read DQS and is carried out delay process, then utilizes the rising edge of the reading DQS after time delay or trailing edge to realize the first ground The generation of location signal and the collection of the first data signal and write.It follows that in one aspect, technical solution of the present invention also may be used To be combined to reach further more excellent technique effect with prior art, it will be appreciated that this type of embodiment is regarded as at this Within the protection domain of invention.On the other hand, what technical solution of the present invention embodied is a kind of inventive concept, and the program is contained Scope should be understood under this design, cover technical solution of the present invention and meet the reasonable prediction of those of ordinary skill All embodiments, it will be appreciated that those of ordinary skill does not has the ability to get rid of those obvious irrational embodiments, thus not The counter productive that should be caused because of the irrational embodiment of some of the present invention and constitute the improper explanation to the present invention.

On the basis of being described above, the data processing equipment provided according to embodiments of the present invention, it is different from prior art, permissible First the first clock signal is judged relative to the phase contrast of second clock signal, wherein, preset if this phase contrast is positioned at first In interval, then second clock can be used in the second address generating circuit 704, in the selection circuit shown in such as Fig. 8 to believe Number rising edge gather the first address signal to generate the second address signal, and according to second clock signal from the first memory block with The storage address read-outing data that second address signal is corresponding, if this phase contrast is positioned at the second pre-set interval, then can be on the second ground Location generative circuit 704 or above-mentioned selection circuit use the trailing edge of second clock signal gather the first address signal to generate the Three address signals, and according to the storage address read-outing data corresponding with the 3rd address signal from the first memory block of second clock signal.

Wherein, corresponding with the write operation performed by the first storage circuit 706, this first storage circuit 706 can also be permissible According to the storage address read-outing data that second clock signal is corresponding with the second address signal or the 3rd address signal from the first memory block, Wherein, it is derived from corresponding with the writing address of the first data signal first due to this second address signal or the 3rd address signal Address signal, therefore can utilize the second address signal or the 3rd address signal is new first number by the data reconstruction of reading The number of it is believed that, is designated as the second data signal, and wherein, the first data signal is identical with the content of the second data signal, but in sequential On, the former corresponds to the first clock signal, and the latter is corresponding to second clock signal, thus completes the biography of the cross clock domain of data Defeated.

On the basis of the cross clock domain realizing data transmits, the embodiment of the present invention can be by the second address generating circuit 704 Selection between rising edge or the trailing edge of the second clock signal used realizes well-to-do cross clock domain transmission path Timing margins, and then reach the technique effect that data are correctly gathered.It is evidenced from the above discussion that, in embodiments of the present invention, It is similar to prior art, again may be by the first clock signal and realize the accurate acquisition to the first data signal, because this timing is abundant During the only possible appearance of defect that degree is not enough other cross clock domain transmission in embodiments of the present invention, namely occur in the One address signal from the clock zone of the first clock signal to the transmission path of the clock zone of second clock signal.Wherein, for For one address signal, no matter it utilizes the rising edge of the first clock signal or trailing edge is updated, each of which value The effectively persistent period is a clock cycle, owing to the clock cycle of second clock signal and the first clock signal is identical, and the Differ half clock cycle between rising edge and the trailing edge of two clock signals, therefore utilize the rising edge of second clock signal with When first address signal is acquired by trailing edge respectively, certainly exist one of which acquisition mode its gather time point relative to The time difference of the starting point of above-mentioned effective persistent period, namely the first address signal from the clock zone of the first clock signal to second time The clock zone of clock signal carries out the timing margins of cross clock domain transmission more than half clock cycle, otherwise in above-mentioned effective persistent period Second half section in there will be no rising edge or the trailing edge of any one second clock signal, this will cause before this second half section Rise/fall along and this second half section after decline/rising edge between interval more than half clock cycle, thus when not meeting second Rising edge in clock signal and the sequential feature of trailing edge.

Under above-mentioned scene, the first pre-set interval described in the second address generating circuit 704 could be arranged to (T/2, T), the Two pre-set interval could be arranged to (0, T/2), and wherein, T represents the clock cycle of second clock signal.By above-mentioned setting, I.e. may insure that the first address signal to such an extent as to the first data signal at least have T/2 cross clock domain transmission timing margins.

As shown in the 1st and 3 row in Fig. 3, the first address generating circuit 702 can be in the rising the first clock signal being detected Along time, update the first address signal according to logic of propositions, wherein, for ease of describing, the logic of propositions shown in Fig. 3 is simply It is defined as the first address signal after updating and adds 1, certainly, in some other reality of the present invention equal to the first address signal before updating Execute in example, it is also possible to define other increasingly complex logic of propositions, this enforcement having no effect on technical solution of the present invention and technology thereof The realization of effect, this is not limited in any way by the present invention.

As shown in the 1st to 5 row in Fig. 3, can be at the rising edge the first clock signal being detected in the first storage circuit 706 Time, the first numerical signal is written to storage address corresponding with the first address signal in the first memory block and is read out number as first According to.Wherein, when first rising edge of the first clock signal shown in the 1st row arrives, the first numerical value letter shown in the 2nd row Number value be a, the value of the first address signal shown in the 3rd row is in by the renewal process of 0 to 1, in conjunction with foregoing teachings, by Certain time is needed to complete in this renewal operation, therefore when above-mentioned first rising edge arrives, the first corresponding address The value of signal remains as 0, and therefore as shown in Fig. 3 the 4th row, numerical value a can be written to the first storage by the first storage circuit 706 Storage address [0] in district, the numerical value a being simultaneously stored in may act as being read out data, until data a are by the first storage circuit 706 read.Similarly, when second rising edge of the first clock signal arrives, the first storage circuit 706 can be by numerical value b The storage address [1] being written in the first memory block, and after numerical value a, numerical value b also will become and be read out data until should It is read out data to be read.

Further, as the 3rd in Fig. 3,6,7 and 8 are shown in row, in the second address generating circuit 704, it is possible to use First address signal is acquired by rising edge or the trailing edge of second clock signal, to obtain the second address signal or the 3rd address Signal.For the quality of both modes, by the collection that 0 is updated to the address value 1 after 1 can be with the first address signal Example compares.

It follows that in embodiments of the present invention, relative to the phase contrast of second clock signal, is positioned at for the first clock signal Situation in one pre-set interval, uses the rising edge of second clock signal to gather the first address signal and can obtain more sufficient sequential Nargin, and this timing margins is at least half clock cycle.Can also be drawn by similar demonstration, in other realities of the present invention Execute in example, the first clock signal is positioned to the situation of the second pre-set interval relative to the phase contrast of second clock signal, use The trailing edge of second clock signal gathers the first address signal can obtain the timing margins of at least half clock cycle, and the present invention exists This does not make tired stating.And then the operation owing to reading data by the first storage circuit 706 from the first memory block is not required to count According to cross clock domain transmission, the most i.e. can ensure that the first data signal from the clock zone of the first clock signal to There is on the transmission path of the clock zone of second clock signal the timing margins of abundance, thus reach correctly to gather the first data signal Effect.

The most still it should be noted that above-described embodiment is only used for the understanding to technical solution of the present invention, can't be to structure of the present invention Become any unnecessary restriction, such as in the first address generating circuit 702, for triggering the renewal operation of the first address signal Can also be the trailing edge of the first clock signal, under this scene, the model of above-mentioned first pre-set interval and the second pre-set interval Enclose and can exchange.Although additionally, the first clock signal illustrated in fig. 3 illustrate only lasting two clock weeks in above-described embodiment The situation of phase, but it is to be appreciated by one skilled in the art that the first clock run signal to the most more clock cycle, this The effect that bright technical scheme is played is similar with effect.

Give the present invention rising edge individually with the first clock signal by above example or trailing edge triggers and gathers single times The embodiment of the data signal of speed rates, wherein, as an optional application scenarios, these embodiments all can be fitted For SDR internal memory is read process and the collection of data, but this is not meant to the present invention is constituted restriction, such as, The rising edge and the trailing edge that utilize reading DQS trigger in the embodiment gathering the data signal that Double Data Rate transmits simultaneously, permissible It is respectively directed to read the rising edge of DQS and trailing edge uses symmetrical processing mode, thus in another optional application scenarios, Can realize the reading data of DDR internal memory are processed and gathered by the data processing equipment that the embodiment of the present invention provides, wherein, Alternatively, in embodiments of the present invention, above-mentioned data processing equipment can further include:

1) the 3rd address generating circuit, corresponding with the first address generating circuit 702, trigger input and the 3rd address including the 5th Outfan, wherein, the first address generating circuit 702, for when the rising edge of the first clock signal being detected, is patrolled according to presetting Collecting and update the first address signal, the 3rd address generating circuit is for detecting that the first clock from the 5th triggering input input is believed Number trailing edge time, according to logic of propositions update the 4th address signal；

2) second storage circuit, with first storage circuit 706 corresponding, including the 6th triggering input, the 4th address input end, 5th address input end, the second data input pin and the second data output end, the 4th address input end connects the 3rd address output end, 5th address input end connects the second address output end；Wherein,

First numerical signal, for when the rising edge of the first clock signal being detected, is written to first by the first storage circuit 706 Storage address corresponding with the first address signal in memory block is read out data as first, and wherein, the first memory block is used for storing Multiple first that multiple continuous print rising edges of the first clock signal are corresponding is read out data, and multiple first is read out in data Each correspondence in the first memory block uniquely stores address；

Second storage circuit, will be from for when detecting from the trailing edge of the first clock signal that the 6th triggers input input First numerical signal of two data input pin inputs is written to storage address conduct corresponding with the 4th address signal in the second memory block Second is read out data, and wherein, the second memory block is for corresponding multiple of multiple continuous print trailing edges of storage the first clock signal Second is read out data, and multiple second each being read out in data correspondence in the second memory block uniquely stores address.

By above-mentioned embodiment, present invention achieves the correct of the data signal to Double Data Rate transmission and gather.Below in conjunction with Some embodiments provide some more specifically embodiment, especially hardware embodiment of the present invention, thus at above-mentioned data Reason device can be arranged in the PHY module of Memory Controller Hub, wherein, with respect to logic controller and write this controller The embodiment of software logic, hardware embodiment can obtain more excellent response speed and lower power consumption.Wherein, optional Ground, in embodiments of the present invention, the second address generating circuit 704 may include that

1) decision circuitry, including control output end, is used for exporting control signal, wherein, in the first clock signal relative to second When the phase contrast of clock signal is positioned at the first pre-set interval, control signal is in the first state, the first clock signal relative to When the phase contrast of second clock signal is positioned at the second pre-set interval, control signal is in the second state；

2) selection circuit, an input of selection circuit is the first address input end, and another input of selection circuit is Three trigger input, and another input of selection circuit is the control input connecting control output end, wherein, control input End is used for inputting control signal, and when control signal is in the first state, the outfan output of selection circuit uses second clock letter Number the first address signal of collecting of rising edge, when control signal is in the second state, the outfan output of selection circuit makes The first address signal collected with the trailing edge of second clock signal, wherein, the outfan of selection circuit collects for output The first address signal；

3) the 4th address generating circuit, an input of the 4th address generating circuit connects the 3rd triggering input, the 4th address Another input of generative circuit connects the outfan of selection circuit, and the outfan of the 4th address generating circuit is that the second address is defeated Go out end.

Specifically, in embodiments of the present invention, above-mentioned first address generating circuit 702 may include that

1) the first depositor, it is the first triggering input that the rising edge of the first depositor triggers end, the data output of the first depositor End is the first address output end；

2) first adder, an input of first adder connects the data input pin of the first depositor, first adder Another input is used for inputting the digital signal representing numerical value " 1 ", and the outfan of first adder connects the number of the first depositor According to input；

Wherein, above-mentioned 3rd address generating circuit may include that

1) the second depositor, it is the 5th triggering input that the trailing edge of the second depositor triggers end, the data output of the second depositor End is the 3rd address output end；

2) second adder, an input of second adder connects the data input pin of the second depositor, second adder Another input is used for inputting the digital signal representing numerical value " 1 ", and the outfan of second adder connects the number of the second depositor According to input；

Wherein, the 4th address generating circuit may include that

1) the 3rd depositor, the rising edge of the 3rd depositor triggers end and connects the 3rd triggering input, and the data of the 3rd depositor are defeated Going out end is the second address output end；

2) the 3rd adder, an input of the 3rd adder connects the data input pin of the 3rd depositor, the 3rd adder Another input is used for inputting the digital signal representing numerical value " 1 ", and the outfan of the 3rd adder connects the number of the 3rd depositor According to input；

3) comparator, including first comparing input, second comparing input and compare outfan, first to compare input direct Or it is indirectly connected with the outfan of selection circuit, second compares input directly or indirectly connects the data output end of the 3rd depositor, Relatively outfan is connected to the 3rd depositor, wherein, compares input and second first and compares the numeral letter that input is received Time number different, the 3rd depositor normally works, and compares input and second first and compares input received digital signal phase Meanwhile, the 3rd depositor quits work；

4) N number of 4th depositor, the outfan and first being connected on selection circuit compares between input, N number of 4th depositor In the rising edge of each trigger end and connect the 3rd triggering input, wherein, N >=0.

More specifically, as a kind of feasible embodiment, above-mentioned selection circuit may include that

1) selector, including the first selection input, the second selection input, selects outfan and selects to control end, selecting to control End processed, for controlling input, is used for receiving control signal, wherein, when control signal is in the first state, selects outfan even Connect the first selection input, when control signal is in the second state, select outfan to connect the second selection input；

2) the 5th depositor, the rising edge of the 5th depositor triggers end and connects the 3rd triggering input, and the data of the 5th depositor are defeated Entering end and connect the first address input end, the data output end of the 5th depositor connects the first selection input；

3) the 6th depositor and the 7th depositor, the trailing edge of the 6th depositor triggers the rising edge of end and the 7th depositor and triggers end Connecting the 3rd triggering input, the data input pin of the 6th depositor connects the first address input end, and the data of the 6th depositor are defeated Going out end and connect the data input pin of the 7th depositor, the data output end of the 7th depositor connects the second selection input.

Optionally, in addition, in embodiments of the present invention, above-mentioned decision circuitry may include that

1) the 8th depositor, the data input pin of the 8th depositor is for input the first clock signal, the outfan of the 8th depositor For exporting indication signal；

2) chronotron, the input of chronotron is used for inputting rising edge and triggers signal, and the outfan of chronotron connects the 8th depositor Rising edge trigger input, wherein, rising edge triggers the rising edge alignment of rising edge and the second clock signal of signal, time delay The delay value of device is according to indication signal increasing or decreasing.

By above-described embodiment, technical solution of the present invention and operation principle thereof are set forth, but it should be noted that on State embodiment and be only used for the convenient understanding to technical solution of the present invention, and should not be considered as limitation of the invention, such as, at this In some embodiments of invention, rising edge triggers signal and can be also used for the gating of the first clock signal, and wherein, rising edge triggers The width of signal can be arranged according to the length of the continuous print data entrained by the first data signal, and this is not construed as limiting by the present invention. Additionally, technical solution of the present invention can be combined with other feasible technological means to reach more excellent effect, such as, for further Ground reduces signal and inverts the interference brought, and as a kind of feasible mode, in embodiments of the present invention, above-mentioned data process dress Put and can also include:

1) the first gray code converter, is connected between the first address input end and the first address output end；

2) the second gray code converter, the data output end and second being connected to the 3rd depositor compares between input.

The invention provides some preferred embodiments further the present invention to be explained, it will be appreciated that this is excellent Select embodiment to be intended merely to preferably and describe the present invention, be not intended that and the present invention is limited improperly.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for those skilled in the art For, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, etc. With replacement, improvement etc., should be included within the scope of the present invention.

Claims

1. a data processing method, it is characterised in that including:

Obtain the first data signal, the first clock signal and second clock signal, wherein, described first data signal and institute State the first clock signal corresponding, the clock cycle phase of the clock cycle of described first clock signal and described second clock signal With；

The first address signal of mechanical periodicity is generated according to described first clock signal, and will according to described first clock signal Described first data signal is written in the first memory block the storage address corresponding with described first address signal；

If described first clock signal is positioned at the first pre-set interval relative to the phase contrast of described second clock signal, then make With rising edge described first address signal of collection of described second clock signal to generate the second address signal, and according to described The storage address read-outing data that second clock signal is corresponding with described second address signal from described first memory block；

If described first clock signal is positioned at the second pre-set interval relative to the phase contrast of described second clock signal, then make With trailing edge described first address signal of collection of described second clock signal to generate the 3rd address signal, and according to described The storage address read-outing data that second clock signal is corresponding with described 3rd address signal from described first memory block；

Using the data of reading as the second data signal.

Method the most according to claim 1, it is characterised in that

Described the first address signal generating mechanical periodicity according to described first clock signal includes: detecting described first During the rising edge of clock signal, update described first address signal according to logic of propositions；

Described according to described first clock signal, described first data signal is written in the first memory block and described first ground The storage address that location signal is corresponding includes: when the rising edge of described first clock signal being detected, by described first numerical value Signal is written to storage address corresponding with described first address signal in described first memory block and is read out data as first, Wherein, described first memory block for store that multiple continuous print rising edges of described first clock signal are corresponding multiple first It is read out data, and the plurality of first each being read out in data correspondence in described first memory block is uniquely deposited Storage address；Wherein,

Described first pre-set interval is (T/2, T), and described second pre-set interval is (0, T/2), and wherein, T represents described The clock cycle of second clock signal.

Method the most according to claim 2, it is characterised in that described acquisition the first data signal, the first clock signal and After second clock signal, also include:

When the trailing edge of described first clock signal being detected, described first numerical signal is written in the second memory block The storage address corresponding with the 4th address signal is read out data as second, and updates described the according to described logic of propositions Four address signals, wherein, described second memory block is for storing multiple continuous print trailing edges pair of described first clock signal Multiple second answered is read out data, and the plurality of second each being read out in data is in described second memory block Correspondence uniquely stores address；

If described first clock signal is positioned at described first pre-set interval relative to the phase contrast of described second clock signal, Then use described second clock signal trailing edge gather described first address signal to generate the 5th address signal, and according to The storage address read-outing data that described second clock signal is corresponding with described 5th address signal from described second memory block；

If described first clock signal is positioned at described second pre-set interval relative to the phase contrast of described second clock signal, Then use described second clock signal rising edge gather described first address signal to generate the 6th address signal, and according to The storage address read-outing data that described second clock signal is corresponding with described 6th address signal from described second memory block.

When the trailing edge of described first clock signal being detected, described first numerical signal is written in the second memory block The storage address corresponding with the 4th address signal is read out data as second, and updates described the according to described logic of propositions Four address signals, wherein, described second memory block is for storing multiple continuous print trailing edges pair of described first clock signal Multiple second answered is read out data, and the plurality of second each being read out in data is in described second memory block Correspondence uniquely stores address；Wherein,

If described first clock signal is positioned at the first pre-set interval relative to the phase contrast of described second clock signal, then exist The rising edge of described use described second clock signal gathers described first address signal after generating the second address signal, Described method also includes: according to described second clock signal from described second memory block corresponding with described second address signal Storage address read-outing data.

5. a data processing method, it is characterised in that including:

Obtain the clock signal of system that Memory Controller Hub is corresponding, obtain the reading returned by each in multiple memory chips The number of it is believed that and read data strobe (RDS) signal, and described read data strobe (RDS) signal is carried out time delay；

According to each in the plurality of memory chip of the data processing method as according to any one of Claims 1-4 The reading data signal of individual correspondence processes, and will read from the first memory block or the first memory block and the second memory block The data gone out read data as the internal memory collected, and wherein, the first data signal is described reading data signal, the first clock Signal is the read data strobe (RDS) signal after time delay, and second clock signal is described clock signal of system；

The described internal memory of each correspondence in the plurality of memory chip collected is read data synchronize, and will be with Internal memory after step is read data and is sent to Memory Controller Hub.

6. a data processing equipment, it is characterised in that including:

First address generating circuit, including the first triggering input and the first address output end, wherein, described first address Generative circuit for generating the first address of mechanical periodicity according to the first clock signal triggering input input from described first Signal, and export described first address signal from described first address output end；

Second address generating circuit, including the second triggering input, the 3rd triggers input, the first address input end and the Double-address outfan, described first address input end directly or indirectly connects described first address output end, wherein, described Second address generating circuit for triggering described first clock signal of input input relative to from described from described second When the phase contrast of the 3rd second clock signal triggering input input is positioned at the first pre-set interval, when using described second The rising edge of clock signal gathers described first address signal to generate the second address signal, and from described second address output end Export described second address signal, be positioned in described first clock signal relative to the phase contrast of described second clock signal Time in two pre-set interval, the trailing edge of described second clock signal is used to gather described first address signal to generate the 3rd ground Location signal, and export described 3rd address signal from described second address output end；

First storage circuit, triggers input, the second address input end, the 3rd address input end, the first number including the 4th According to input and the first data output end, described second address input end connects described first address output end, and the described 3rd Address input end connects described second address output end, and wherein, described first storage circuit is for touching according to from the described 4th Described first clock signal sending out input input will be write from described first data signal of described first data input pin input Enter in the first memory block the storage address corresponding with described first address signal, and according to described second clock signal from Storage address read-outing data corresponding with described second address signal or described 3rd address signal in described first memory block, And the data read are exported from described first data output end.

Device the most according to claim 6, it is characterised in that also include:

3rd address generating circuit, corresponding with described first address generating circuit, trigger input and the 3rd ground including the 5th Location outfan, wherein, described first address generating circuit is used for when the rising edge of described first clock signal being detected, Updating described first address signal according to logic of propositions, described 3rd address generating circuit is for detecting from the described 5th When triggering the trailing edge of described first clock signal that input inputs, update the 4th address signal according to described logic of propositions；

Second storage circuit, with described first storage circuit corresponding, including the 6th triggering input, the 4th address input end, 5th address input end, the second data input pin and the second data output end, described 4th address input end connects described the Three address output ends, described 5th address input end connects described second address output end；Wherein,

Described first storage circuit is for when the rising edge of described first clock signal being detected, by described first numerical value letter Number being written to storage address corresponding with described first address signal in described first memory block is read out data as first, Wherein, described first memory block for store that multiple continuous print rising edges of described first clock signal are corresponding multiple first It is read out data, and the plurality of first each being read out in data correspondence in described first memory block is uniquely deposited Storage address；

Described second storage circuit is for detecting from the described 6th described first clock signal triggering input input During trailing edge, will be written in the second memory block and institute from described first numerical signal of described second data input pin input The storage address stating the 4th address signal corresponding is read out data as second, and wherein, described second memory block is used for storing Multiple second that multiple continuous print trailing edges of described first clock signal are corresponding is read out data, and the plurality of second treats Each correspondence in described second memory block read in data uniquely stores address.

Device the most according to claim 7, it is characterised in that described first pre-set interval is (T/2, T), described second pre- If interval is (0, T/2), wherein, T represents the clock cycle of described second clock signal.

9. according to the device described in claim 7 or 8, it is characterised in that described second address generating circuit includes:

Decision circuitry, including control output end, is used for exporting control signal, wherein, relative in described first clock signal When the phase contrast of described second clock signal is positioned at described first pre-set interval, described control signal is in the first state, When described first clock signal is positioned at described second pre-set interval relative to the phase contrast of described second clock signal, institute State control signal and be in the second state；

Selection circuit, an input of described selection circuit is described first address input end, described selection circuit another One input is described 3rd triggering input, and another input of described selection circuit exports for connecting described control The control input of end, wherein, described control input is used for inputting described control signal, is in described control signal During described first state, the outfan output of described selection circuit uses the rising edge of described second clock signal to collect First address signal, when described control signal is in described second state, the outfan output of described selection circuit uses The first address signal that the trailing edge of described second clock signal collects, wherein, the outfan of described selection circuit is used for The first address signal collected described in output；

4th address generating circuit, an input of described 4th address generating circuit connects the described 3rd and triggers input, Another input of described 4th address generating circuit connects the described outfan of described selection circuit, described 4th address The outfan of generative circuit is described second address output end.

Device the most according to claim 9, it is characterised in that

Described first address generating circuit includes: the first depositor, and it is described that the rising edge of described first depositor triggers end First triggers input, and the data output end of described first depositor is described first address output end；First adder, One input of described first adder connects the described data input pin of described first depositor, described first adder Another input be used for inputting the digital signal representing numerical value " 1 ", the outfan of described first adder connects described The data input pin of the first depositor；

Described 3rd address generating circuit includes: the second depositor, and it is described that the trailing edge of described second depositor triggers end 5th triggers input, and the data output end of described second depositor is described 3rd address output end；Second adder, One input of described second adder connects the described data input pin of described second depositor, described second adder Another input be used for inputting the digital signal representing numerical value " 1 ", the outfan of described second adder connects described The data input pin of the second depositor；

Described 4th address generating circuit includes: the 3rd depositor, and the rising edge of described 3rd depositor triggers end and connects institute Stating the 3rd triggering input, the data output end of described 3rd depositor is described second address output end；3rd adder, One input of described 3rd adder connects the described data input pin of described 3rd depositor, described 3rd adder Another input be used for inputting the digital signal representing numerical value " 1 ", the outfan of described 3rd adder connects described The data input pin of the 3rd depositor；Comparator, including first comparing input, second comparing input and compare output End, described first compares input directly or indirectly connects the described outfan of described selection circuit, and described second is the most defeated Entering end and directly or indirectly connect the described data output end of described 3rd depositor, the described outfan that compares is connected to described the Three depositors, wherein, comparing input described first, to compare input received digital signal from described second different Time, described 3rd depositor normally works, and compares input described first and compares what input was received with described second When digital signal is identical, described 3rd depositor quits work；N number of 4th depositor, is connected on the institute of described selection circuit Stating outfan and compare between input with described first, the rising edge of each in described N number of 4th depositor triggers end Connect the described 3rd and trigger input, wherein, N=0.

11. devices according to claim 10, it is characterised in that also include:

First gray code converter, is connected between described first address input end and described first address output end；

Second gray code converter, the described data output end being connected to described 3rd depositor compares input with described second Between end.

12. devices according to claim 9, it is characterised in that described selection circuit includes:

Selector, including the first selection input, the second selection input, selects outfan and selects to control end, described Selecting to control end is described control input, is used for receiving described control signal, wherein, is in institute in described control signal When stating the first state, described selection outfan connects described first and selects input, is in described the in described control signal During two-state, described selection outfan connects described second and selects input；

5th depositor, the described 3rd triggering input of rising edge triggering end connection of described 5th depositor, the described 5th The data input pin of depositor connects described first address input end, and the data output end of described 5th depositor connects described First selects input；

6th depositor and the 7th depositor, the trailing edge of described 6th depositor triggers the upper of end and described 7th depositor Rising along triggering the described 3rd triggering input of end connection, the data input pin of described 6th depositor connects described first address Input, the data output end of described 6th depositor connects the data input pin of described 7th depositor, and the described 7th posts The data output end of storage connects described second and selects input.

13. devices according to claim 9, it is characterised in that described decision circuitry includes:

8th depositor, the data input pin of described 8th depositor is used for inputting described first clock signal, and the described 8th The outfan of depositor is used for exporting indication signal；

Chronotron, the input of described chronotron is used for inputting rising edge and triggers signal, and the outfan of described chronotron connects The rising edge of described 8th depositor triggers input, and wherein, described rising edge triggers the rising edge and described second of signal The rising edge alignment of clock signal, the delay value of described chronotron is according to described indication signal increasing or decreasing.

14. devices according to claim 13, it is characterised in that described rising edge triggers signal and is additionally operable to described first clock letter Number gating, wherein, described rising edge trigger signal width according to the continuous print number entrained by described first data signal According to length arrange.