CN104778137A - Multi-channel analog real-time acquisition and caching method based on AVALON bus - Google Patents
Multi-channel analog real-time acquisition and caching method based on AVALON bus Download PDFInfo
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- CN104778137A CN104778137A CN201510204941.1A CN201510204941A CN104778137A CN 104778137 A CN104778137 A CN 104778137A CN 201510204941 A CN201510204941 A CN 201510204941A CN 104778137 A CN104778137 A CN 104778137A
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Abstract
The invention relates to a multi-channel analog real-time acquisition and caching method based on an AVALON bus, belonging to the technical field of analog real-time acquisition and caching. The multi-channel analog real-time acquisition and caching method aims at solving the problem that a control process of an SPI (Serial Peripheral Interface) single-channel AD (Analog/Digital) chip is complicated and easily causes program bugs in a process of orienting to multi-channel signal acquisition. According to the multi-channel analog real-time acquisition and caching method, a main port according with the AVALON bus is established by using AVALON bus resources, and a distinct structure can be achieved by taking the AVALON bus as an internal interconnection bus and by using the AVALON bus and extensible resources on the AVALON bus, so that the development period is greatly shortened, the control process is simplified, and thus the occurrence probability of bugs is further reduced. Besides, a microprocessor Nios II of an FPGA (Field Programmable Gate Array) can be subjected to data interaction and control with the AVALON bus and all the logical modules on the AVALON bus.
Description
Technical field
The invention belongs to analog quantity Real-time Collection and caching technology field.
Background technology
Analog acquisition is the task that current most of hardware circuit has all needed.At present, analog acquisition has needed 2 tasks usually: one is the current data of Real-time Collection, is used for monitoring in real time; Two is that buffer memory image data is for ex-post analysis.The serial AD of SPI interface has the relatively little feature of volume, and a lot of serial AD chip all has SPI interface at present.For when needing to limit collecting device volume requirement, adopting the serial AD with SPI interface to complete multichannel analog amount collection design is the scheme relatively commonly used.Altera corp has devised the kernel meeting SPI protocol, can be connected data interaction by AVALON from machine interface with the peripheral hardware AVALON bus.User only needs to be arranged by SOPCBuilder configuration wizard the parameters such as SPI (Serial Peripheral interface, serial peripheral equipment) kernel master slave mode, data bit width, clock frequency, appointment time delay just can complete accurate control to peripheral hardware.
But in the program, need to control the opening and closing of multichannel analog switch, write the AD analog acquisition of SPI interface logic control and control the tasks such as image data buffer memory.Write steering logic in the conventional mode, design process is complicated, and easily occurs bug because control procedure is loaded down with trivial details.
Summary of the invention
The present invention realizes in multi-channel signal acquiring process based on SPI interface single channel A/D chip to solve, and the loaded down with trivial details problem easily occurring bug of control procedure, now provides the multichannel analog amount Real-time Collection based on AVALON bus and caching method.
Based on multichannel analog amount Real-time Collection and the caching method of AVALON bus, the method realizes based on the multichannel analog amount Real-time Collection of AVALON bus and caching system, this system is embedded in FPGA, it comprises: 32 tunnel analog quantity Real-time Collections and control module, AD currency register module, fifo module, time interval controls module, the main SPI module of AD currency to FIFO control module, AD and the main SPI module of analog switch, and above-mentioned module is all articulated in AVALON bus; The method comprises: analog quantity real-time collecting method and the real-time caching method of analog quantity;
Analog quantity real-time collecting method, comprises the following steps:
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module write data to the transmitter register of the main SPI module of analog switch, and the main SPI module of described analog switch opens the wherein a-road-through road of analog switch;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module send the main SPI transmitter register address of AD, and write data to the main SPI module of AD, start AD conversion chip, carry out AD conversion to the simulating signal of input AD conversion chip;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module send the main SPI receiving register address of AD, and send and read enable signal;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module read the AD conversion value that AD conversion chip obtains;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module send the current register address of present day analog switch open wireless tunnel, and the AD conversion value of reading are write in this actual registers, complete the analog acquisition in a-road-through road;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module upgrade the write data of transmitter register in the main SPI module of analog switch, repeat the analog acquisition that above-mentioned analog quantity real-time collecting method carries out next paths;
The real-time caching method of analog quantity, comprises the following steps:
AD currency in FPGA to FIFO control module sends the status register address of FIFO;
AD currency in FPGA reads data to FIFO control module from AD currency register module;
AD currency in FPGA to FIFO control module sends the data register address of fifo module, and writes in the data register of fifo module by data;
AD currency in FPGA reads the status register of fifo module to FIFO control module, judges that whether FIFO is full, if then stop writing data to fifo module; Otherwise repeat the real-time caching method of above-mentioned analog quantity, continue to write data to fifo module;
Data are write External memory equipment by fifo module, complete the buffer memory of present day analog amount.
The present invention relates to a kind of multichannel analog amount Real-time Collection based on AVALON bus and buffer control method, this method can be applied in multichannel analog data acquisition system (DAS).The method of the invention utilizes AVALON bus resource, build the master port meeting AVALON bus, with AVALON bus for interconnected bus, extended resources on AVALON bus and line thereof is utilized to accomplish clear in structure, greatly shorten the construction cycle, simplify control procedure, and then reduce leak appearance.In addition, the microprocessor Nios II of FPGA self also can carry out data interaction and control by logic modules all on AVALON bus and line.The collection of real time modelling amount is carried out with the AD conversion chip controlling to have SPI interface, translation data is carried out arbitrary time span is stored in buffer memory corresponding to each passage simultaneously, the timesharing switching of analog channel, AD conversion control, Real-time Collection and data buffer storage can be realized, the IP kernel form meeting ALTERA Corporation Instructions exists, and actual application value is high, has flexible and convenient to use, stable and reliable for performance, control procedure is simple, highly versatile, the feature such as to be widely used.The present invention is generated the IP kernel meeting AVALON bus protocol specification by SOPC Builder, user by the parameter define channel number of the corresponding IP kernel of configuration, can control switching rate, have very strong dirigibility and versatility.
Accompanying drawing explanation
Fig. 1 is the overall plan block diagram of analog quantity real-time collecting method;
Fig. 2 is that hyperchannel switches AD conversion logic state figure;
Fig. 3 is analog quantity real-time caching method steering logic block diagram;
Fig. 4 is that each passage AD currency is to fifo logic constitutional diagram.
Embodiment
Embodiment one: with reference to Fig. 1, Fig. 2, Fig. 3 and Fig. 4 illustrates present embodiment, the multichannel analog amount Real-time Collection based on AVALON bus described in present embodiment and caching method, the method realizes based on the multichannel analog amount Real-time Collection of AVALON bus and caching system, this system is embedded in FPGA, it comprises: 32 tunnel analog quantity Real-time Collection and control modules 1, AD currency register module 2, fifo module 3, time interval controls module 4, AD currency is to FIFO control module 5, the main SPI module 6 of AD and the main SPI module 7 of analog switch, above-mentioned module is all articulated in AVALON bus, the method comprises: analog quantity real-time collecting method and the real-time caching method of analog quantity,
Analog quantity real-time collecting method, comprises the following steps:
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module 1 write data to the transmitter register of the main SPI module 7 of analog switch, and the main SPI module 7 of described analog switch opens the wherein a-road-through road of analog switch;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module 1 send the main SPI transmitter register address of AD, and write data to the main SPI module 6 of AD, start AD conversion chip, carry out AD conversion to the simulating signal of input AD conversion chip;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module 1 send the main SPI receiving register address of AD, and send and read enable signal;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module 1 read the AD conversion value that AD conversion chip obtains;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module 1 send the current register address of present day analog switch open wireless tunnel, and the AD conversion value of reading are write in this actual registers, complete the analog acquisition in a-road-through road;
In the main SPI module 7 of FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module 1 pair of analog switch, the write data of transmitter register upgrade, and repeat the analog acquisition that above-mentioned analog quantity real-time collecting method carries out next paths;
The real-time caching method of analog quantity, comprises the following steps:
AD currency in FPGA to FIFO control module 5 sends the status register address of FIFO;
AD currency in FPGA reads data to FIFO control module 5 from AD currency register module 2;
AD currency in FPGA to FIFO control module 5 sends the data register address of fifo module 3, and data is write in the data register of fifo module 3;
AD currency in FPGA reads the status register of fifo module 3 to FIFO control module 5, judge that whether FIFO is full, if then stop writing data to fifo module 3; Otherwise repeat the real-time caching method of above-mentioned analog quantity, continue to write data to fifo module 3;
Data are write External memory equipment by fifo module 3, complete the buffer memory of present day analog amount.
In present embodiment, analog quantity real-time collecting method comprises passage bridge and analog quantity Real-time Collection two parts.
The method carries out passage bridge with scan mode control simulation switch, gives AD conversion chip conversion successively by each road analog quantity.The transformation result of each passage is placed in 32 mutual independently corresponding currency registers respectively.The real-time caching method of analog quantity is responsible for that the analog quantity of each passage is carried out buffer memory and is done ex-post analysis for user.If user needs the real time modelling value knowing certain passage, only need by being articulated in currency register corresponding to microprocessor access in AVALON bus.
Cut-offfing of passage has been controlled by the main SPI module 7 of corresponding analog switch, and system needs the main SPI of the analog switch data comprising switch control rule information sent in a serial fashion in AVALON bus to complete chip controls.In like manner, AD conversion chip then completes whole AD conversion process by the main SPI of AD corresponding to Systematical control.
For reaching maximum flexibility ratio, each passage of analog switch has an AD data buffer storage control system.AD data buffer storage control system is responsible for constantly reading the data in AD currency register, carries out buffer memory according in the time interval write FIFO of definition.
The AD data buffer storage control system of every each passage comprises fifo module 3, time interval controls module 4, AD currency register module 2 and AD currency to FIFO control module 5.AD currency register module 2 and AD currency to the effect of FIFO control module 5 is that the AD data ensured in each passage AD currency register module 2 effectively enter fifo module 3 and carry out buffer memory, and its state transition graph as shown in Figure 4.Because the degree of depth of fifo module 3 is limited, for preventing loss of data, logic needs the status register of real time inspection fifo module 3, judges whether fifo module 3 has been write full.If fifo module 3 is write full, logic will stop from AD currency register module 2, read data and put into fifo module 3 data register, wait for microcomputer reads fifo module 3, until fifo module 3 produces room to the follow-up data write in currency register.For accomplishing flexible use, AD data buffer storage steering logic is generated the kernel meeting specification by SOPC Builder, user independently increases and decreases the number of this kernel according to number of active lanes.
The present invention, for the A/D chip of SPI interface, solves 32 road multichannel analog amount Real-time Collections and to hold concurrently buffer control problem.In this design basis, user can each tunnels analogy value of real time inspection, also the analog acquisition data of a period of time can be carried out buffer memory with arbitrary time span, to facilitate later observation and analysis.For realizing the greatest versatility of logic, strengthen flexibility ratio, all logics are made into the kernel meeting specification, can be articulated according to actual needs in AVALON bus by user.
Embodiment two: present embodiment is described further the multichannel analog amount Real-time Collection based on AVALON bus described in embodiment one and caching method, in present embodiment, also comprise based on the multichannel analog amount Real-time Collection of AVALON bus and caching system: microprocessor and timer; Microprocessor in FPGA can by write cycle to timer, as the time interval sampled from AD currency register.
Embodiment three: present embodiment is described further the multichannel analog amount Real-time Collection based on AVALON bus described in embodiment one and caching method, in present embodiment, before analog quantity real-time collecting method institute in steps, first electrification reset, make all read-write operations invalid, export zeros data.
Embodiment four: present embodiment is described further the multichannel analog amount Real-time Collection based on AVALON bus described in embodiment one and caching method, in present embodiment, FPGA carries out data transmission by the main SPI interface of the AD in AVALON bus and AD conversion chip.
Embodiment five: present embodiment is described further the multichannel analog amount Real-time Collection based on AVALON bus described in embodiment one and caching method, in present embodiment, FPGA carries out data transmission by the main SPI interface of the analog switch in AVALON bus and FPGA to analog switch.
Embodiment six: present embodiment is described further the multichannel analog amount Real-time Collection based on AVALON bus described in embodiment one and caching method, and in present embodiment, FIFO is the kernel of Altera.
Embodiment seven: present embodiment is described further the multichannel analog amount Real-time Collection based on AVALON bus described in embodiment two and caching method, in present embodiment, FPGA can pass through microcomputer reads data fifo, is then stored to data cached in outside DDR3 (third generation double data rate Synchronous Dynamic Random Access Memory).
Embodiment eight: present embodiment is described further the multichannel analog amount Real-time Collection based on AVALON bus described in embodiment one and caching method, in present embodiment, the timer kernel that can configure write cycle is time interval controls device.
Claims (8)
1. based on multichannel analog amount Real-time Collection and the caching method of AVALON bus, it is characterized in that, the method realizes based on the multichannel analog amount Real-time Collection of AVALON bus and caching system, this system is embedded in FPGA, it comprises: 32 tunnel analog quantity Real-time Collections and control module (1), AD currency register module (2), fifo module (3), time interval controls module (4), AD currency is to FIFO control module (5), the main SPI module (6) of AD and the main SPI module (7) of analog switch, above-mentioned module is all articulated in AVALON bus, the method comprises: analog quantity real-time collecting method and the real-time caching method of analog quantity,
Analog quantity real-time collecting method, comprises the following steps:
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module (1) write data to the transmitter register of the main SPI module (7) of analog switch, and the main SPI module (7) of described analog switch opens the wherein a-road-through road of analog switch;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module (1) send the main SPI transmitter register address of AD, and write data to the main SPI module (6) of AD, start AD conversion chip, AD conversion is carried out to the simulating signal of input AD conversion chip;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module (1) send the main SPI receiving register address of AD, and send and read enable signal;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module (1) read the AD conversion value that AD conversion chip obtains;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module (1) send the current register address of present day analog switch open wireless tunnel, and the AD conversion value of reading are write in this actual registers, complete the analog acquisition in a-road-through road;
FPGA Zhong 32 tunnel analog quantity Real-time Collection and control module (1) upgrade the write data of transmitter register in the main SPI module (7) of analog switch, repeat the analog acquisition that above-mentioned analog quantity real-time collecting method carries out next paths;
The real-time caching method of analog quantity, comprises the following steps:
AD currency in FPGA sends the status register address of FIFO to FIFO control module (5);
AD currency in FPGA reads data to FIFO control module (5) from AD currency register module (2);
AD currency in FPGA sends the data register address of fifo module (3) to FIFO control module (5), and data is write in the data register of fifo module (3);
AD currency in FPGA reads the status register of fifo module (3) to FIFO control module (5), judges that whether FIFO is full, if then stop writing data to fifo module (3); Otherwise repeat the real-time caching method of above-mentioned analog quantity, continue to write data to fifo module (3);
Data are write External memory equipment by fifo module (3), complete the buffer memory of present day analog amount;
Time interval controls module (4) gathers the time interval of simulating signal for controlling 32 tunnel analog quantity Real-time Collections and control module (1).
2. the multichannel analog amount Real-time Collection based on AVALON bus according to claim 1 and caching method, is characterized in that, also comprises: microprocessor and timer based on the multichannel analog amount Real-time Collection of AVALON bus and caching system; Microprocessor in FPGA can by write cycle to timer, as the time interval sampled from AD currency register.
3. the multichannel analog amount Real-time Collection based on AVALON bus according to claim 1 and caching method, it is characterized in that, before analog quantity real-time collecting method institute is in steps, first electrification reset, make all read-write operations invalid, export zeros data.
4. the multichannel analog amount Real-time Collection based on AVALON bus according to claim 1 and caching method, is characterized in that, FPGA carries out data transmission by the main SPI interface of the AD in AVALON bus and AD conversion chip.
5. the multichannel analog amount Real-time Collection based on AVALON bus according to claim 1 and caching method, is characterized in that, FPGA carries out data transmission by the main SPI interface of the analog switch in AVALON bus and FPGA to analog switch.
6. the multichannel analog amount Real-time Collection based on AVALON bus according to claim 1 and caching method, is characterized in that, FIFO is the kernel of Altera.
7. the multichannel analog amount Real-time Collection based on AVALON bus according to claim 2 and caching method, it is characterized in that, FPGA can pass through microcomputer reads data fifo, then controls kernel by DDR3 and is stored to data cached in outside DDR3.
8. the multichannel analog amount Real-time Collection based on AVALON bus according to claim 1 and caching method, is characterized in that, the timer kernel that can configure write cycle is time interval controls device.
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Application publication date: 20150715 |