CN104777456B - Configurable radar digital signal processing device and its processing method - Google Patents

Abstract

The invention discloses a kind of configurable radar digital signal processing device and its processing method.Which includes eight modules, and the configuration information outside control logic module reception produces four tunnel control signals, controls address generating module all the way and produce butterfly coefficient module, the read/write address signal of plug-in memory module；Control data adjusting module adjusts data and is defeated by data allocation module all the way；Control data distribute module assigns data to multiplication tree module and data post-processing module all the way；Control data post-processing module processing data it is defeated by data point reuse module and plug-in memory module all the way；Butterfly coefficient module reads data to data allocation module, and plug-in memory module reads data and gives data point reuse module, and multiplication tree module completes multiplying and output result gives Data Post module.The present invention has the advantages that to cache and storage area is little, function is more, the low in energy consumption and design cycle is short, can be used for the real-time processing communicated with radar digital signal.

Description

Configurable radar digital signal processor and its processing method

technical field

The invention relates to the technical field of digital signal processing, in particular to a configurable radar digital signal processing technology, which can be used for real-time processing of communication and radar signals.

Background technique

With the continuous development of radar signal processing theory and digital technology, most of today's radar signals are processed by digital methods. After the digital-to-analog converter, the digital down-conversion DDC is used to move the intermediate frequency signal to zero frequency, extract useful information, filter out interference information, extract data, and reduce the data rate; pulse compression PC solves the problem of radar operating distance and The contradiction between resolution, because the method of pulse compression in the frequency domain is greatly reduced than the calculation amount of convolution in the time domain, so the frequency domain is generally used to achieve pulse compression; the moving target detection MTD uses the Doppler effect to improve the radar in the The ability to detect moving targets in the background of clutter improves the anti-jamming capability of the radar. The general radar signal processor is implemented in a pipelined manner, which has the advantage of being able to process data continuously, but this implementation scheme has complex hardware structure, large cache and storage resources, high cost, high power consumption, and does not conform to pulse Doppler. The characteristics of Leradar's intermittent transmission and reception of pulsed signals.

Beihang University's patented technology "A Real-time Processing System and Method for Intermediate Frequency LFM-PD Radar Signals Based on FPGA and DSP" (application number CN201110131410, authorized announcement number CN102288941B) discloses a real-time processing method for pulsed radar signals. The method uses FPGA to complete intermediate frequency sampling, digital down-conversion and pulse compression, and uses DSP to complete moving target detection, coherent accumulation, moving target compensation and constant false alarm processing. The disadvantage of this patented technology is that the entire system adopts the pipeline method, and a large amount of cache resources are required between pipelines at all levels, and the area is large. Moreover, with the increase of the number of coherent accumulations, the processing speed of DSP cannot meet the requirements of real-time processing. .

Contents of the invention

The purpose of the present invention is to address the shortcomings of the above-mentioned existing prior art, and propose a configurable radar digital signal processor and its processing method, so as to reduce processor cache and storage area, reduce cost, and realize real-time processing of radar signals.

The technical idea of the present invention is to realize real-time processing of radar signals by means of time-division multiplexing, realize the separation of functional modules and storage modules by way of external storage, save cache and storage area, and reduce costs. Its implementation plan is as follows:

One, a kind of configurable radar digital signal processor is characterized in that comprising:

The control logic module is used to configure the working mode of the radar signal processor, and generates a control signal corresponding to the working mode, and the control signal is sent to the address generation module, the data adjustment module, the data distribution module, and the data post-processing module;

The address generation module is used to generate read/write address signals according to the control signals, and output the address signals to the butterfly factor module and the external storage module;

The butterfly factor module is used to store the butterfly factor required for FFT/IFFT operations, and read the stored data according to the address control signal and output it to the data allocation module;

An external storage module is used to store the coefficients of the low-pass filter, the coefficients of the matched filter and the calculation results of the data post-processing module, and read the stored data according to the address control signal and output them to the data adjustment module;

The data adjustment module is used to find out the maximum absolute value in the output data of the data post-processing module, and shift or synchronize the output data of the external storage module according to the control signal, and output the processed data to the data distribution module;

The data allocation module is used to select the output data of the butterfly factor module, the output data of the external storage module, the external input data and the constant 0 according to the control signal, and output the selection result to the multiplication tree module and the data post-processing module;

The multiplication tree module is used for multiplying the data of the data distribution module, and outputting the operation result to the data post-processing module after truncation;

The data post-processing module is used to add/subtract the output data of the data distribution module and the output data of the multiplication tree module according to the control signal, and output the operation results to the data adjustment module and the external storage module.

Two, carry out the method for radar digital signal processing with above-mentioned processor, comprise the steps:

(1) Initial parameter configuration:

The user stores the processor mode configuration information into the first configuration register, stores the length configuration information into the second configuration register, stores the butterfly factor required for FFT/IFFT operation into the butterfly factor module, and stores the low-pass filter coefficient, The coefficients of the matched filter are stored in the external storage module;

(2) Generate a control signal:

When the data enable signal is high level, the processor enters the working state, the value of the working flag signal is high level, and the counter starts counting at the same time, and the counter judges whether the counting ends according to the state value of the first configuration register and the second configuration register, if Yes, the value of the working flag signal jumps to a low level, if not, the value of the working flag signal remains high;

When the work flag signal is high level, the control unit of the logic control module generates four control signals, the first control signal is used to control the address generation module to generate address signals, and the second control signal is used to control the data adjustment module to shift the data / synchronization, the third control signal is used to control the data distribution module to select data, and the fourth control signal is used to control the data post-processing module to perform addition/subtraction operations after data selection;

(3) Determine whether the operation is completed:

Judging whether the work flag signal is low level, if yes, then the operation is completed, if not, then the operation is not completed, and step (4) is performed;

(4) Generate address signal:

The address generation signal module generates the read address signal of the butterfly factor module under the control of the first control signal, and simultaneously generates the read address signal and the write address signal of the external storage module;

(5) Data preparation:

According to the read address signal of the external storage module, the data is read and output to the data adjustment module, and the data is shifted/synchronized according to the second control signal, and the result is sent to the data distribution module; according to the read address signal of the butterfly factor module, the data is read Take the butterfly factor and output the data to the data distribution module; receive external input data and output the data to the data distribution module;

(6) Data distribution:

The data distribution module selects data from the output data of step (5) under the control of the third control signal, and outputs to the multiplication tree module and the data post-processing module;

(7) Multiplication operation:

The multiplication tree module multiplies the output data of step (6), and the obtained result is truncated and output to the data post-processing module;

(8) Data post-processing:

Under the control of the fourth control signal, the data post-processing module selects the output data of steps (6) and (7) and then performs addition/subtraction operations, and truncates the calculation results to the external storage module and the data adjustment module ;

(9) Data storage:

Output the calculation result of the data post-processing module to the data adjustment module, find out the maximum absolute value of the output data and the most significant bit of the maximum absolute value; write the calculation result of the data post-processing module in the external storage module, and return to the step ( 3).

Compared with the prior art, the present invention has the following characteristics:

First, because the present invention adopts the separation of functional modules and storage modules, a large amount of cache and storage area can be saved, and costs can be reduced. Storage resources can be plugged in according to user needs, maximizing the utilization of storage resources and having high flexibility.

Second, because the present invention extracts the common points of digital down-conversion, pulse compression, and moving target detection algorithms in radar digital signal processing, a multifunctional circuit structure is designed, so that the present invention can respectively realize digital down-conversion and different points Pulse compression and different numbers of moving target detection can also be used to sequentially complete digital down-conversion, pulse compression of different points and different numbers of moving targets by time-division multiplexing, and digital down-conversion and different points The pulse compression and detection of different numbers of moving targets shorten the design cycle of the processor and improve the efficiency.

Description of drawings

Fig. 1 is the block diagram of processor of the present invention;

Fig. 2 is the block diagram of logic control module in the processor of the present invention;

Fig. 3 is the block diagram of the data adjustment module in the processor of the present invention;

Fig. 4 is the block diagram of the data post-processing module in the processor of the present invention;

Fig. 5 is a flow chart of the processing method of the present invention.

detailed description

The radar signal processor of the present invention will be further described below in conjunction with the accompanying drawings.

Referring to accompanying drawing 1, the configurable radar digital signal processor of the present invention comprises; Tree module 7 and data post-processing module 8 . in:

The control logic module 1 is connected with the address generation module 2, the data adjustment module 5, the data distribution module 6 and the data post-processing module 8, and is used to receive externally input mode configuration information, length configuration information, configuration enabling signals and Data enable signal; when the data enable signal is high level, four control signals are generated according to the mode configuration information and length configuration information, and these four control signals control different modules to complete different functions. Wherein the first control signal is transmitted to the address generation module 2 through the control bus, and the address generation module 2 is controlled to generate the address signal; the second control signal is transmitted to the data adjustment module 5 through the control bus, and the data adjustment module 5 is controlled to shift the data / synchronization; the third control signal is transmitted to the data distribution module 6 through the control bus, and the data distribution module 6 is controlled to select data; the fourth control signal is transmitted to the data post-processing module 8 through the control bus, and the data post-processing module 8 is controlled. Select and add/subtract data.

The address generating module 2 is connected with the butterfly factor module 3 and the plug-in storage module 4, and is used to receive the control signal of the logic control module 1, and generates the read address signal and the plug-in memory module 3 of the butterfly factor module 3 under the control of the control signal. The read address signal and write address signal of the storage module 4; the read address signal of the butterfly factor module 3 is transmitted to the butterfly factor module 3 through the read address bus, and the read address signal of the external storage module 4 is transmitted to the external storage module through the read address bus 4. The write address signal of the external storage module 4 is transmitted to the external storage module 4 through the write address bus.

Described butterfly factor module 3, it is connected with data allocation module 6, is used to receive the read address signal of address generation module 2, reads the butterfly factor in the butterfly factor module 3 according to read address signal, the butterfly factor of this butterfly factor The real part and the imaginary part are respectively transmitted to the data distribution module 6 through the data bus.

Described plug-in storage module 4, it is connected with data adjustment module 5, is used to receive the real part and the imaginary part data of postprocessing module 8 output of data and address generation module 2 read address signal and write address signal, write address signal according to write address signal The real part and imaginary part data output by the data post-processing module 8 are written into the external storage module 4, and the data of the external storage module 4 is read according to the read address signal, and the real part and imaginary part of the data are respectively transmitted to the data adjustment module through the data bus 5.

The data adjustment module 5, which is connected with the data distribution module 6, is used to receive the control signal of the control logic module 1, the real part and imaginary part data output by the external storage module 4, and the real part and imaginary part data output by the data post-processing module 8. part data, find out the maximum absolute value in the real part and the imaginary part data output by the data post-processing module 8 and judge its maximum significant bit, and judge according to the control signal whether the real part and the imaginary part data output by the external storage module 4 are processed Shifting or synchronizing: if the control signal is at a high level, then the real part and imaginary part data output by the external storage module 4 are shifted, and the number of shifted bits is equal to the difference between the data bit width minus the maximum significant bit; If the control signal is low level, the real part and imaginary part data output by the external storage module 4 are synchronized; then the real part and imaginary part data after the shift/synchronization are transmitted to the data distribution module 6 through the data bus respectively;

The data allocation module 6 is connected with the multiplication tree module 7 and the data post-processing module 8, and is used to receive the real part and the imaginary part data of the external input data, the butterfly factor 3 output, the real part and the imaginary part data of the data adjustment module 5 output and The imaginary part data, the constant 0 and the control signal of the logic control module 1 select the received data under the control of the control signal, and transmit the selected data to the data post-processing module 8 through the data bus, and the selected The four data are transmitted to the multiplication tree module 7 through the data bus respectively.

The multiplication tree module 7, which is connected with the data post-processing module 8, is used to receive the four output data of the data distribution module 6, and carry out multiplication operation of the first data and the second data, and the third data and the fourth data Perform multiplication, and then truncate the two calculation results and then transmit them to the data post-processing module 8 through the data bus.

The data post-processing module 8, which is connected with the external storage module 4 and the data adjustment module 5, is used to receive the control signal of the logic control module 1, the output data of the data distribution module 6, the constant 0 and the two of the multiplication tree module 7 Output data, send the received data to the real part channel and the imaginary part channel respectively, under the control of the control signal, add/subtract the data of the real part channel and the imaginary part channel The first two results are truncated and then transmitted to the external storage module 4 and the data adjustment module 5 through the data bus.

Referring to FIG. 2 , the logic control module 1 in the processor of the present invention includes: a first configuration register 11 , a second configuration register 12 and a control unit 13 . in:

The first configuration register 11, which is connected to the control unit 13, is used to receive the configuration enable signal and mode configuration signal input from the outside, and when the configuration enable signal is high, the configuration mode signal is stored in the first configuration register 11 , output the data in the first configuration register 11 to the control unit 13 through the data bus.

The second configuration register 12, which is connected to the control unit 13, is used to receive an externally input configuration enable signal and a length configuration signal, and when the configuration enable signal is high, the length configuration signal is stored in the second configuration register 12 , and output the data in the second configuration register 12 to the control unit 13 through the data bus.

The control unit 13 is connected with the address generation module 2, the data adjustment module 5, the data distribution module 6 and the data post-processing module 8, and is used to receive an externally input data enable signal, the output data of the first configuration register 11 and the second The output data of the configuration register, when the data enable signal is high, four control signals are generated according to the output data of the first configuration register 11 and the output data of the second configuration register, and these four control signals respectively control different modules to complete different functions. Wherein the first control signal is transmitted to the address generation module 2 through the control bus, and the address generation module 2 is controlled to generate the address signal; the second control signal is transmitted to the data adjustment module 5 through the control bus, and the data adjustment module 5 is controlled to shift the data / synchronization; the third control signal is transmitted to the data distribution module 6 through the control bus, and the data distribution module 6 is controlled to select data; the fourth control signal is transmitted to the data post-processing module 8 through the control bus, and the data post-processing module 8 is controlled. Select and add/subtract data.

Referring to FIG. 3 , the data adjustment module 5 in the processor of the present invention includes; a maximum absolute value unit 51 , a most significant bit unit 52 and a data shift/synchronization unit 53 . in:

The maximum absolute value unit 51, which is connected with the most significant bit unit 52, is used to receive the output data of the data post-processing module 8, find out the maximum absolute value of the output data of the data post-processing module 8, and output the maximum absolute value through the data bus to most significant bit location 52.

The most significant bit unit 52, which is connected with the data shift/synchronization unit 53, is used to receive the output data of the maximum absolute value unit 51, find out the most significant bit of the data, and output the most significant bit to the data shifter through the data bus / synchronization unit 53 .

Data shift/synchronization unit 53, which is connected with data distribution module 6, is used to receive the output data of the most significant bit unit 52, the control signal of the control logic module 1 and the output data of the external storage module 4, and judge whether it is right according to the control signal The real part and imaginary part data output by the external storage module 4 are shifted or synchronized: if the control signal is high, then the shift operation is performed, and the real part and imaginary part data output by the external storage module 4 are shifted. The number of digits of the bit is equal to the difference of the data bit width minus the most significant bit; if the control signal is low level, synchronization is performed, and the real part and imaginary part data output by the external storage module 4 are synchronized; then the shift/ The synchronized real part and imaginary part data are respectively transmitted to the data distribution module 6 through the data bus.

Referring to accompanying drawing 4, the data post-processing module 8 in the processor of the present invention includes: a first data selection unit 81, a second data selection unit 82, a truncation unit 83 and four addition/subtraction units. in:

The first data selection unit 81, which is connected with the first addition/subtraction unit 84 and the third addition/subtraction unit 86, is used to receive two output data of the multiplication tree module 7, a constant 0, the output data of the data distribution module 6, The output data of the first addition/subtraction unit 84 and the control signal of the logic control module 1, under the control of the control signal, two data are selected and transmitted to the first addition/subtraction unit 84 through the data bus, and one of them is selected The data is transmitted to the third addition/subtraction unit 86 via the data bus.

The first addition/subtraction unit 84, which is connected with the first data selection unit 81 and the third addition/subtraction unit 86, is used to receive the two output data of the first data selection unit 81 and the control signal of the logic control module 1. Under the control of the control signal, two data are added or subtracted, and the operation result is transmitted to the first data selection unit 81 and the third addition/subtraction unit 86 through the data bus.

The third addition/subtraction unit 86, which is connected with the truncation unit 83, is used to receive the output data of the first data selection unit 81, the output data of the first addition/subtraction unit 84 and the control signal of the logic control module 1, in Under the control of the control signal, two data are added or subtracted, and the result of the operation is transmitted to the truncation unit 83 through the data bus.

The second data selection unit 82, which is connected with the second addition/subtraction unit 85 and the fourth addition/subtraction unit 87, is used to receive two output data of the multiplication tree module 7, constant 0, the output data of the data distribution module 6, The output data of the second addition/subtraction unit 85 and the control signal of the logic control module 1, under the control of the control signal, two data are selected to be transmitted to the second addition/subtraction unit 85 respectively through the data bus, and one of them is selected The data is transmitted to the fourth addition/subtraction unit 87 via the data bus.

The second addition/subtraction unit 85, which is connected with the second data selection unit 82 and the fourth addition/subtraction unit 87, is used to receive the two output data of the second data selection unit 82 and the control signal of the logic control module 1. Under the control of the control signal, two data are added or subtracted, and the operation result is transmitted to the second data selection unit 82 and the fourth addition/subtraction unit 87 through the data bus.

The fourth addition/subtraction unit 87, which is connected with the truncation unit 83, is used to receive the output data of the second data selection unit 82, the output data of the second addition/subtraction unit 85 and the control signal of the logic control module 1, in Under the control of the control signal, two data are added or subtracted, and the result of the operation is transmitted to the truncation unit 83 through the data bus.

Truncation unit 83, which is connected with the external storage module 4 and the data adjustment module 5, is used to receive the output data of the third addition/subtraction unit 86 and the output data of the fourth addition/subtraction unit 87, after the two data are truncated They are respectively transmitted to the external storage module 4 and the data adjustment module 5 through the data bus.

With reference to Fig. 5, utilize above-mentioned processor to carry out the method for radar digital signal processing, its steps are as follows:

Step 1, initial parameter configuration

The user stores the processor mode configuration information into the first configuration register, stores the length configuration information into the second configuration register, stores the butterfly factor required for FFT/IFFT operation into the butterfly factor module, and stores the low-pass filter coefficient, The coefficients of the matched filter are stored in the external storage module;

Among them, the bit width of the mode configuration information is 2, including four working modes. When the mode configuration information is 00, enter the digital down-conversion mode; when the mode configuration information is 01, enter the frequency domain pulse compression mode; when the mode configuration information is At 10 o'clock, enter the moving target detection mode; when the mode configuration information is 11, enter the time division multiplexing mode, and the time division multiplexing performs digital down conversion, frequency domain pulse compression and moving target detection calculation;

The bit width of the length configuration information is 20, the high ten bits are information on the length of the pulse compression sequence, and the length ranges from 2 to 1024, and the low ten bits are information on the number of coherent accumulations, and the number ranges from 2 to 1024.

Step 2, generate control signal

2a) When the data enable signal is high level, the processor enters the working state, the value of the working flag signal is high level, and the counter starts counting at the same time, and the counter judges whether the counting ends according to the state values of the first configuration register and the second configuration register , if yes, the value of the working flag signal jumps to a low level, if not, the value of the working flag signal remains high;

2b) When the work flag signal is at a high level, the control logic control module generates control signals, and these four control signals are controlled as follows:

The first control signal is used to control the address generating module to generate an address signal, and different working modes require different address signals, specifically as follows;

When the processor is in the digital down-conversion mode, the control signal is used to control the address generation module to generate the read address signal and write address signal of the data plug-in module; when the processor is in the frequency domain pulse compression mode, the control signal is used to control the address The generation module generates the read address signal of the butterfly factor module and the read address signal and write address signal of the plug-in module; when the processor is in the moving target detection mode, the control signal is used to control the address generation module to generate the read address of the butterfly factor module signal and the read address signal and write address signal of the plug-in module; when the processor is in the time division multiplexing mode, the control signal is used to control the address generation module to generate the read address signal of the butterfly factor module and the read address signal and write address of the plug-in module address signal;

The second control signal is used to control the data adjustment module to shift/synchronize the data, and different working modes require different operations on the data, specifically as follows;

When the processor is in digital down-conversion mode, this signal is not used; when the processor is in frequency domain pulse compression mode, this control signal is used to synchronize the matched filter coefficients output by the external storage module, and output When the processor is in the moving target detection mode, the control signal is used to shift the pulse sequence output by the external storage module; when the processor is in the time division multiplexing mode, the control signal It is used to synchronize the matched filter coefficient output by the external storage module, and shift the pulse sequence output by the external storage module;

The third control signal is used to control the data distribution module to select data, and different working modes require different selection of data, which is specifically shown as follows;

When the processor is in the digital down-conversion mode, the control signal is used to select the external input data and the output data of the data adjustment module to send to the data distribution module; when the processor is in the frequency domain pulse compression mode, the processor needs to sequentially perform fast Domain FFT, multiplication of matching coefficients and fast time domain IFFT operations. When performing fast time domain FFT/IFFT operations, this control signal is used to select external input data, output data of the data adjustment module and output data of the butterfly factor module to send to The data distribution module, when performing matching coefficient multiplication, the control signal is used to select the output data of the data adjustment module and send it to the data distribution module; when the processor is in the moving target detection mode, the processor needs to perform slow time-domain FFT operations, the The control signal is used to select the external input data, the output data of the data adjustment module and the output data of the butterfly factor module to send to the data distribution module; when the processor is in the time division multiplexing mode, the processor needs to perform digital down-conversion, fast time domain FFT, multiplication of matching coefficients, fast time domain IFFT and slow time domain FFT operations, when performing digital down-conversion, the control signal is used to select external input data and the output data of the data adjustment module is sent to the data distribution module for fast time domain In FFT/IFFT and slow time domain FFT, the control signal is used to select the external input data, the output data of the data adjustment module and the output data of the butterfly factor module to send to the data distribution module, and when the matching coefficient is multiplied, the control signal The output data used to select the data adjustment module is sent to the data distribution module;

The fourth control signal is used to control the data post-processing module to perform addition/subtraction operations after the data is selected. Different operation modes require different operations, and the specific performance is as follows;

When the processor is in the digital down conversion mode, the control signal is used to control the data post-processing module to complete the accumulation operation in the digital down conversion; when the processor is in the frequency domain pulse compression, the processor needs to perform fast time domain FFT, matching coefficient Multiplication and fast time-domain IFFT operation. When performing fast time-domain FFT/IFFT, the control signal is used to control the data post-processing module to complete the addition of the butterfly operation. When performing matching coefficient multiplication, the control signal is used to control the data The post-processing module completes the addition operation of matching multiplication; when the processor is in the moving target detection, the processor needs to perform slow time-domain FFT operation, and the control signal is used to control the data post-processing module to complete the addition operation of the butterfly operation; when processing When the device is in time-division multiplexing mode, the processor needs to perform digital down conversion, fast time domain FFT, matching coefficient multiplication, fast time domain IFFT and slow time domain FFT operations. When performing digital down conversion, the control signal is used to control data The post-processing module completes the accumulation/subtraction operation in the digital down-conversion, and when performing fast time domain FFT/IFFT and slow time domain FFT, the control signal is used to control the data post-processing module to complete the addition/subtraction operation in the butterfly operation. When the matching coefficients are multiplied, the control signal is used to control the data post-processing module to complete the addition/subtraction operation in the matching multiplication.

Step 3, judge whether the operation corresponding to the working mode is completed:

The operations corresponding to the working mode are divided into four types: the first is digital down-conversion mode, including low-pass filtering and decimation operations; the second is frequency domain pulse compression mode, including fast time domain FFT, matching coefficient multiplication and fast time domain IFFT operation; the third is moving target detection mode, including slow time domain FFT operation; the fourth is time division multiplexing mode, including digital down conversion, fast time domain FFT, matching coefficient multiplication, fast time domain IFFT and slow Time domain FFT operation;

Judging whether to complete the operation corresponding to the working mode is realized by judging whether the working flag signal is low level. If the working flag signal is low level, the operation corresponding to the working mode is completed. If the working flag signal is high level, If the operation corresponding to the working mode is not completed, go to step 4.

Step 4, generate address signal

The address generation signal module generates the read address signal of the butterfly factor module under the control of the first control signal, and simultaneously generates the read address signal and the write address signal of the external storage module.

Step 5, Data Preparation

5a) receiving external input data, and outputting the data to the data distribution module;

5b) read data according to the read address signal of the external storage module, output the real part and imaginary part of the data to the data adjustment module, and shift/synchronize the real part and imaginary part data according to the second control signal and then shift the real part and imaginary part data Part and imaginary part results are sent to the data allocation module;

5c) Read the butterfly factor according to the read address signal of the butterfly factor module, and output the real part and the imaginary part of the butterfly factor to the data distribution module.

Step 6, Data Distribution

Under the control of the third control signal, the data distribution module selects data from the five output data and the constant 0 in step 5, selects four data to output to the multiplication tree module, and selects one data to output to the data post-processing module.

Step 7, Multiplication

The multiplication tree module multiplies the four output data output in step 6, that is, first multiplies the first data and the second data; then multiplies the third data and the fourth data; and then the two calculation results After the bits are truncated, they are respectively transmitted to the data post-processing module through the data bus.

Step 8, data post-processing

The data post-processing module receives one output data of step 6, two output data data and constant 0 of step 7, and sends the received data to the real part channel and the imaginary part channel respectively; then under the control of the fourth control signal , respectively add/subtract the data of the real part channel and the imaginary part channel, and finally truncate the real part and imaginary part results and transmit them to the external storage module and the data adjustment module respectively through the data bus.

Step 9, Data Storage

Output the real part and imaginary part data of the data post-processing module to the data adjustment module, find out the maximum absolute value of the output data and its most significant bit; write the real part and imaginary part data of the data post-processing module into the external storage module , return to step 3.

The above description is only a specific example of the present invention. Obviously, for those skilled in the art, after understanding the contents and principles of the present invention, it is possible to modify the forms and details without departing from the principles and structures of the present invention. Various amendments and changes above, but these amendments and changes based on the idea of the present invention are still within the protection scope of the claims of the present invention.

Claims (4)

1. a kind of configurable radar digital signal processing device, it is characterised in that include：

Control logic module (1), for configuring the mode of operation of radar signal processor, produces the control corresponding with mode of operation Signal processed, after the control signal is transported to address generating module (2), data point reuse module (5), data allocation module (6), data Processing module (8)；

Address generating module (2), for producing read/write address signal according to control signal, and by address signal output to butterfly Factor module (3) and plug-in memory module (4)；

Butterfly coefficient module (3), for storing the butterfly coefficient needed for FFT/IFFT computings, and reads according to address control signal The data output of storage is to data allocation module (6)；

Plug-in memory module (4), for storing the coefficient of low-pass filtering, the coefficient of matched filtering and data post-processing module (8) Operation result, and the data output of storage is read to data point reuse module (5) according to address control signal；

Data point reuse module (5), for finding out the maximum value in Data Post module (8) output data, and according to control Signal processed is shifted to the output data of plug-in memory module (4) or synchronous, by the data output after process to data point With module (6)；

Data allocation module (6), for according to output data, plug-in memory module of the control signal to butterfly coefficient module (3) (4) output data, outer input data and constant 0 are selected, after selection result output to multiplication tree module (7) and data Processing module (8)；

Multiplication tree module (7), for carrying out multiplying to the data of data allocation module (6), will be defeated after operation result cut position Go out to Data Post module (8)；

Data Post module (8), for according to output data, multiplication tree module of the control signal to data allocation module (6) (7) output data carries out plus/minus computing, by operation result output to data point reuse module (5) and plug-in memory module (4)；

The Data Post module (8) includes：One the first data selection unit (81), second data selection unit (82), a cut position unit (83) and four plus/minus method units；

First data selection unit (81), for the control signal transmitted according to control module (1), from data allocation module (6) Output data, the output data of multiplication tree module (7), in the output data and constant 0 of the first plus/minus method unit (84), choosing Two of which data output is selected out to the first plus/minus method unit (84), one of data output is selected to the Acanthopanan trifoliatus (L.) Merr./subtraction Unit (86)；

First plus/minus method unit (84), two data for exporting to the first data selection unit (81) carry out plus/minus fortune Calculate, and operation result is exported to the first data selection unit (81) and the Acanthopanan trifoliatus (L.) Merr./subtrator (86)；

The Acanthopanan trifoliatus (L.) Merr./subtrator (86), for the output data to the first data selection unit (81) and the first plus/minus method unit (84) output data carries out plus/minus computing, result is exported and gives cut position unit (83)；

Second data selection unit (82), for the control signal transmitted according to control module (1), from data allocation module (6) Output data, the output data of multiplication tree module (7), in the output data and constant 0 of the second plus/minus method unit (85), choosing Go out two of which data output to the second plus/minus method unit (85), one of data output is selected to the 4th plus/minus method unit (87)；

Second plus/minus method unit (85), two data for exporting to the second data selection unit (82) carry out plus/minus fortune Calculate, operation result is exported to the 4th plus/minus method unit (87)；

4th plus/minus method unit (87), for the output data to the second data selection unit (82) and the second plus/minus method unit (85) output data carries out plus/minus computing, operation result is exported and gives cut position unit (83)；

Cut position unit (83), for the output result cut position to the Acanthopanan trifoliatus (L.) Merr./subtrator (86) and the 4th plus/minus method unit (87) After export to plug-in memory module (4) and data adjusting module (5).

2. configurable radar digital signal processing device according to claim 1, it is characterised in that the logic control mould Block (1) includes：First configuration register (11), the second configuration register (12) and a control unit (13)；First configuration For storing the pattern configurations information of processor, second configuration register (12) matches somebody with somebody confidence for memory length to depositor (11) Breath；The input of control unit (13) is connected with the first configuration register (11) and the second configuration register (12), is matched somebody with somebody first Control signal is produced under the control of the data enable signal for putting depositor (11), the second configuration register (12) and outside input, Export to address generating module (2), data point reuse module (5), data allocation module (6), and data post-processing module (8).

3. configurable radar digital signal processing device according to claim 1, it is characterised in that the data point reuse mould Block (5) includes：One maximum value unit (51), a highest significant position unit (52) and a data displacement/synchronous list First (53)；Maximum value unit (51) is for finding out the maximum value of Data Post module (8) output data, and exports Give highest significant position unit (52)；Highest significant position unit (52) is for finding out the highest significant position of maximum value, and exports Give data displacement/lock unit (53)；Data displacement/lock unit (53) is for external according to control signal and highest significant position The output data for hanging memory module (4) carries out shifting/and it is synchronous, and export and give data allocation module (6).

4. a kind of method that processor of utilization claim 1 carries out radar digital signal processing, comprises the steps：

(1) initial parameter configuration：

Processor mode configuration information is stored in the first configuration register by user, and length configuration information is stored in the second configuration deposit Butterfly coefficient needed for FFT/IFFT computings is stored in butterfly coefficient module by device, by the coefficient of low-pass filtering, matched filtering is Number is stored in plug-in memory module；

(2) produce control signal：

When it is high level that data enable signal, processor enters working condition, and the value of working mark signal is high level, while Enumerator is started counting up, and whether enumerator judges to count according to the first configuration register and the second configuration register state value ties Beam, if it is, the value saltus step of working mark signal is low level, if it is not, then the value of working mark signal keeps high electricity It is flat；

When working mark signal is high level, the control unit of Logic control module produces four control signals：

First control signal is used to control address generating module generation address signal, i.e., when processor compresses mould in frequency-domain impulse During formula seasonal pulse punching press compressed mode, the reading for reading address signal and plug-in module that address generating module generates butterfly coefficient module is controlled Address signal and writing address signal；When processor be in moving-target detection pattern when, control address generating module generate butterfly because The reading address signal and writing address signal of reading address signal and plug-in module of submodule；When processor is in time division multiplexing When, control the reading address signal and write address of reading address signal and plug-in module that address generating module generates butterfly coefficient module Signal

Second control signal is used for control data adjusting module to be carried out shifting/synchronization to data, i.e., when processor is in frequency domain arteries and veins During punching press compressed mode, the matched filtering coefficient of plug-in memory module output is synchronized, to the output of plug-in memory module Pulse train is shifted；When processor is in moving-target detection pattern, the pulse train to the output of plug-in memory module Shifted；When processor is in time division multiplexing, the matched filtering coefficient of plug-in memory module output is synchronized, The pulse train of plug-in memory module output is shifted；

3rd control signal is selected to data for control data distribute module, i.e., when processor is in Digital Down Convert mould During formula, outer input data and the output data of data adjusting module is selected to give data allocation module；When processor is in frequency During the pulse compression pattern of domain, processor needs to carry out fast time domain FFT, matching factor multiplication and fast time domain IFFT fortune successively Calculate, when fast time domain FFT/IFFT computing is carried out, the control signal selects outer input data, the output number of data point reuse module Data allocation module is given according to the output data with butterfly coefficient module, when matching factor multiplication is carried out, the control signal is selected The output data for selecting data point reuse module gives data allocation module；When processor is in moving-target detection pattern, processor Needs carry out slow time domain FFT computing, and the control signal selects outer input data, the output data of data point reuse module and butterfly The output data of shape factor module gives data allocation module；When processor be in time division multiplexing when, processor need into Row Digital Down Convert, fast time domain FFT, matching factor multiplication, fast time domain IFFT and slow time domain FFT computing, are entering line number During word down coversion, the control signal selects outer input data and the output data of data adjusting module to give data distribution mould Block, when fast time domain FFT/IFFT and slow time domain FFT is carried out, the control signal selects outer input data, data point reuse mould The output data of the output data and butterfly coefficient module of block gives data allocation module, when matching factor multiplication is carried out, should Control signal selects the output data of data point reuse module to give data allocation module；

4th control signal is used for control data post-processing module to carrying out plus/minus computing after data selection, i.e., at the processor When Digital Down Convert pattern, control data post-processing module completes the accumulating operation in Digital Down Convert；When processor is in When frequency-domain impulse compresses, processor needs to carry out fast time domain FFT, matching factor multiplication and fast time domain IFFT computing, is entering During fast time domain FFT/IFFT of row, control data post-processing module completes the additive operation of butterfly computation, is carrying out matching factor phase Take the opportunity, control data post-processing module completes to match the additive operation being multiplied；When processor is detected in moving-target, processor Needs carry out slow time domain FFT computing, and the control signal control data post-processing module completes the additive operation of butterfly computation；When When processor is in time division multiplexing, processor need to carry out Digital Down Convert, fast time domain FFT, matching factor be multiplied, it is fast Time domain IFFT and slow time domain FFT computing, when Digital Down Convert is carried out, the control signal control data post-processing module is complete Into the tired plus/minus computing in Digital Down Convert, when fast time domain FFT/IFFT and slow time domain FFT is carried out, the control signal control Data Post module processed completes the plus/minus method computing in butterfly computation, when matching factor multiplication is carried out, the control signal control Data Post module processed completes to match the plus/minus method computing in being multiplied；

(3) judge whether to complete computing：

Judge whether working mark signal is low level, if it is, computing is completed, if it is not, then computing is not completed, perform Step (4)；

(4) produce address signal：

Address produces signaling module under the control of the first control signal, produces the reading address signal of butterfly coefficient module, while Produce the reading address signal and its writing address signal of plug-in memory module；

(5) data prepare：

Data output is read to data point reuse module according to the reading address signal of plug-in memory module, and according to the second control signal Data are carried out shifting/synchronization after the result is sent to into data allocation module；Read according to the reading address signal of butterfly coefficient module Butterfly coefficient is taken, by the data output to data allocation module；Input data outside receiving, by data output to data point With module；

(6) data distribution：

Data allocation module selects data from the output data of step (5) under the control of the 3rd control signal, exports to taking advantage of Method tree module, Data Post module；

(7) multiplying：

Multiplication tree module carries out multiplying to step (6) output data, after the result of acquisition exports data after carrying out cut position Processing module；

(8) Data Post：

Data Post module is selected to the output data of step (6), step (7) under the control of the 4th control signal After carry out plus/minus computing, plug-in memory module, data point reuse module will be conveyed to after result of calculation cut position；

(9) data storage：

By the result of calculation output of Data Post module to data point reuse module, find out the maximum value of output data and be somebody's turn to do The highest significant position of maximum value；The result of calculation of Data Post module is write in plug-in memory module, return to step (3)。