CN104777456B - Configurable radar digital signal processing device and its processing method - Google Patents
Configurable radar digital signal processing device and its processing method Download PDFInfo
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- CN104777456B CN104777456B CN201510172252.7A CN201510172252A CN104777456B CN 104777456 B CN104777456 B CN 104777456B CN 201510172252 A CN201510172252 A CN 201510172252A CN 104777456 B CN104777456 B CN 104777456B
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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Abstract
The invention discloses a kind of configurable radar digital signal processing device and its processing method.Which includes eight modules, and the configuration information outside control logic module reception produces four tunnel control signals, controls address generating module all the way and produce butterfly coefficient module, the read/write address signal of plug-in memory module；Control data adjusting module adjusts data and is defeated by data allocation module all the way；Control data distribute module assigns data to multiplication tree module and data post-processing module all the way；Control data post-processing module processing data it is defeated by data point reuse module and plug-in memory module all the way；Butterfly coefficient module reads data to data allocation module, and plug-in memory module reads data and gives data point reuse module, and multiplication tree module completes multiplying and output result gives Data Post module.The present invention has the advantages that to cache and storage area is little, function is more, the low in energy consumption and design cycle is short, can be used for the real-time processing communicated with radar digital signal.
Description
Technical field
The present invention relates to digital signal processing technique field, more particularly to a kind of configurable radar digital signal processing skill
Art, can be used for the real-time processing communicated with radar signal.
Background technology
The continuous development of theoretical and digital technology with Radar Signal Processing, radar signal now adopt numeral side mostly
Method process.Digital Down Convert DDC for intermediate-freuqncy signal is moved zero-frequency, and is extracted useful after digital to analog converter
Information, filters interference information, and data are extracted, and reduces data rate；Pulse compression PC solve radar horizon with
Contradiction between resolving power, as frequency domain realizes that the method for pulse compression greatly reduces than the operand of convolution, so one
As pulse compression is realized by the way of frequency domain；Moving-target detection MTD improves radar in clutter background using Doppler effect
The ability of lower detection moving-target, improves the capacity of resisting disturbance of radar.Side of the general radar signal processor using streamline
Formula realizes, its advantage be can continuously processing data, but this implementation hardware configuration is complicated, and caching and storing is provided
Source is big, high cost, and power consumption is big, and does not meet the characteristic of pulse Doppler radar intermittent transmission and return pulse signal.
Patented technology " a kind of intermediate frequency LFM-PD radar signals based on FPGA and DSP that BJ University of Aeronautics ＆ Astronautics possesses
Real time processing system and processing method " (application number CN201110131410, Authorization Notice No. CN102288941B) discloses one
Plant pulsed radar signal real-time processing method.The method completes if sampling, Digital Down Convert, pulse compression using FPGA, uses
DSP completes moving-target detection, correlative accumulation, moving target compensation and CFAR and processes.The deficiency that the patented technology is present is, whole
Individual system needs substantial amounts of cache resources by the way of streamline between flowing water at different levels, area is big, and with correlative accumulation
The increase of number, the processing speed of DSP do not reach the requirement of real-time processing.
The content of the invention
Present invention aims to above-mentioned existing the deficiencies in the prior art, propose a kind of configurable radar digital signal
Processor and its processing method, to reduce processor cache and storage area, reduces cost realizes the real-time place of radar signal
Reason.
The present invention technical thought be：By time-multiplexed mode, the real-time processing of radar signal is realized, by plug-in
The mode of storage, realizes that functional module is separated with memory module, saves caching and stores area, reduces cost.Its implementation
It is as follows：
First, a kind of configurable radar digital signal processing device, it is characterised in that include：
Control logic module, for configuring the mode of operation of radar signal processor, produces corresponding with mode of operation
Control signal, the control signal are transported to address generating module, data point reuse module, data allocation module, Data Post mould
Block；
Address generating module, for producing read/write address signal according to control signal, and by address signal output to butterfly
Factor module and plug-in memory module；
Butterfly coefficient module, for storing the butterfly coefficient needed for FFT/IFFT computings, and reads according to address control signal
The data output of storage is taken to data allocation module；
Plug-in memory module, for storing the coefficient of low-pass filtering, the coefficient of matched filtering and data post-processing module
Operation result, and the data output of storage is read to data point reuse module according to address control signal；
Data point reuse module, for finding out the maximum value in Data Post module output data, and according to control
Signal is shifted to the output data of plug-in memory module or synchronous, by the data output after process to data distribution mould
Block；
Data allocation module, for defeated to the output data of butterfly coefficient module, plug-in memory module according to control signal
Go out data, outer input data and constant 0 to be selected, by selection result output to multiplication tree module and Data Post mould
Block；
Multiplication tree module, carries out multiplying for the data to data allocation module, will export after operation result cut position
To Data Post module；
Data Post module, for according to control signal to the output data of data allocation module, multiplication tree module
Output data carries out plus/minus computing, by operation result output to data point reuse module and plug-in memory module.
2nd, the method for carrying out radar digital signal processing with above-mentioned processor, comprises the steps：
(1) initial parameter configuration：
Processor mode configuration information is stored in the first configuration register by user, and length configuration information is stored in the second configuration
Butterfly coefficient needed for FFT/IFFT computings is stored in butterfly coefficient module by depositor, by the coefficient of low-pass filtering, matched filtering
Coefficient be stored in plug-in memory module；
(2) produce control signal：
When it is high level that data enable signal, processor enters working condition, and the value of working mark signal is high level,
Unison counter is started counting up, and whether enumerator judges counting according to the first configuration register and the second configuration register state value
Terminate, if it is, the value saltus step of working mark signal is low level, if it is not, then the value of working mark signal keeps high
Level；
When working mark signal is high level, control unit four control signals of generation of Logic control module, first
Control signal is used to control address generating module generation address signal, and the second control signal is used for control data adjusting module logarithm
According to carrying out shifting/synchronization, the 3rd control signal is selected to data for control data distribute module, and the 4th control signal is used
Plus/minus computing is carried out after control data post-processing module is to data selection；
(3) judge whether to complete computing：
Judge whether working mark signal is low level, if it is, computing is completed, if it is not, then computing is not completed,
Execution step (4)；
(4) produce address signal：
Address produces signaling module under the control of the first control signal, produces the reading address signal of butterfly coefficient module,
The reading address signal and its writing address signal of plug-in memory module are produced simultaneously；
(5) data prepare：
Data output is read to data point reuse module according to the reading address signal of plug-in memory module, and according to the second control
Data signal carries out shifting/synchronization after the result is sent to into data allocation module；Believed according to the reading address of butterfly coefficient module
Number read butterfly coefficient, by the data output to data allocation module；Input data outside receiving, by the data output to number
According to distribute module；
(6) data distribution：
Data allocation module selects data from the output data of step (5) under the control of the 3rd control signal, output
To multiplication tree module, Data Post module；
(7) multiplying：
Multiplication tree module carries out multiplying to step (6) output data, and number is arrived in output after the result of acquisition carries out cut position
According to post-processing module；
(8) Data Post：
Data Post module is carried out to the output data of step (6), step (7) under the control of the 4th control signal
Plus/minus computing is carried out after selection, plug-in memory module, data point reuse module will be conveyed to after result of calculation cut position；
(9) data storage：
By the result of calculation output of Data Post module to data point reuse module, the maximum value of output data is found out
And the highest significant position of the maximum value；The result of calculation of Data Post module is write in plug-in memory module, is returned
Step (3).
The present invention is had the characteristics that compared with prior art：
First, separate with memory module due to present invention employs functional module, substantial amounts of caching and storage can be saved
Area, reduces cost, and storage resource can be plug-in according to user's request, reaches utilization ratio of storage resources maximization, motility
It is high.
Second, as the present invention is extracted Digital Down Convert in radar digital signal processing, pulse compression, moving-target detection
The common ground of algorithm, designs a multi-functional circuit structure so that the present invention can realize Digital Down Convert, difference respectively
The pulse compression of points and the detection of different number of moving-target, it would however also be possible to employ time-multiplexed mode order completes to become under numeral
Frequently, the pulse compression of different points and the detection of different number of moving-target, can also carry out becoming under numeral by the way of flowing water
Frequently, the pulse compression of different points and the detection of different number of moving-target, the design cycle for shortening processor are short, improve effect
Rate.
Description of the drawings
Fig. 1 is the block diagram of processor of the present invention；
Fig. 2 is the block diagram of Logic control module in processor of the present invention；
Fig. 3 is the block diagram of data point reuse module in processor of the present invention；
Fig. 4 is the block diagram of Data Post module in processor of the present invention；
Fig. 5 is the process flow figure of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawings the radar signal processor of the present invention is further described.
Referring to the drawings 1, the configurable radar digital signal processing device of the present invention includes；Control logic module 1, address is produced
Raw module 2, butterfly coefficient module 3, plug-in memory module 4, data point reuse module 5, data allocation module 6,7 and of multiplication tree module
Data Post module 8.Wherein：
The control logic module 1, itself and address generating module 2, data point reuse module 5, data allocation module 6 and data
Post-processing module 8 connects, and enables signal sum for receiving the pattern configurations information of outside input, length configuration information, configuration
According to enable signal；When it is high level that data enable signal, four controls are produced according to pattern configurations information and length configuration information
Signal processed, this four control signals control different modules respectively and complete different functions.Wherein the first control signal is by control
Bus transfer processed controls the address generating module 2 and generates address signal to address generating module 2；Second control signal is by control
To data point reuse module 5, control the data point reuse module 5 carries out shifting/synchronization bus transfer processed to data；3rd control signal
Data allocation module 6 is transferred to by controlling bus, the data allocation module 6 is controlled and data is selected；4th control letter
Number be transferred to Data Post module 8 by controlling bus, control the Data Post module 8 data are selected and carry out plus/
Subtract computing.
The address generating module 2, which is connected with butterfly coefficient module 3 and plug-in memory module 4, for receiving logic control
The control signal of molding block 1, produces the reading address signal and plug-in storage mould of butterfly coefficient module 3 under control of the control signal
The reading address signal of block 4 and writing address signal；The reading address signal of butterfly coefficient module 3 is transferred to butterfly by reading address bus
Shape factor module 3, the reading address signal of plug-in memory module 4 are transferred to plug-in memory module 4 by reading address bus, plug-in to deposit
The writing address signal of storage module 4 gives plug-in memory module 4 by write address bus transfer.
The butterfly coefficient module 3, which is connected with data allocation module 6, for receiving the reading address of address generating module 2
Signal, according to the butterfly coefficient read in address signal reading butterfly coefficient module 3, the real part and imaginary part of the butterfly coefficient lead to respectively
Data bus transmission is crossed to data allocation module 6.
The plug-in memory module 4, which is connected with data point reuse module 5, for the output of receiving data post-processing module 8
The reading address signal of real part and imaginary data and address generating module 2 and writing address signal, according to writing address signal by after data
The real part and imaginary data of the output of processing module 8 writes plug-in memory module 4, reads plug-in memory module according to address signal is read
4 data, the real part and imaginary part of the data is respectively by data bus transmission to data point reuse module 5.
The data point reuse module 5, which is connected with data allocation module 6, and the control for receiving control logic module 1 is believed
Number, plug-in memory module 4 output real part and imaginary data and data post-processing module 8 output real part and imaginary data, look for
Go out Data Post module 8 output real part and imaginary data in maximum value and judge its most significant digit, and according to
Control signal judges it is that real part and imaginary data to the output of plug-in memory module 4 are shifted or synchronous：If control letter
Number it is high level, then the real part for exporting plug-in memory module 4 and imaginary data carry out shifting function, and the digit of displacement is equal to number
The difference of most significant digit is deducted according to bit wide；If control signal be low level, the real part that plug-in memory module 4 is exported and
Imaginary data is synchronized；Again by the real part and imaginary data after displacement/synchronization respectively by data bus transmission to data point
With module 6；
The data allocation module 6, which is connected with multiplication tree module 7 and data post-processing module 8, outside defeated for receiving
Enter data, the real part of the output of butterfly coefficient 3 and imaginary data, the real part of the output of data point reuse module 5 and imaginary data, constant 0
With the control signal of Logic control module 1, under control of the control signal received data is selected, and will be selected
A data by data bus transmission to Data Post module 8, select four data are total by data respectively
Line is transferred to multiplication tree module 7.
The multiplication tree module 7, which is connected with Data Post module 8, and four for receiving data distribute module 6 are defeated
Go out data, and the first data and the second data are carried out into multiplying, the 3rd data and the 4th data are carried out into multiplying, then
Data bus transmission will be passed through after the two result of calculation cut positions respectively to Data Post module 8.
The Data Post module 8, which is connected with plug-in memory module 4 and data adjusting module 5, for receiving logic
Two output datas of the control signal of control module 1, the output data of data allocation module 6, constant 0 and multiplication tree module 7,
Received data is sent to real part passage and imaginary part passage respectively, under control of the control signal, to real part passage and imaginary part
The data of passage carry out plus/minus computing after selecting, and real part and imaginary part two-way result are carried out total by data respectively after cut position
Line is transferred to plug-in memory module 4 and data adjusting module 5.
Referring to the drawings 2, in processor of the present invention, Logic control module 1 includes；First the 11, second configuration of configuration register is posted
Storage 12 and control unit 13.Wherein：
First configuration register 11, which is connected with control unit 13, for receive outside input configuration enable signal and
Mode configuration signals, when it is high level that configuration enables signal, configuration mode signal are stored in the first configuration register 11, will
Data in first configuration register 11 are by data/address bus output to control unit 13.
Second configuration register 12, which is connected with control unit 13, for receive outside input configuration enable signal and
Length configures signal, when it is high level that configuration enables signal, length configuration signal is stored in the second configuration register 12, will
Data in second configuration register 12 are by data/address bus output to control unit 13.
Control unit 13, itself and address generating module 2, data point reuse module 5, data allocation module 6 and Data Post
Module 8 connects, and the data for receiving outside input enable signal, the output data of the first configuration register 11 and the second configuration
The output data of depositor, when it is high level that data enable signal, according to the output data of the first configuration register 11 and the
The output data of two configuration registers produces four control signals, and this four control signals control different modules respectively and complete not
Same function.Wherein the first control signal is transferred to address generating module 2 by controlling bus, controls the address generating module 2
Generate address signal；Second control signal is transferred to data point reuse module 5 by controlling bus, controls the data point reuse module 5
Data are carried out shifting/synchronization；3rd control signal is transferred to data allocation module 6 by controlling bus, controls the data point
Data are selected with module 6；4th control signal is transferred to Data Post module 8 by controlling bus, controls the number
Data are selected according to post-processing module 8 and carry out plus/minus computing.
Referring to the drawings 3, in processor of the present invention, data point reuse module 5 includes；One maximum value unit 51, one is most
High effectively bit location 52 and a data displacement/lock unit 53.Wherein：
Maximum value unit 51, which is connected with highest significant position unit 52, for the defeated of receiving data post-processing module 8
Go out data, find out the maximum value of 8 output data of Data Post module, the maximum value is exported by data/address bus
To highest significant position unit 52.
Highest significant position unit 52, which is connected with data displacement/lock unit 53, for receiving maximum value unit 51
Output data, find out the highest significant position of the data, by highest significant position by data/address bus output to data displacement/synchronous
Unit 53.
Data shifting/lock unit 53, which is connected with data allocation module 6, for receiving the defeated of highest significant position unit 52
Go out the output data of data, the control signal of control logic module 1 and plug-in memory module 4, and according to control signal judgement be
The real part and imaginary data of the output of plug-in memory module 4 are carried out shifting or synchronous：Enter if control signal is high level
Row displacement, the then real part for exporting plug-in memory module 4 and imaginary data carry out shifting function, and the digit of displacement is equal to data bit
Width deducts the difference of most significant digit；Synchronize if control signal is low level, then plug-in memory module 4 is exported
Real part and imaginary data are synchronized；Again the real part and imaginary data after displacement/synchronization is given by data bus transmission respectively
Data allocation module 6.
Referring to the drawings 4, in processor of the present invention, Data Post module 8 includes；First data selection unit 81, second is counted
According to 82, cut position unit 83 of select unit and four plus/minus method units.Wherein：
First data selection unit 81, which is connected with the first plus/minus method unit 84 and the Acanthopanan trifoliatus (L.) Merr./subtrator 86, is used for
Two output datas of reception multiplication tree module 7, constant 0, the output data of data allocation module 6, the first plus/minus method unit 84
Output data and Logic control module 1 control signal, under the control of the control signal, select two data and lead to respectively
Data bus transmission is crossed to the first plus/minus method unit 84, select one of data by data bus transmission to Acanthopanan trifoliatus (L.) Merr./
Subtrator 86.
First plus/minus method unit 84, which is connected with the first data selection unit 81 and the Acanthopanan trifoliatus (L.) Merr./subtrator 86, is used for
Two output datas and the control signal of Logic control module 1 of the first data selection unit 81 are received, in the control signal
Under control, two data are carried out into addition or subtraction, operation result is selected to the first data by data bus transmission
Unit 81 and the Acanthopanan trifoliatus (L.) Merr./subtrator 86.
The Acanthopanan trifoliatus (L.) Merr./subtrator 86, which is connected with cut position unit 83, for receiving by the first data selection unit 81
The control signal of output data, the output data of the first plus/minus method unit 84 and Logic control module 1, in the control of control signal
Under system, two data are carried out into addition or subtraction, operation result is by data bus transmission to cut position unit 83.
Second data selection unit 82, which is connected with the second plus/minus method unit 85 and the 4th plus/minus method unit 87, is used for
Two output datas of reception multiplication tree module 7, constant 0, the output data of data allocation module 6, the second plus/minus method unit 85
Output data and Logic control module 1 control signal, under the control of the control signal, select two data and lead to respectively
Data bus transmission is crossed to the second plus/minus method unit 85, select one of data by data bus transmission to the 4th plus/
Subtrator 87.
Second plus/minus method unit 85, which is connected with the second data selection unit 82 and the 4th plus/minus method unit 87, is used for
Two output datas and the control signal of Logic control module 1 of the second data selection unit 82 are received, in the control signal
Under control, two data are carried out into addition or subtraction, operation result is selected to the second data by data bus transmission
Unit 82 and the 4th plus/minus method unit 87.
4th plus/minus method unit 87, which is connected with cut position unit 83, for receiving by the second data selection unit 82
The control signal of output data, the output data of the second plus/minus method unit 85 and Logic control module 1, in the control signal
Under control, two data are carried out into addition or subtraction, operation result is by data bus transmission to cut position unit 83.
Cut position unit 83, which is connected with plug-in memory module 4 and data adjusting module 5, for receiving the Acanthopanan trifoliatus (L.) Merr./subtraction list
The output data and the output data of the 4th plus/minus method unit 87 of unit 86, will pass through data/address bus respectively after two data cut positions
It is transferred to plug-in memory module 4 and data adjusting module 5.
With reference to Fig. 5, the method for carrying out radar digital signal processing using above-mentioned processor, its step are as follows：
Step 1, initial parameter configuration
Processor mode configuration information is stored in the first configuration register by user, and length configuration information is stored in the second configuration
Butterfly coefficient needed for FFT/IFFT computings is stored in butterfly coefficient module by depositor, by the coefficient of low-pass filtering, matched filtering
Coefficient be stored in plug-in memory module；
Wherein, pattern configurations information bit a width of 2, including four kinds of mode of operations, when pattern configurations information is 00, into number
Word down coversion pattern；When pattern configurations information is 01, into frequency-domain impulse compact model；When pattern configurations information is 10,
Into moving-target detection pattern；It is when pattern configurations information is 11, into time division multiplexing, time-multiplexed to carry out under numeral
Frequency conversion, frequency-domain impulse compression and moving-target detection calculations；
Length configuration information bit wide is the information that 20, Gao Shiwei is pulse compression sequence length, and length range is arrived for 2
1024, low ten information for correlative accumulation number, number range are 2 to 1024.
Step 2, produces control signal
2a) when it is high level that data enable signal, processor enters working condition, and the value of working mark signal is high electricity
Flat, unison counter is started counting up, and enumerator judges to count according to the first configuration register and the second configuration register state value
Whether terminate, if it is, the value saltus step of working mark signal is low level, if it is not, then the value of working mark signal is protected
Hold high level；
2b) when working mark signal is high level, control logic control module produces control signal, this four control letters
Number controlled as follows respectively：
First control signal, generates address signal for controlling address generating module, and different mode of operations need
Different address signals, concrete manifestation are as follows；
When processor is in Digital Down Convert pattern, the control signal is used to control outside address generating module generation data
Hang the reading address signal and writing address signal of module；When processor is in frequency-domain impulse compact model, the control signal is used for
Control address generating module generates the reading address signal and write address letter for reading address signal and plug-in module of butterfly coefficient module
Number；When processor is in moving-target detection pattern, the control signal is used to control address generating module generation butterfly coefficient mould
The reading address signal and writing address signal of reading address signal and plug-in module of block；When processor is in time division multiplexing,
The control signal is used to control the reading address for reading address signal and plug-in module that address generating module generates butterfly coefficient module
Signal and writing address signal；
Data are carried out shifting/synchronization, different Working moulds by second control signal for control data adjusting module
Formula needs to carry out different operations to data, and concrete manifestation is as follows；
When processor is in Digital Down Convert pattern, the signal is not used；When processor is compressed in frequency-domain impulse
During pattern, the control signal for synchronizing to the matched filtering coefficient that plug-in memory module is exported, to plug-in storage mould
The pulse train of block output is shifted；When processor is in moving-target detection pattern, the control signal is for plug-in
The pulse train of memory module output is shifted；When processor is in time division multiplexing pattern, the control signal is used
Synchronize in the matched filtering coefficient exported to plug-in memory module, the pulse train of plug-in memory module output is moved
Position；
3rd control signal is selected to data for control data distribute module, and different mode of operations need
Different selections are carried out to data, concrete manifestation is as follows；
When processor is in Digital Down Convert pattern, the control signal is used to select outer input data and data point reuse
The output data of module gives data allocation module；When processor is in frequency-domain impulse compact model, processor needs successively
Carry out fast time domain FFT, matching factor to be multiplied and fast time domain IFFT computing, when carrying out fast time domain FFT/IFFT computing, the control
Signal processed is used to select the output data of outer input data, the output data of data point reuse module and butterfly coefficient module to give
Data allocation module, when carrying out matching factor multiplication, the control signal is used to select the output data of data point reuse module to give
Data allocation module；When processor is in moving-target detection pattern, processor needs to carry out slow time domain FFT computing, the control
Signal processed is used to select the output data of outer input data, the output data of data point reuse module and butterfly coefficient module to give
Data allocation module；When processor is in time division multiplexing, processor need to carry out Digital Down Convert, fast time domain FFT,
Matching factor multiplication, fast time domain IFFT and slow time domain FFT computing, when carrying out Digital Down Convert, the control signal is used to select
The output data for selecting outer input data and data adjusting module gives data allocation module, carries out fast time domain FFT/IFFT and slow
During time domain FFT, the control signal is used to select outer input data, the output data of data point reuse module and butterfly coefficient mould
The output data of block gives data allocation module, and when carrying out matching factor multiplication, the control signal is used to select data point reuse mould
The output data of block gives data allocation module；
4th control signal is used for control data post-processing module to carrying out plus/minus computing after data selection, different
Mode of operation need different computings, concrete manifestation is as follows；
When processor is in Digital Down Convert pattern, the control signal completes numeral for control data post-processing module
Accumulating operation in down coversion；When processor is compressed in frequency-domain impulse, processor needs to carry out fast time domain FFT, matching
Multiplication and fast time domain IFFT computing, when carrying out fast time domain FFT/IFFT, the control signal is used for control data post processing
Module completes the additive operation of butterfly computation, and when carrying out matching factor multiplication, the control signal is used for control data post processing mould
Block completes to match the additive operation being multiplied；When processor is detected in moving-target, processor needs to carry out slow time domain FFT fortune
Calculate, the control signal is used for the additive operation that control data post-processing module completes butterfly computation；When processor was answered in the time-division
When using pattern, processor need to carry out Digital Down Convert, fast time domain FFT, matching factor be multiplied, fast time domain IFFT and it is slow when
Between domain FFT computings, when carrying out Digital Down Convert, the control signal is completed in Digital Down Convert for control data post-processing module
Tired plus/minus computing, when carrying out fast time domain FFT/IFFT and slow time domain FFT, the control signal be used for control data post processing
Module completes the plus/minus method computing in butterfly computation, and when carrying out matching factor multiplication, the control signal is located after being used for control data
Reason module completes to match the plus/minus method computing in being multiplied.
Step 3, judges whether to complete the computing corresponding to mode of operation：
The corresponding computing of mode of operation is divided into four kinds：The first is Digital Down Convert pattern, including low-pass filtering and extraction
Computing；It is for second frequency-domain impulse compact model, including fast time domain FFT, matching factor is multiplied and fast time domain IFFT computing；
The third is moving-target detection pattern, including slow time domain FFT computing；4th kind is become under time division multiplexing, including numeral
Frequently, fast time domain FFT, matching factor multiplication, fast time domain IFFT and slow time domain FFT computing；
Judge whether that the computing completed corresponding to mode of operation is by judging whether working mark signal is low level reality
It is existing, if working mark signal is low level, the computing corresponding to mode of operation is completed, if working mark signal is high
Level, the then computing corresponding to unfinished work pattern, execution step 4.
Step 4, produces address signal
Address produces signaling module under the control of the first control signal, produces the reading address signal of butterfly coefficient module,
The reading address signal and its writing address signal of plug-in memory module are produced simultaneously.
Step 5, data prepare
Input data outside 5a) receiving, by the data output to data allocation module；
Data are read according to the reading address signal of plug-in memory module 5b), by the real part of the data and imaginary part output to number
According to adjusting module, and real part and imaginary data are carried out shifting according to the second control signal/synchronization after by real part and imaginary results
It is sent to data allocation module；
Butterfly coefficient is read according to the reading address signal of butterfly coefficient module 5c), by the real part and imaginary part of the butterfly coefficient
Export data allocation module.
Step 6, data distribution
Data allocation module is carried out under the control of the 3rd control signal from five output datas and constant 0 of step 5
Data are selected, and are selected four data outputs to multiplication tree module, are selected a data output to Data Post module.
Step 7, multiplying
Four output datas that multiplication tree module is exported to step 6 carry out multiplying, i.e., first by the first data and second
Data carry out multiplying；The 3rd data and the 4th data are carried out into multiplying again；Then by the two result of calculation cut positions
Data Post module is given by data bus transmission respectively afterwards.
Step 8, Data Post
One output data of Data Post module receiving step 6, two output data data of step 7 and constant 0,
And received data is sent to real part passage and imaginary part passage respectively；It is again under the control of the 4th control signal, logical to real part
The data of road and imaginary part passage carry out plus/minus computing respectively, lead to after real part and imaginary part two-way result are carried out cut position finally respectively
Data bus transmission is crossed to plug-in memory module and data adjusting module.
Step 9, data storage
By the real part of Data Post module and imaginary data output to data point reuse module, the maximum of output data is found out
Absolute value and its highest significant position；The real part and imaginary data of Data Post module are write in plug-in memory module, is returned
Step 3.
Above description is only example of the present invention, it is clear that for the professional person of this area, is being understood
After present invention and principle, it is likely to, in the case of without departing substantially from the principle of the invention, structure, to carry out in form and details
Various amendments and change, but these amendments based on inventive concept and change claim protection model still in the present invention
Within enclosing.
Claims (4)
1. a kind of configurable radar digital signal processing device, it is characterised in that include：
Control logic module (1), for configuring the mode of operation of radar signal processor, produces the control corresponding with mode of operation
Signal processed, after the control signal is transported to address generating module (2), data point reuse module (5), data allocation module (6), data
Processing module (8)；
Address generating module (2), for producing read/write address signal according to control signal, and by address signal output to butterfly
Factor module (3) and plug-in memory module (4)；
Butterfly coefficient module (3), for storing the butterfly coefficient needed for FFT/IFFT computings, and reads according to address control signal
The data output of storage is to data allocation module (6)；
Plug-in memory module (4), for storing the coefficient of low-pass filtering, the coefficient of matched filtering and data post-processing module (8)
Operation result, and the data output of storage is read to data point reuse module (5) according to address control signal；
Data point reuse module (5), for finding out the maximum value in Data Post module (8) output data, and according to control
Signal processed is shifted to the output data of plug-in memory module (4) or synchronous, by the data output after process to data point
With module (6)；
Data allocation module (6), for according to output data, plug-in memory module of the control signal to butterfly coefficient module (3)
(4) output data, outer input data and constant 0 are selected, after selection result output to multiplication tree module (7) and data
Processing module (8)；
Multiplication tree module (7), for carrying out multiplying to the data of data allocation module (6), will be defeated after operation result cut position
Go out to Data Post module (8)；
Data Post module (8), for according to output data, multiplication tree module of the control signal to data allocation module (6)
(7) output data carries out plus/minus computing, by operation result output to data point reuse module (5) and plug-in memory module (4)；
The Data Post module (8) includes：One the first data selection unit (81), second data selection unit
(82), a cut position unit (83) and four plus/minus method units；
First data selection unit (81), for the control signal transmitted according to control module (1), from data allocation module (6)
Output data, the output data of multiplication tree module (7), in the output data and constant 0 of the first plus/minus method unit (84), choosing
Two of which data output is selected out to the first plus/minus method unit (84), one of data output is selected to the Acanthopanan trifoliatus (L.) Merr./subtraction
Unit (86)；
First plus/minus method unit (84), two data for exporting to the first data selection unit (81) carry out plus/minus fortune
Calculate, and operation result is exported to the first data selection unit (81) and the Acanthopanan trifoliatus (L.) Merr./subtrator (86)；
The Acanthopanan trifoliatus (L.) Merr./subtrator (86), for the output data to the first data selection unit (81) and the first plus/minus method unit
(84) output data carries out plus/minus computing, result is exported and gives cut position unit (83)；
Second data selection unit (82), for the control signal transmitted according to control module (1), from data allocation module (6)
Output data, the output data of multiplication tree module (7), in the output data and constant 0 of the second plus/minus method unit (85), choosing
Go out two of which data output to the second plus/minus method unit (85), one of data output is selected to the 4th plus/minus method unit
(87)；
Second plus/minus method unit (85), two data for exporting to the second data selection unit (82) carry out plus/minus fortune
Calculate, operation result is exported to the 4th plus/minus method unit (87)；
4th plus/minus method unit (87), for the output data to the second data selection unit (82) and the second plus/minus method unit
(85) output data carries out plus/minus computing, operation result is exported and gives cut position unit (83)；
Cut position unit (83), for the output result cut position to the Acanthopanan trifoliatus (L.) Merr./subtrator (86) and the 4th plus/minus method unit (87)
After export to plug-in memory module (4) and data adjusting module (5).
2. configurable radar digital signal processing device according to claim 1, it is characterised in that the logic control mould
Block (1) includes：First configuration register (11), the second configuration register (12) and a control unit (13)；First configuration
For storing the pattern configurations information of processor, second configuration register (12) matches somebody with somebody confidence for memory length to depositor (11)
Breath；The input of control unit (13) is connected with the first configuration register (11) and the second configuration register (12), is matched somebody with somebody first
Control signal is produced under the control of the data enable signal for putting depositor (11), the second configuration register (12) and outside input,
Export to address generating module (2), data point reuse module (5), data allocation module (6), and data post-processing module (8).
3. configurable radar digital signal processing device according to claim 1, it is characterised in that the data point reuse mould
Block (5) includes：One maximum value unit (51), a highest significant position unit (52) and a data displacement/synchronous list
First (53)；Maximum value unit (51) is for finding out the maximum value of Data Post module (8) output data, and exports
Give highest significant position unit (52)；Highest significant position unit (52) is for finding out the highest significant position of maximum value, and exports
Give data displacement/lock unit (53)；Data displacement/lock unit (53) is for external according to control signal and highest significant position
The output data for hanging memory module (4) carries out shifting/and it is synchronous, and export and give data allocation module (6).
4. a kind of method that processor of utilization claim 1 carries out radar digital signal processing, comprises the steps：
(1) initial parameter configuration：
Processor mode configuration information is stored in the first configuration register by user, and length configuration information is stored in the second configuration deposit
Butterfly coefficient needed for FFT/IFFT computings is stored in butterfly coefficient module by device, by the coefficient of low-pass filtering, matched filtering is
Number is stored in plug-in memory module；
(2) produce control signal：
When it is high level that data enable signal, processor enters working condition, and the value of working mark signal is high level, while
Enumerator is started counting up, and whether enumerator judges to count according to the first configuration register and the second configuration register state value ties
Beam, if it is, the value saltus step of working mark signal is low level, if it is not, then the value of working mark signal keeps high electricity
It is flat；
When working mark signal is high level, the control unit of Logic control module produces four control signals：
First control signal is used to control address generating module generation address signal, i.e., when processor compresses mould in frequency-domain impulse
During formula seasonal pulse punching press compressed mode, the reading for reading address signal and plug-in module that address generating module generates butterfly coefficient module is controlled
Address signal and writing address signal；When processor be in moving-target detection pattern when, control address generating module generate butterfly because
The reading address signal and writing address signal of reading address signal and plug-in module of submodule；When processor is in time division multiplexing
When, control the reading address signal and write address of reading address signal and plug-in module that address generating module generates butterfly coefficient module
Signal
Second control signal is used for control data adjusting module to be carried out shifting/synchronization to data, i.e., when processor is in frequency domain arteries and veins
During punching press compressed mode, the matched filtering coefficient of plug-in memory module output is synchronized, to the output of plug-in memory module
Pulse train is shifted；When processor is in moving-target detection pattern, the pulse train to the output of plug-in memory module
Shifted；When processor is in time division multiplexing, the matched filtering coefficient of plug-in memory module output is synchronized,
The pulse train of plug-in memory module output is shifted；
3rd control signal is selected to data for control data distribute module, i.e., when processor is in Digital Down Convert mould
During formula, outer input data and the output data of data adjusting module is selected to give data allocation module；When processor is in frequency
During the pulse compression pattern of domain, processor needs to carry out fast time domain FFT, matching factor multiplication and fast time domain IFFT fortune successively
Calculate, when fast time domain FFT/IFFT computing is carried out, the control signal selects outer input data, the output number of data point reuse module
Data allocation module is given according to the output data with butterfly coefficient module, when matching factor multiplication is carried out, the control signal is selected
The output data for selecting data point reuse module gives data allocation module；When processor is in moving-target detection pattern, processor
Needs carry out slow time domain FFT computing, and the control signal selects outer input data, the output data of data point reuse module and butterfly
The output data of shape factor module gives data allocation module；When processor be in time division multiplexing when, processor need into
Row Digital Down Convert, fast time domain FFT, matching factor multiplication, fast time domain IFFT and slow time domain FFT computing, are entering line number
During word down coversion, the control signal selects outer input data and the output data of data adjusting module to give data distribution mould
Block, when fast time domain FFT/IFFT and slow time domain FFT is carried out, the control signal selects outer input data, data point reuse mould
The output data of the output data and butterfly coefficient module of block gives data allocation module, when matching factor multiplication is carried out, should
Control signal selects the output data of data point reuse module to give data allocation module；
4th control signal is used for control data post-processing module to carrying out plus/minus computing after data selection, i.e., at the processor
When Digital Down Convert pattern, control data post-processing module completes the accumulating operation in Digital Down Convert；When processor is in
When frequency-domain impulse compresses, processor needs to carry out fast time domain FFT, matching factor multiplication and fast time domain IFFT computing, is entering
During fast time domain FFT/IFFT of row, control data post-processing module completes the additive operation of butterfly computation, is carrying out matching factor phase
Take the opportunity, control data post-processing module completes to match the additive operation being multiplied；When processor is detected in moving-target, processor
Needs carry out slow time domain FFT computing, and the control signal control data post-processing module completes the additive operation of butterfly computation；When
When processor is in time division multiplexing, processor need to carry out Digital Down Convert, fast time domain FFT, matching factor be multiplied, it is fast
Time domain IFFT and slow time domain FFT computing, when Digital Down Convert is carried out, the control signal control data post-processing module is complete
Into the tired plus/minus computing in Digital Down Convert, when fast time domain FFT/IFFT and slow time domain FFT is carried out, the control signal control
Data Post module processed completes the plus/minus method computing in butterfly computation, when matching factor multiplication is carried out, the control signal control
Data Post module processed completes to match the plus/minus method computing in being multiplied；
(3) judge whether to complete computing：
Judge whether working mark signal is low level, if it is, computing is completed, if it is not, then computing is not completed, perform
Step (4)；
(4) produce address signal：
Address produces signaling module under the control of the first control signal, produces the reading address signal of butterfly coefficient module, while
Produce the reading address signal and its writing address signal of plug-in memory module；
(5) data prepare：
Data output is read to data point reuse module according to the reading address signal of plug-in memory module, and according to the second control signal
Data are carried out shifting/synchronization after the result is sent to into data allocation module；Read according to the reading address signal of butterfly coefficient module
Butterfly coefficient is taken, by the data output to data allocation module；Input data outside receiving, by data output to data point
With module；
(6) data distribution：
Data allocation module selects data from the output data of step (5) under the control of the 3rd control signal, exports to taking advantage of
Method tree module, Data Post module；
(7) multiplying：
Multiplication tree module carries out multiplying to step (6) output data, after the result of acquisition exports data after carrying out cut position
Processing module；
(8) Data Post：
Data Post module is selected to the output data of step (6), step (7) under the control of the 4th control signal
After carry out plus/minus computing, plug-in memory module, data point reuse module will be conveyed to after result of calculation cut position；
(9) data storage：
By the result of calculation output of Data Post module to data point reuse module, find out the maximum value of output data and be somebody's turn to do
The highest significant position of maximum value；The result of calculation of Data Post module is write in plug-in memory module, return to step
(3)。
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