CN106484658B - The device and method of 65536 pulses compression is realized based on FPGA - Google Patents
The device and method of 65536 pulses compression is realized based on FPGA Download PDFInfo
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Abstract
The invention belongs to Radar Signal Processing Technology fields, disclose a kind of device and method that 65536 pulses compression is realized based on FPGA, it realizes process are as follows: 16 tunnels first receive data parallel, and to read Lothrus apterus parallel as principle, store data into 16 block RAMs；Then 16 numbers are read every time in pipelined fashion, carry out 4 grades of -16 butterfly computations of base and stored on-site, complete FFT processing；Carry out the filtering processing of 16 tunnel PARALLEL MATCHINGs and stored on-site；Followed by 4 grades of butterfly computations realize IFFT processing；Last 16 road parallel output；The wherein trigonometric table of twiddle factor and matched filtering coefficient piece-wise linearization, is generated in real time by way of difference of tabling look-up.The use of RAM resource in FPGA is greatly saved in the present invention, and significantly improves processing speed, increases the throughput of data.
Description
Technical field
The invention belongs to Radar Signal Processing Technology fields, more particularly to a kind of FPGA that is based on to realize 65536 pulse pressures
The device and method of contracting, can in high-resolution detection radar, carry out distance to or orientation real-time pulse compression processing.
Background technique
In radar system, wide pulse signal can be compressed into narrow pulse signal by process of pulse-compression, so both can be with
Emit broad pulse to improve the detectability of mean power and radar, and be able to maintain the distance resolution of burst pulse, effectively solves
The certainly contradiction between radar horizon and distance resolution improves the distance point of radar under the premise of not reducing operating distance
Resolution.When equally carrying out process of pulse-compression, the resolution ratio of the more radars of operation points is higher.As time goes on, to thunder
The requirement reached is higher and higher, the real-time pulse compression processing technology for thus needing to count greatly.
It is general using the method for carrying out matched filtering in frequency domain, process flow such as Fig. 1 when realizing pulse compression with FPGA
Shown, data first carry out FFT processing, then multiplied by the matched filtering coefficient of frequency domain, then carry out IFFT processing.
The FPGA of pulse compression technique realizes that currently existing scheme is: scheme one: with FFT module, matched filtering module and
IFFT module-cascade realizes, the wherein IP kernel of FFT module and IFFT module direct Li Hua FPGA manufacturer；Scheme two: FFT module is used
Realize FFT/IFFT processing, FFT processing result directly carries out matched filtering, and the result of matched filtering first carries out caching and is then delivered to
FFT module carries out IFFT processing.
The prior art has the disadvantage that (1) processing speed is slow, when realizing FFT/IFFT processing with the IP kernel of existing FFT
Using low SPLIT RADIX ALGORITHM FOR, in the FFT processing for carrying out big points data, the big degree of parallelism of hour operation quantity is low causes processing speed slow；
Since the interface concurrent degree of the IP kernel of FFT is low (highest supports 4 tunnels parallel), cause matched filtering processing speed slow；(2) interface speed
Rate is low, since IP kernel interface concurrent degree is low, causes the data input and output degree of parallelism of entire module low, interface rate seriously affects
Whole data throughput；(3) resource occupation is more, two individual module waste of resource of FFT and IFFT in scheme one, side
FFT module is multiplexed in case two, but data need to cache, the RAM resource of occupancy is still very much.
Summary of the invention
The shortcomings that for the above-mentioned prior art, the purpose of the present invention is to provide one kind to realize 65536 arteries and veins based on FPGA
The device and method of punching press contracting, with solve that data processing speed is slow in traditional design scheme, interface rate is low and and FFT,
The problem of with data transmission delay between filtering and IFFT.
In order to achieve the above objectives, the embodiment of the present invention, which adopts the following technical scheme that, is achieved.
Technical solution one:
A kind of device for realizing 65536 pulses compression based on FPGA, the input terminal of described device and external progress pulse
The 16 tunnel input data channels connection of compression, the output end of described device are connect with external pulse compression result output channel, institute
Stating device includes: input sequencing module, inputs selecting module, RAM memory module, RAM Read-write Catrol module, data truncation mould
Block, preceding sequencing module, 16 road parallel processing modules, rear sequencing module, Coefficient generation module export sequencing module, overflow ruling
Module, control module；
Wherein, the input terminal of the input sequencing module and the external 16 tunnel input data channels for carrying out pulse compression connect
Connect, input sequencing module output end with input selecting module first input end connect, input selecting module output end and
The input terminal of RAM memory module connects, and the first output end of RAM Read-write Catrol module is connect with the control terminal of RAM memory module,
The second output terminal of RAM Read-write Catrol module is connect with the control terminal of preceding sequencing module, the third output of RAM Read-write Catrol module
End is connect with the control terminal of rear sequencing module, and the output end of RAM memory module is connect with the first input end of data truncation module,
First output end of data truncation module is connect with the input terminal of preceding sequencing module, and the output end of preceding sequencing module and 16 tunnels are parallel
The first input end of processing module connects, and the second input terminal of the output end of Coefficient generation module and 16 road parallel processing modules connects
It connecing, the output end of 16 road parallel processing modules is connect with the input terminal of the input terminal of rear sequencing module, spilling arbitration module respectively,
The output end of sequencing module is connect with the second input terminal of input selecting module afterwards, and the output end and data for overflowing arbitration module are cut
The second output terminal of the second input terminal connection of disconnected module, data truncation module is connect with the input terminal of output sequencing module, institute
State output sequencing module output end connect with external pulse compression result output channel, the input terminal of the control module with outside
Portion carry out pulse compression control signal connection, the first output end of control module respectively with input sequencing module control terminal and
Input selecting module control terminal connection, the second output terminal of control module respectively with the control terminal of RAM Read-write Catrol module, 16
The control terminal of road parallel processing module is connected with the control terminal of Coefficient generation module, and the third output end of control module and output are adjusted
The control terminal of sequence module connects, and the 4th output end of control module is connect with external pulse compression result output signal.
Technical solution two:
A method of 65536 pulse compressions being realized based on FPGA, described method includes following steps:
Step 1,16 input datas are obtained in each clock cycle, and 16 input datas is deposited according to Lothrus apterus
The mode of storage is stored respectively in 16 sub- memory modules；To obtain 65536 point datas by 4096 clock cycle, and deposit
It is stored in RAM memory module；
Step 2,16 pending datas are obtained from RAM memory module；
Step 3, data truncation module carries out 16 pending datas according to the shift amount for overflowing arbitration module output
Displacement；The shift amount initial value for overflowing arbitration module output is zero；
Step 4, the sequence of 16 pending datas after displacement is adjusted to base -16 butterfly computation rule by preceding sequencing module
Sequence；
Step 5,16 pending datas after sequencing are sent to 16 road parallel processing modules by the preceding sequencing module, and
Coefficient generation module generates the corresponding twiddle factor of 16 pending datas, and is sent to 16 road parallel processing modules；
Step 6,16 road parallel processing module is according to 16 pending datas received and corresponding twiddle factor,
- 16 butterfly computation of base is carried out, -16 butterfly computation result of base of this group of data is obtained；
Step 7, the spilling arbitration module carries out spilling judgement to -16 butterfly computation result of base, obtains displacement position
Number；
Step 8, the storage by -16 butterfly computation result of base according to 16 pending datas in RAM memory module
Position carries out stored on-site；
Step 9, step 2 to step 8 is repeated 4096 times in pipelined fashion, obtains first order butterfly computation knot
Fruit；
Step 10, step 2 to step 9 is repeated 4 times, obtains the Fourier transformation result of 65536 point datas；At this time
The data stored in the RAM memory module are 65536 point datas after Fast Fourier Transform (FFT)；
Step 11, the data after obtaining 16 Fast Fourier Transform (FFT)s in RAM memory module；
Step 12, data truncation module according to overflow arbitration module output shift amount, to 16 pending datas into
Row displacement；
Step 13, the sequence of the data after 16 Fast Fourier Transform (FFT)s after displacement is adjusted to base-by preceding sequencing module
The sequence of 16 butterfly computations rule；
Step 14, the data after 16 Fast Fourier Transform (FFT)s after sequencing are sent to 16 tunnels simultaneously by the preceding sequencing module
Row processing module, and Coefficient generation module generates the corresponding matched filtering coefficient of data after 16 Fast Fourier Transform (FFT)s, and
It is sent to 16 road parallel processing modules；
Step 15,16 road parallel processing module is according to data after 16 Fast Fourier Transform (FFT)s received and right
The matched filtering coefficient answered carries out complex multiplication operation, obtains the matched filter operation result of this group of data；
Step 16, the spilling arbitration module carries out spilling judgement to the matched filter operation result, obtains displacement position
Number；
Step 17, the matched filter operation result is stored according to the data after 16 Fast Fourier Transform (FFT)s in RAM
Storage location in module carries out stored on-site；
Step 18, step 11 to step 17 is repeated 4096 times in pipelined fashion, obtains matched filter operation
As a result；The data stored in the RAM memory module at this time are 65536 point datas after matched filter operation；
Step 19, the data after obtaining 16 matched filter operations in RAM memory module；
Step 20, data truncation module is according to the shift amount for overflowing arbitration module output, to 16 matched filter operations
Data afterwards are shifted；
Step 21, the sequence of the data after 16 matched filter operations after displacement is adjusted to base -16 by preceding sequencing module
The sequence of butterfly computation rule；
Step 22, the preceding sequencing module is sent to after the data after 16 matched filter operations after sequencing are taken conjugation
16 road parallel processing modules, and Coefficient generation module generates the corresponding twiddle factor of data after 16 matched filter operations, and
It is sent to 16 road parallel processing modules；
Step 23,16 road parallel processing module is according to the data and correspondence after 16 matched filter operations received
Twiddle factor, carry out -16 butterfly computation of base, obtain -16 butterfly computation result of base of this group of data；
Step 24, the spilling arbitration module carries out spilling judgement to -16 butterfly computation result of base, obtains displacement position
Number；
Step 25, -16 butterfly computation result of base is taken and is existed after being conjugated according to the data after 16 matched filter operations
Storage location in RAM memory module carries out stored on-site；
Step 26, step 19 to step 25 is repeated 4096 times in pipelined fashion, obtains first order butterfly fortune
Calculate result；
Step 27, step 19 to step 26 is repeated 4 times, the data after obtaining 65536 matched filter operations
Inverse Fourier transform is as a result, i.e. pulse compression result；The data stored in the RAM memory module at this time are that pulse is compressed
65536 point datas；
Step 28, data truncation module is read according to the shift amount for overflowing arbitration module output from RAM memory module
The 65536 compressed data of pulse taken are shifted；
Step 29, output sequencing module is by the pulse compression result carry out sequence adjustment after displacement, and exports.
Technical solution of the present invention compared with prior art, has the advantages that
(1) processing speed is fast.Based on 16 tunnel parallel pipeline processing units, FFT/IFFT processing and matched filtering are handled
It combines.Compared at most 4 tunnel concurrent operations are used in existing implementation method, the method for the present invention is reducing the same of calculation amount
The degree of parallelism of Shi Tigao data processing, is greatly improved processing speed.The process of pulse-compression of 65536 point datas is carried out, is passed
System design method needs 131260 clocks that could complete operation, and 28839 clock of module of the method for the present invention design can be completed,
Speed is its 4.55 times.
(2) interface rate is higher.Using the parallel data I/O mode in 16 tunnels, data input and output bottle is eliminated
Neck, compared to could support up 4 road parallel outputs in traditional design method, the method for the present invention once can be with 16 numbers of input and output
According to interface rate of the invention is its 4~16 times.
(3) data throughput is high on the whole.Comprehensively consider interface rate and processing speed, compared to traditional design method,
The throughput that the method for the present invention is realized is its 11.95 times, only needs to can be completed less than 164us at 65536 points under 200M clock
The pulse of data is compressed.
(4) RAM resource is saved.Traditional design method needs the block RAM of 396 36K, and module of the present invention only needs 95 altogether
The block RAM of a 36K.Compared to traditional design method, the method for the present invention has only been used less than its 1/4 RAM resource.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 be it is provided in an embodiment of the present invention in the prior art with FPGA realize pulse compression when, matched in frequency domain
The method flow schematic diagram of filtering；
Fig. 2 is that a kind of structure of device that 65536 pulses compression is realized based on FPGA provided in an embodiment of the present invention is shown
It is intended to；
Fig. 3 is the structural schematic diagram of 16 road provided in an embodiment of the present invention parallel processing module；
Fig. 4 is that Coefficient generation module provided in an embodiment of the present invention generates twiddle factor and the process of matched filtering coefficient is shown
It is intended to.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It is provided in an embodiment of the present invention it is a kind of based on FPGA realize 65536 pulses compression device, described device it is defeated
Enter end to connect with the external 16 tunnel input data channels for carrying out pulse compression, output end and the external pulse compression of described device are tied
The connection of fruit output channel；Its structural schematic diagram is as shown in Figure 2:
Described device includes: input sequencing module, inputs selecting module, RAM memory module, RAM Read-write Catrol module, number
According to truncation module, preceding sequencing module, 16 road parallel processing modules, rear sequencing module, Coefficient generation module, output sequencing module,
Overflow arbitration module, control module；
Wherein, the input terminal of the input sequencing module and the external 16 tunnel input data channels for carrying out pulse compression connect
Connect, input sequencing module output end with input selecting module first input end connect, input selecting module output end and
The input terminal of RAM memory module connects, and the first output end of RAM Read-write Catrol module is connect with the control terminal of RAM memory module,
The second output terminal of RAM Read-write Catrol module is connect with the control terminal of preceding sequencing module, the third output of RAM Read-write Catrol module
End is connect with the control terminal of rear sequencing module, and the output end of RAM memory module is connect with the first input end of data truncation module,
First output end of data truncation module is connect with the input terminal of preceding sequencing module, and the output end of preceding sequencing module and 16 tunnels are parallel
The first input end of processing module connects, and the second input terminal of the output end of Coefficient generation module and 16 road parallel processing modules connects
It connecing, the output end of 16 road parallel processing modules is connect with the input terminal of the input terminal of rear sequencing module, spilling arbitration module respectively,
The output end of sequencing module is connect with the second input terminal of input selecting module afterwards, and the output end and data for overflowing arbitration module are cut
The second output terminal of the second input terminal connection of disconnected module, data truncation module is connect with the input terminal of output sequencing module, institute
State output sequencing module output end connect with external pulse compression result output channel, the input terminal of the control module with outside
Portion carry out pulse compression control signal connection, the first output end of control module respectively with input sequencing module control terminal and
Input selecting module control terminal connection, the second output terminal of control module respectively with the control terminal of RAM Read-write Catrol module, 16
The control terminal of road parallel processing module is connected with the control terminal of Coefficient generation module, and the third output end of control module and output are adjusted
The control terminal of sequence module connects, and the 4th output end of control module is connect with external pulse compression result output signal.
It should be noted that external 65536 point datas for carrying out pulse compression, which are divided into 16 channels, carries out data input, and
First data number according to the 1st channel is that first data number in the 0, the 2nd channel is the of the 1, the 16th channel
It is second data number in the 16, the 2nd channel is 17 that one data number, which is second data number in the 15, the 1st channel,
65536 point datas are numbered in the mode that second data number in the 16th channel is 31；And 65536 point data with 16
The form of complement code is stored.
Each channel in 16 channels inputs a data within a clock cycle, thus external progress pulse compression
65536 point datas need 4096 clock cycle to complete data input.
Specifically, control module generates the input indicative signal input_flag of high level, it is to be processed to be used to indicate input
65536 point datas；The control module generates the output indication signal output_flag of high level, is used to indicate output arteries and veins
Rush compression result；And the control module generates 15 operation indication signal step_sig [14:0], in 16 tunnel parallel processings
During module is run, high 3 of 15 operation indication signal step_sig [14:0] are used to indicate 16 road parallel processing modules
Carry out the grade of operation, wherein the 0th~3 grade is Fast Fourier Transform (FFT), and the 4th grade is matched filter operation, and the 5th~8 grade is inverse fast
Fast Fourier transformation, low 12 of 15 operation indication signal step_sig [14:0] are used to indicate -16 butterfly of every grade of base fortune
The number of calculation.
It should be understood that 65536 points of FFT/IFFT operation needs 4 grades of -16 butterfly computations of base, each grade carries out 4096
Secondary butterfly computation, matched filtering need to carry out 4096 parallel complex multiplication operations in 16 tunnels.
The input sequencing module, for being adjusted in such a way that Lothrus apterus stores to the input data in 16 channels
Sequence；It is not stored in same sub- memory module so that being divided into 1,16,256,4096 data between data number；
Further, input sequencing module is in input_flag signal 16 12 digit counter count of enabled lower generation, just
Value is respectively 0~15, and each clock enablement count device adds 16, and the value of such counter just represents the number of input data.Use tricks
Number device generates the number that block address signal block_addr [3:0] indicates the RAM of each data storage, formula block_
Addr [3:0]=count [11:8]+count [7:4]+count [3:0] is inputted according to 16 tunnel Zhi Jiang of signal block_addr
Data carry out sequencing, are then delivered to RAM memory module.Such storage mode is divided into 1,16,256,4096 between data number
Not in same sub- RAM, the parallel FFT processing in 16 tunnels may be implemented in point.
The input selecting module, for the output data for inputting sequencing module to be input to RAM memory module；Alternatively,
For the output data of rear sequencing module to be input to RAM memory module；
Specifically, the module selects the input data of RAM memory module at data input phase (input_flag=1)
Lead to input the sequencing data of sequencing module, is otherwise gated for the processing result of 16 road parallel processing modules.
The RAM memory module, for caching the 16 tunnel input datas for carrying out pulse compression, alternatively, being used for stored on-site
16 circuit-switched datas of sequencing module output afterwards；
Further, the RAM memory module includes the sub- RAM of 16 dual-ports, and number is RAM0-RAM15 respectively.
Specifically, the module is used for the temporary data received, and store the intermediate result of every level-one operation.The module by
The block RAM composition of 16 dual-ports, the bit wide of each block RAM is 40, depth 4096.Storage format of the data in RAM
Are as follows: in 40 high 20 be data real part, low 20 be data imaginary part, data are all the forms of complement code.It needs to illustrate
Be: the data real part imaginary part received from external data input channel is all 16, and the side of high-order zero padding is aligned using low level
Formula storage.
The RAM Read-write Catrol module, input sequencing module input 65536 point data when, generate write enable signal and
Every 16 circuit-switched data corresponding storage address in RAM memory module；In 16 circuit-switched datas for obtaining 16 road parallel processing modules of input
When, it generates and reads enable signal and preceding tune sequence control signal, sequencing module is from described before adjusting sequence control signal to be used to indicate before described
16 circuit-switched datas are read in RAM memory module, and sequencing is carried out to 16 circuit-switched datas of reading；Obtaining 16 road parallel processing modules
When 16 tunnel output data, write enable signal and rear tune sequence control signal are generated, is adjusted after adjusting sequence control signal to be used to indicate after described
Sequence module carries out sequencing to 16 circuit-switched datas that 16 road parallel processing module exports, and 16 circuit-switched datas after sequencing are written
In RAM memory module；When exporting sequencing module and exporting 65536 pulse compression result data, generates and read enable signal and defeated
Sequence control signal is adjusted out, and the output is adjusted sequence control signal to be used to indicate the output sequencing module and read from RAM memory module
16 tunnel pulse compression result data are taken, and are carried out sequencing output.
Specifically, the module is used to generate the read/write address and enable signal of RAM memory module.In data input phase
(input_flag=1), it draws high and writes enabled wea signal, and writing address signal addra is being write into enabled lower incremental count, 4096
A clock completes entire 65536 points of data input.In the data operation stage, butterfly is transported every time in the level Four operation of FFT processing
The data number interval of calculation is respectively 1,16,256 and 4096, when generating address also it is envisaged that the number of sequential storage
According to becoming the data of inverted order after FFT operation, therefore the generation of IFFT and FFT arithmetic address is different.Implementation
It is: 16 counter cnt0~cnt15 is first generated according to step_sig signal, this group of counter meets butterfly computation to data
Every requirement, then with this group of counter generate each butterfly computation need data address ram and RAM number, be sent to RAM and deposit
Store up module.When carrying out IFFT processing, what is stored in RAM memory module is the data of inverted order, raw with the counter by bit-reversed
It is numbered at address ram and RAM.The address generating mode and IFFT of matched filtering handle the identical of the first order.
The preceding sequencing module, for transporting the data of 16 sub- memory modules in RAM memory module according to -16 butterfly of base
The requirement of calculation, carry out sequence adjustment, and sequence 16 circuit-switched data adjusted is inputted into 16 road parallel processing modules；
The Coefficient generation module, for carrying out Fast Fourier Transform (FFT) or inverse quick Fu in 16 road parallel processing modules
In leaf transformation when, generate corresponding with 16 tunnel input datas twiddle factor；Alternatively, carrying out matching filter in 16 road parallel processing modules
When wave operation, matched filtering coefficient corresponding with 16 tunnel input datas is generated；
16 road parallel processing module, pair for sending sequence 16 circuit-switched data adjusted and Coefficient generation module
It answers twiddle factor to carry out -16 butterfly computation of base, obtains Fast Fourier Transform (FFT) result；
16 road parallel processing module is also used to pair for sending Fast Fourier Transform (FFT) result and Coefficient generation module
It answers matched filtering coefficient to carry out complex multiplication operation, obtains matched filtering result；
16 road parallel processing module is also used to send matched filtering result data with Coefficient generation module corresponding
Twiddle factor carries out -16 butterfly computation of base, obtains pulse compression result；
Further, 16 road parallel processing module is based on -16 butterfly processing element of base, and uses -16 butterfly of base
The complex multiplier of shape arithmetic element realizes the process of matched filter operation；If 16 road parallel processing module carries out quick Fu
In leaf transformation, then before sequencing module obtain 16 pending datas from RAM memory module every time, Coefficient generation module is real-time every time
The corresponding twiddle factor of 16 pending datas is generated, then 16 pending datas and 16 pending data difference
Input of the corresponding twiddle factor as -16 butterfly processing element of base, and 4096 bases-of level-one are completed in pipelined fashion
16 butterfly computations, thus result of the result of -16 butterfly computation of level Four base as Fast Fourier Transform (FFT)；If 16 tunnel is parallel
Processing module carries out matched filter operation, then preceding sequencing module obtains 16 Fast Fourier Transform (FFT)s from RAM memory module every time
Result data, Coefficient generation module generate the corresponding matched filtering of 16 Fast Fourier Transform (FFT) result datas in real time every time
Coefficient, then 16 Fast Fourier Transform (FFT) result datas and 16 Fast Fourier Transform (FFT) result data corresponding
Input with filter factor as 16 complex multipliers, the output of 16 complex multipliers is as this matched filter operation
As a result, and complete 4096 complex multiplication operations in pipelined fashion, to complete the parallel matching filter in 4096 16 tunnels
Wave operation；If 16 road parallel processing module carries out inverse fast fourier transform, preceding sequencing module stores mould from RAM every time
Block obtains 16 matched filter operation result datas and takes conjugation to it, and Coefficient generation module generates 16 matching filters in real time every time
The corresponding twiddle factor of wave operation result data, then 16 take conjugation after matched filter operation result data and 16
A corresponding twiddle factor of matched filter operation result data taken after being conjugated is as the defeated of -16 butterfly processing element of base
Enter, and complete 4096-16 butterfly computations of base of level-one in pipelined fashion, thus the result of-16 butterfly computation of level Four base
The result being conjugated as inverse Fourier transform is taken again.
Further, 16 road parallel processing modules complete the pulse compression of 65536 point datas, need to carry out at 65536 points
The Fast Fourier Transform (FFT) of data, 65536 point datas inverse fast fourier transform, the matched filter operation of 65536 point datas,
Wherein, the Fast Fourier Transform (FFT) of 65536 point datas, 65536 point datas inverse fast fourier transform be respectively necessary for carry out four
Grade-16 butterfly computation of base, and every grade of-16 butterfly computation of base includes 4096-16 butterfly computations of base, the matching of 65536 point datas
Filtering operation includes the parallel complex multiplication operation in 4096 16 tunnels.
Sequencing module, the operation result carry out sequence adjustment for exporting 16 road parallel processing modules make it after described
According to Lothrus apterus storage mode stored on-site in RAM memory module；
The spilling arbitration module, the operation result for exporting to 16 road parallel processing module carry out spilling bit wide
Judgement will overflow bit wide and be sent to data truncation module to obtain overflowing bit wide；
The module is specific to judge regular foundation for carrying out spilling judgement to the data after 16 road parallel processing module operations
Following table carries out, and obtains the spilling bit wide of every group of 16 data of data, then takes the maximum overflowed in all operation results of level-one
It is worth the spilling bit wide ovflow_num as this grade, is sent to data cutout module.
| Number | High 5 place value | Overflow digit |
| 0 | 00000/11111 | 0 |
| 1 | 00001/11110 | 1 |
| 2 | 0001x/1110x | 2 |
| 3 | 001xx/110xx | 3 |
| 4 | 01xxx/10xxx | 4 |
The data truncation module, the spilling bit wide for sending according to arbitration module is overflowed, will be from RAM memory module
The data of reading are shifted accordingly, obtain 16 valid data；
Specifically, the spilling bit wide overflow_num [3:0] that the module will be generated according to arbitration module is overflowed, it will be from
The data read in RAM memory module carry out moving to right overflow_num, before fill sign bit (highest order), obtain in this way
Data maximum have 16 significance bits, 20 bit wides are not overflowed after operation, carry out also will do it when operation again cuts
It takes, to guarantee data precision to greatest extent.
The output sequencing module, the pulse compression knot for will be stored in the RAM memory module after displacement
Fruit carries out sequencing and exports；
Specifically, the module is used to carry out sequencing to the result after data operation, make in the way of the parallel sequence in 16 tunnels
Output, with inputting, sequencing module is similar, and 16 read from RAM memory module every time are generated according to output_flag signal
Then the number of data generates address and the number of sub- RAM according to number, reads the data in sub- RAM and carry out sequencing, as a result
Along output.
The embodiment of the present invention also provides a kind of method for realizing 65536 pulses compression based on FPGA, the method includes
Following steps:
Step 1,16 input datas are obtained in each clock cycle, and 16 input datas is deposited according to Lothrus apterus
The mode of storage is stored respectively in 16 sub- memory modules；To obtain 65536 point datas by 4096 clock cycle, and deposit
It is stored in RAM memory module；
Step 2,16 pending datas are obtained from RAM memory module；
Step 3, data truncation module carries out 16 pending datas according to the shift amount for overflowing arbitration module output
Displacement；The shift amount initial value for overflowing arbitration module output is zero；
Step 4, the sequence of 16 pending datas after displacement is adjusted to base -16 butterfly computation rule by preceding sequencing module
Sequence；
Step 5,16 pending datas after sequencing are sent to 16 road parallel processing modules by the preceding sequencing module, and
Coefficient generation module generates the corresponding twiddle factor of 16 pending datas, and is sent to 16 road parallel processing modules；
Step 6,16 road parallel processing module is according to 16 pending datas received and corresponding twiddle factor,
- 16 butterfly computation of base is carried out, -16 butterfly computation result of base of this group of data is obtained；
Step 7, the spilling arbitration module carries out spilling judgement to -16 butterfly computation result of base, obtains displacement position
Number；
Step 8, the storage by -16 butterfly computation result of base according to 16 pending datas in RAM memory module
Position carries out stored on-site；
Step 9, step 2 to step 8 is repeated 4096 times in pipelined fashion, obtains first order butterfly computation knot
Fruit；
Step 10, step 2 to step 9 is repeated 4 times, obtains the Fourier transformation result of 65536 point datas；At this time
The data stored in the RAM memory module are 65536 point datas after Fast Fourier Transform (FFT)；
Step 11, the data after obtaining 16 Fast Fourier Transform (FFT)s in RAM memory module；
Step 12, data truncation module according to overflow arbitration module output shift amount, to 16 pending datas into
Row displacement；
Step 13, the sequence of the data after 16 Fast Fourier Transform (FFT)s after displacement is adjusted to base-by preceding sequencing module
The sequence of 16 butterfly computations rule；
Step 14, the data after 16 Fast Fourier Transform (FFT)s after sequencing are sent to 16 tunnels simultaneously by the preceding sequencing module
Row processing module, and Coefficient generation module generates the corresponding matched filtering coefficient of data after 16 Fast Fourier Transform (FFT)s, and
It is sent to 16 road parallel processing modules；
Step 15,16 road parallel processing module is according to data after 16 Fast Fourier Transform (FFT)s received and right
The matched filtering coefficient answered carries out complex multiplication operation, obtains the matched filter operation result of this group of data；
Step 16, the spilling arbitration module carries out spilling judgement to the matched filter operation result, obtains displacement position
Number；
Step 17, the matched filter operation result is stored according to the data after 16 Fast Fourier Transform (FFT)s in RAM
Storage location in module carries out stored on-site；
Step 18, step 11 to step 17 is repeated 4096 times in pipelined fashion, obtains matched filter operation
As a result；The data stored in the RAM memory module at this time are 65536 point datas after matched filter operation；
Step 19, the data after obtaining 16 matched filter operations in RAM memory module；
Step 20, data truncation module is according to the shift amount for overflowing arbitration module output, to 16 matched filter operations
Data afterwards are shifted；
Step 21, the sequence of the data after 16 matched filter operations after displacement is adjusted to base -16 by preceding sequencing module
The sequence of butterfly computation rule；
Step 22, the preceding sequencing module is sent to after the data after 16 matched filter operations after sequencing are taken conjugation
16 road parallel processing modules, and Coefficient generation module generates the corresponding twiddle factor of data after 16 matched filter operations, and
It is sent to 16 road parallel processing modules；
Step 23,16 road parallel processing module is according to the data and correspondence after 16 matched filter operations received
Twiddle factor, carry out -16 butterfly computation of base, obtain -16 butterfly computation result of base of this group of data；
Step 24, the spilling arbitration module carries out spilling judgement to -16 butterfly computation result of base, obtains displacement position
Number；
Step 25, -16 butterfly computation result of base is taken and is existed after being conjugated according to the data after 16 matched filter operations
Storage location in RAM memory module carries out stored on-site；
Step 26, step 19 to step 25 is repeated 4096 times in pipelined fashion, obtains first order butterfly fortune
Calculate result；
Step 27, step 19 to step 26 is repeated 4 times, the data after obtaining 65536 matched filter operations
Inverse Fourier transform is as a result, i.e. pulse compression result；The data stored in the RAM memory module at this time are that pulse is compressed
65536 point datas；
Step 28, data truncation module is read according to the shift amount for overflowing arbitration module output from RAM memory module
The 65536 compressed data of pulse taken are shifted；
Step 29, output sequencing module is by the pulse compression result carry out sequence adjustment after displacement, and exports.
Specifically, be the structural schematic diagram of 16 road provided in an embodiment of the present invention parallel processing module as shown in Figure 3, it will
FFT processing and matched filtering processing are united, which improves -16 butterfly processing element of base, reduces operation and prolongs
When, and the operation of energy compatible processing matched filtering.The design of the module is described in detail below.
X0~x15 is the data (FFT or matched filtering) for carrying out once-through operation in figure, be real part imaginary part is all 16 bit complements
Plural number, f0~f15 be carry out once-through operation coefficient, in FFT operation, this group of coefficient is twiddle factor corresponding with data,
When carrying out matched filter operation, this group of coefficient is matched filtering coefficient corresponding with data.
C0~C15 is complex multiplier in figure, is directly realized with the inside DSP of FPGA, and input bit wide is 16 plural numbers, defeated
Bit wide is 20 plural numbers out, and type is truncated as convergence rounding-off, completes a complex multiplication and needs to consume 4 clocks.C16~
C23 is also complex multiplier, is equally realized with DSP inside FPGA, is inputted as the plural number of 20 and 16, and output is truncated low 16
20 plural numbers are obtained, a complex multiplication is completed and needs to consume 4 clocks, wherein 16 of complex multiplier C16~C23
Coefficient real and imaginary parts are listed in the table below:
| Multiplier | Coefficient real part | Coefficient imaginary part | Multiplier | Coefficient real part | Coefficient imaginary part |
| C16 | 16′h2d41 | 16′hd2bf | C20 | 16′h187d | 16′hc4e0 |
| C17 | 16′hd2bf | 16′hd2bf | C21 | 16′h187d | 16′hc4e0 |
| C18 | 16′h3b20 | 16′he783 | C22 | 16′hd2bf | 16′hd2bf |
| C19 | 16′h2d41 | 16′hd2bf | C23 | 16′hc4e0 | 16′h187d |
" D4 " operation is 4 clocks that data flowing water is delayed in figure, it is therefore an objective to synchronous with the result of complex multiplication operation.
In figure "-jD " operation for first by data imaginary part real part exchange position imaginary part is negated again, then flowing water be delayed 4 when
Clock.
Indicate that first operand, c+id indicate second operand, as a result indicated with x+iy, explanation figure with a+ib below
In operation.
Two 20 digits is directly are added by "+" operation in figure, x=a+c, y=b+d.
"-" operates in figure are as follows: first operation data subtracts second operand, i.e. x=a-c, y=b-d.
" j+ " is operated in figure are as follows: first operation data is plus second operand multiplied by the value of j, i.e. x=a-d, y=b+
c。
" j- " is operated in figure are as follows: first operand subtracts second operand multiplied by the value of j, i.e. x=a+d, y=b-c.
" S " is data selection in figure, and the result output of final step operation is selected when carrying out FFT operation, is matched
When filtering operation, the result of complex multiplication is selected to export.
Further, the flow diagram of Coefficient generation module generation coefficient provided in an embodiment of the present invention is as shown in Figure 4.
First illustrate the generative theory of matched filtering coefficient before the process for illustrating to generate coefficient.
Matched filtering coefficient generates formula are as follows:
Fr=[- fs/2:fs/nrn:fs/2-fs/nrn]；
Fr=fftshift (fr)
SR=exp (j*pi*tp/B*Fr2)；
Wherein, fs indicate sample frequency, nrn indicate distance to points, fr indicate frequency domain in frequency range, Fr indicate
The range of zero-frequency frequency in the frequency domain at midpoint, tp indicate pulse width, and B indicates signal bandwidth, and SR indicates matched filter
Coefficient, the effect of fftshift () function are among composing 0 frequency point shift frequency.
It enables
Cnt=[- nrn/2:nrn/2-1]；
Cnt2=fftshift (cnt)；
Gama=π * tp*B*fs2/nrn2
It brings into the formula of SR and obtains:
SR=exp (j* π * tp/B* (cnt2.^2) * (fs^2/nrn^2))；
=exp (j*gama*cnt2)
Wherein cnt, cnt2 and gama are nonsensical, are the intermediate variables for calculating and generating for convenience.
The range of cnt2 is that 0~32767, -32768~-1, cnt2 will be carried out square when generating matched filter coefficient
Operation, therefore its absolute value is indicated with a counter when realizing.Gama can be calculated in advance with matlab, when with 38
It can satisfy the needs of most frequency modulation rates when quantization, the value for needing to modify gama under different occasions can generate response
Matched filtering coefficient.
It generates coefficient and needs first to design a trigonometric function look-up table:
A trigonometric table first is designed with matalb: by the cosine value of a cycle, carrying out 65536 point extractions, then
128 cosine data are one group totally 512 groups, and every group of data carry out once fitting with least square method, obtained zero degree term coefficient
As the base of this 128 data, unit offset of the Monomial coefficient as this 128 data therefore can with base and offset
To restore the cosine value of this 128 data.
Due to the symmetry of trigonometric function, base and the offset in 1/2 period are only stored, wherein base is quantified with 24, and offset is used
11 quantizations, base are stored in high-order offset in the data that low level forms 35.The cosine function obtained in this way has 16 digits
According to precision.When carrying out FFT, IFFT and matched filter operation, the address of trigonometric table is first generated according to step_sig, is tabled look-up
Twiddle factor or matched filtering coefficient can be generated according to base and offset afterwards.
The process flow of Coefficient generation module is as follows:
Judged whether carrying out matched filter operation according to high 3 of step_sig signal after entirely module brings into operation,
Matched filter operation is currently carried out when this 3 value is 4, what is otherwise carried out is FFT/IFFT operation.
When carrying out matched filtering, generates matched filtering coefficient and has the following steps:
(1) one group of 16 number, the group # and the data for carrying out a butterfly computation are generated according to step_sig signal
It is corresponding.
(2) number carries out sequencing, the fftshift operation being equivalent in formula, but what is obtained is absolute value, specifically
When the value of number is greater than 32768, use 65536 subtracts the number and obtains fr, and the value of number is directly otherwise assigned to fr, that is,
Fa in formula.
(3) square of fr is sought.
(4) square being multiplied matched filtering parameter gama and fr.
(5) it is intercepted the result of product to obtain address.
(6) product is intercepted to obtain address, the quantization address obtained after specifically intercepting is the triangle letter of actual value
512 times of number variable.
(7) according to address by tabling look-up to obtain base and slope.
(8) matched filtering coefficient is finally calculated according to base, slope and address offset, specifically slope is inclined multiplied by address
It moves and adds base.
When carrying out FFT/IFFT operation, generates matched filtering coefficient and has the following steps:
(1) one group of 16 number, the group # and the data for carrying out a butterfly computation are generated according to step_sig signal
It is corresponding.
(2) address can be directly generated according to number, the value of specifically address is 256 times of number value.
(3) according to address by tabling look-up to obtain base and slope.
(4) it is finally obtained according to base, slope and address offset obtains matched filtering coefficient, specifically slope is multiplied by address offset
Along with base.
To sum up, (1) problem slow for traditional design processing speed, the embodiment of the present invention design a 16 tunnel parallel processings
Module carries out FFT/IFFT processing or process of pulse-compression parallel, mentions as core processing unit, 16 tunnel processing module Ke Yi
The speed of high disposal；(2) in traditional design method, highest supports 4 tunnels to output and input parallel, design of the embodiment of the present invention
One parallel input/output interface in 16 tunnels improves the interface rate of design module；(3) more for traditional design method occupancy resource
The problem of, the embodiment of the present invention designs what core processing module was multiplexed by unified control logic, with stored on-site mode
It realizes the multiplexing of data buffer storage RAM, saves resource.Further with regards to twiddle factor and matched filtering coefficient, using trigonometric function point
Section linearisation storage, the mode for interpolation of then tabling look-up generate in real time, further save resource.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of device for realizing 65536 pulses compression based on FPGA, the input terminal of described device and external progress pulse pressure
The connection of the 16 tunnel input data channel Suo, the output end of described device are connect with external pulse compression result output channel, special
Sign is that described device includes: input sequencing module, inputs selecting module, RAM memory module, RAM Read-write Catrol module, number
According to truncation module, preceding sequencing module, 16 road parallel processing modules, rear sequencing module, Coefficient generation module, output sequencing module,
Overflow arbitration module, control module；
Wherein, the input terminal of the input sequencing module is connect with the external 16 tunnel input data channels for carrying out pulse compression, defeated
The output end for entering sequencing module is connect with the first input end of input selecting module, and the output end and RAM for inputting selecting module are deposited
The input terminal connection of module is stored up, the first output end of RAM Read-write Catrol module is connect with the control terminal of RAM memory module, and RAM is read
The second output terminal for writing control module is connect with the control terminal of preceding sequencing module, the third output end of RAM Read-write Catrol module with
The control terminal connection of sequencing module, the output end of RAM memory module are connect with the first input end of data truncation module afterwards, data
First output end of truncation module is connect with the input terminal of preceding sequencing module, the output end of preceding sequencing module and 16 tunnel parallel processings
The first input end of module connects, and the output end of Coefficient generation module is connect with the second input terminal of 16 road parallel processing modules,
The output end of 16 road parallel processing modules is connect with the input terminal of the input terminal of rear sequencing module, spilling arbitration module respectively, after
The output end of sequencing module is connect with the second input terminal of input selecting module, overflows the output end and data truncation of arbitration module
Second input terminal of module connects, and the second output terminal of data truncation module is connect with the input terminal of output sequencing module, described
The output end of output sequencing module is connect with external pulse compression result output channel, the input terminal of the control module and outside
Carry out the control signal connection of pulse compression, the first output end of control module respectively with the input control terminal of sequencing module and defeated
Enter selecting module control terminal connection, the second output terminal of control module respectively with the control terminal of RAM Read-write Catrol module, 16 tunnels
The control terminal of parallel processing module is connected with the control terminal of Coefficient generation module, the third output end and output sequencing of control module
The control terminal of module connects, and the 4th output end of control module is connect with external pulse compression result output signal.
2. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 1, which is characterized in that outer
65536 point datas that portion carries out pulse compression are divided into 16 channels and carry out data input, and according to first points in the 1st channel
It is 0 according to number, the first point data number in the 2nd channel is 1, and successively the first point data number to the 16th channel is 15,
The second point data number in the 1st channel is that the second point data number in the 16, the 2nd channel is 17, successively to the 16th channel
Second point data number be 31 mode 65536 point datas are numbered；And 65536 point data in the form of 16 bit complements
It is stored；
Each channel in 16 channels inputs a point data within a clock cycle, thus external progress pulse compression
65536 point datas need 4096 clock cycle to complete data input.
3. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 2, which is characterized in that institute
The sub- memory module that RAM memory module includes 16 dual-ports is stated, number is RAM0-RAM15 respectively, every a sub- memory module
Bit wide is 40, depth 4096；Storage format of the data in every sub- memory module are as follows: the reality of high 20 storing datas
Portion, the imaginary part of low 20 storing datas, the real and imaginary parts of data are stored in the form of complement code, and every sub- memory module
Store 4096 point datas.
4. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 2, which is characterized in that
The input sequencing module, for carrying out sequencing to the input data in 16 channels in such a way that Lothrus apterus stores；From
And the data for being divided into 1,16,256,4096 between data number are not stored in same sub- memory module；
The input selecting module, for the output data for inputting sequencing module to be input to RAM memory module；Alternatively, being used for
The output data of rear sequencing module is input to RAM memory module；
The RAM memory module, for caching the 16 tunnel input datas for carrying out pulse compression, alternatively, for being adjusted after stored on-site
16 circuit-switched datas of sequence module output；
The RAM Read-write Catrol module, for generating the read/write address and the enabled letter of corresponding read-write of the RAM memory module
Number；
The preceding sequencing module, for by the data of 16 sub- memory modules in RAM memory module according to -16 butterfly computation of base
It is required that carry out sequence adjustment, and sequence 16 circuit-switched data adjusted is inputted into 16 road parallel processing modules；
The Coefficient generation module, for carrying out Fast Fourier Transform (FFT) or inverse fast Fourier in 16 road parallel processing modules
When transformation, twiddle factor corresponding with 16 tunnel input datas is generated；Alternatively, carrying out matched filtering fortune in 16 road parallel processing modules
When calculation, matched filtering coefficient corresponding with 16 tunnel input datas is generated；
16 road parallel processing module, the corresponding rotation for sending sequence 16 circuit-switched data adjusted with Coefficient generation module
Transposon carries out -16 butterfly computation of base, obtains Fast Fourier Transform (FFT) result；
16 road parallel processing module, corresponding for being also used to send Fast Fourier Transform (FFT) result with Coefficient generation module
Complex multiplication operation is carried out with filter factor, obtains matched filtering result；
16 road parallel processing module is also used to the corresponding rotation for sending matched filtering result data with Coefficient generation module
The factor carries out -16 butterfly computation of base, obtains pulse compression result；
Sequencing module after described, the operation result carry out sequence adjustment for exporting 16 road parallel processing modules, make its according to
Lothrus apterus storage mode stored on-site is in RAM memory module；The operation result of 16 road parallel processing module output is fast
Fast Fourier transformation as a result, matched filtering as a result, pulse compression result；
The spilling arbitration module, the operation result for exporting to 16 road parallel processing module carry out spilling bit wide and sentence
It is disconnected, to obtain overflowing bit wide, bit wide will be overflowed and be sent to data truncation module；
The data truncation module, the spilling bit wide for sending according to arbitration module is overflowed, will read from RAM memory module
Data shifted accordingly, obtain 16 valid data；
The output sequencing module, for will by the pulse compression result that stores in the RAM memory module after displacement into
Row sequencing simultaneously exports.
5. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 4, which is characterized in that institute
16 road parallel processing modules are stated based on -16 butterfly processing element of base, and using the complex multiplication of -16 butterfly processing element of base
The process of device realization matched filter operation；If 16 road parallel processing module carries out Fast Fourier Transform (FFT), preceding sequencing mould
Block obtains 16 pending datas from RAM memory module every time, and Coefficient generation module generates 16 pending datas in real time every time
Corresponding twiddle factor, then 16 pending datas and the corresponding twiddle factor conduct of 16 pending datas
The input of-16 butterfly processing element of base, and 4096-16 butterfly computations of base of level-one are completed in pipelined fashion, until
To -16 butterfly computation of level Four base as a result, and as the result of Fast Fourier Transform (FFT)；If the 16 tunnel parallel processing mould
Block carries out matched filter operation, then preceding sequencing module obtains 16 point quick Fourier transformation results numbers from RAM memory module every time
According to, Coefficient generation module generates the corresponding matched filtering coefficient of 16 point quick Fourier transformation results data in real time every time,
Then 16 point quick Fourier transformation results data and the corresponding matching filter of 16 point quick Fourier transformation results data
Input of the wave system number as 16 complex multipliers obtains the output of 16 complex multipliers by complex multiplication operation, and will
Its as this matched filter operation as a result, and in pipelined fashion complete 4096 complex multiplication operations, thus complete
At the parallel matched filter operation in 4096 16 tunnels；If 16 road parallel processing module carries out inverse fast fourier transform,
Preceding sequencing module obtains 16 matched filter operation result datas from RAM memory module every time and takes conjugation to it, and coefficient generates
Module generates the corresponding twiddle factor of 16 matched filter operation result datas in real time every time, then 16 points take conjugation after
Matched filter operation result data and 16 points of corresponding twiddle factors of matched filter operation result data taken after conjugation
As the input of-16 butterfly processing element of base, and 4096-16 butterfly computations of base of level-one are completed in pipelined fashion, directly
To obtain -16 butterfly computation of level Four base as a result, and being taken again to it and being conjugated result as inverse Fourier transform.
6. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 1, which is characterized in that 16
Road parallel processing module complete 65536 point datas pulse compression, need to carry out 65536 point datas Fast Fourier Transform (FFT),
The inverse fast fourier transform of 65536 point datas, the matched filter operation of 65536 point datas, wherein 65536 point datas it is fast
Fast Fourier transformation, 65536 point datas inverse fast fourier transform be respectively necessary for carrying out -16 butterfly computation of level Four base, and it is every
Grade-16 butterfly computation of base includes 4096-16 butterfly computations of base, and the matched filter operation of 65536 point datas includes 4096 times 16
The parallel complex multiplication operation in road.
7. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 4, which is characterized in that institute
The input indicative signal input_flag that control module generates high level is stated, is used to indicate and inputs 65536 point datas to be processed；
The control module generates the output indication signal output_flag of high level, is used to indicate output pulse compression result；And institute
The operation indication signal step_sig [14:0] that control module generates 15 is stated, during the operation of 16 road parallel processing modules, 15
High 3 of the operation indication signal step_sig [14:0] of position are used to indicate the grade that 16 road parallel processing modules carry out operation,
In, 16 road parallel processing modules carry out in the grade of operation: the 0th~3 grade is Fast Fourier Transform (FFT), and the 4th grade is transported for matched filtering
It calculates, the 5th~8 grade is inverse fast fourier transform, and low 12 of 15 operation indication signal step_sig [14:0] are for referring to
Show the number of -16 butterfly computation of every grade of base.
8. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 7, which is characterized in that institute
State input sequencing module generated under the enabled effect of input indicative signal input_flag 16 12 digit counter count [11:
0], 16 12 digit counters respectively with the external 16 tunnel input datas for carrying out pulse compression, and 16 12 digit counters
Initial value is respectively 0~15, and the value of each counter is used to characterize the number of input data all the way.
9. a kind of device for realizing 65536 pulses compression based on FPGA according to claim 8, which is characterized in that
The RAM Read-write Catrol module generates write enable signal and every 16 when inputting sequencing module 65536 point data of input
Circuit-switched data corresponding storage address in RAM memory module；It is raw when obtaining 16 circuit-switched data of 16 road parallel processing modules of input
At enable signal and preceding tune sequence control signal is read, sequencing module is deposited from the RAM before adjusting sequence control signal to be used to indicate before described
16 circuit-switched datas are read in storage module, and sequencing is carried out to 16 circuit-switched datas of reading；On 16 tunnels for obtaining 16 road parallel processing modules
When output data, write enable signal and rear tune sequence control signal are generated, adjusts sequence control signal to be used to indicate rear sequencing mould after described
Block carries out sequencing to 16 circuit-switched datas that 16 road parallel processing module exports, and the 16 circuit-switched datas write-in RAM after sequencing is deposited
It stores up in module；When exporting sequencing module 65536 pulse compression result data of output, generates and read enable signal and output sequencing
Signal is controlled, the output adjusts sequence control signal to be used to indicate the output sequencing module and reads 16 tunnels from RAM memory module
Pulse compression result data, and carried out sequencing output.
10. a kind of method for realizing 65536 pulses compression based on FPGA, which is characterized in that described method includes following steps:
Step 1,16 input datas are obtained in each clock cycle, and 16 input datas are stored according to Lothrus apterus
Mode is stored respectively in 16 sub- memory modules；To obtain 65536 point datas by 4096 clock cycle, and it is stored in
In RAM memory module；
Step 2,16 pending datas are obtained from RAM memory module；
Step 3, data truncation module moves 16 pending datas according to the shift amount for overflowing arbitration module output
Position；The shift amount initial value for overflowing arbitration module output is zero；
Step 4, the sequence of 16 pending datas after displacement is adjusted to the suitable of base -16 butterfly computation rule by preceding sequencing module
Sequence；
Step 5,16 pending datas after sequencing are sent to 16 road parallel processing modules, and coefficient by the preceding sequencing module
Generation module generates the corresponding twiddle factor of 16 pending datas, and is sent to 16 road parallel processing modules；
Step 6,16 road parallel processing module is carried out according to 16 pending datas received and corresponding twiddle factor
- 16 butterfly computation of base obtains -16 butterfly computation result of base of 16 pending datas；
Step 7, the spilling arbitration module carries out spilling judgement to -16 butterfly computation result of base, obtains shift amount；
Step 8, the storage location by -16 butterfly computation result of base according to 16 pending datas in RAM memory module
Carry out stored on-site；
Step 9, step 2 to step 8 is repeated 4096 times in pipelined fashion, obtains first order butterfly computation result；
Step 10, step 2 to step 9 is repeated 4 times, obtains the Fourier transformation result of 65536 point datas；It is described at this time
The data stored in RAM memory module are 65536 point datas after Fast Fourier Transform (FFT)；
Step 11, the transformed data of 16 point quick Fouriers are obtained from RAM memory module；
Step 12, data truncation module is according to the shift amount for overflowing arbitration module output, after the transformation of 16 point quick Fouriers
Data shifted；
Step 13, the sequence of the transformed data of 16 point quick Fouriers after displacement is adjusted to -16 butterfly of base by preceding sequencing module
The sequence of shape operation rule；
Step 14, the transformed data of 16 point quick Fouriers after sequencing are sent to 16 tunnels and located parallel by the preceding sequencing module
Module is managed, and Coefficient generation module generates the corresponding matched filtering coefficient of the transformed data of 16 point quick Fouriers, and sends
To 16 road parallel processing modules；
Step 15,16 road parallel processing module is according to the transformed data of 16 point quick Fouriers that receive and corresponding
Matched filtering coefficient carries out complex multiplication operation, obtains the matched filter operation knot of the transformed data of 16 point quick Fouriers
Fruit；
Step 16, the spilling arbitration module carries out spilling judgement to the matched filter operation result, obtains shift amount；
Step 17, by the matched filter operation result according to the transformed data of 16 point quick Fouriers in RAM memory module
In storage location carry out stored on-site；
Step 18, step 11 to step 17 is repeated 4096 times in pipelined fashion, obtains matched filter operation result；
The data stored in the RAM memory module at this time are 65536 point datas after matched filter operation；
Step 19, the data after obtaining 16 matched filter operations in RAM memory module；
Step 20, data truncation module is according to the shift amount for overflowing arbitration module output, after 16 matched filter operations
Data are shifted；
Step 21, the sequence of the data after 16 matched filter operations after displacement is adjusted to -16 butterfly of base by preceding sequencing module
The sequence of operation rule；
Step 22, the preceding sequencing module is sent to 16 tunnels after the data after 16 matched filter operations after sequencing are taken conjugation
Parallel processing module, and Coefficient generation module generates the corresponding twiddle factor of data after 16 matched filter operations, and sends
To 16 road parallel processing modules；
Step 23,16 road parallel processing module is according to the data and corresponding rotation after 16 matched filter operations received
Transposon carries out -16 butterfly computation of base, -16 butterfly computation result of base of the data after obtaining 16 matched filter operations；
Step 24, the spilling arbitration module carries out spilling judgement to -16 butterfly computation result of base, obtains shift amount；
Step 25, -16 butterfly computation result of base is taken and is deposited according to the data after 16 matched filter operations in RAM after being conjugated
The storage location stored up in module carries out stored on-site；
Step 26, step 19 to step 25 is repeated 4096 times in pipelined fashion, obtains first order butterfly computation knot
Fruit；
Step 27, step 19 to step 26 is repeated 4 times, inverse Fu of the data after obtaining 65536 matched filter operations
In leaf transformation as a result, i.e. pulse compression result；The data stored in the RAM memory module at this time are that pulse is compressed
65536 point datas；
Step 28, data truncation module is according to the shift amount for overflowing arbitration module output, to what is read from RAM memory module
65536 compressed data of pulse are shifted；
Step 29, output sequencing module is by the pulse compression result carry out sequence adjustment after displacement, and exports.
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| CN108919200A (en) * | 2018-07-12 | 2018-11-30 | 中国船舶重工集团公司第七二四研究所 | A kind of any radar waveform Photographing On-line method based on FPGA |
| CN109101347B (en) * | 2018-07-16 | 2021-07-20 | 北京理工大学 | Pulse compression processing method of FPGA heterogeneous computing platform based on OpenCL |
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| CN109815546B (en) * | 2018-12-26 | 2022-12-13 | 中国电子科技集团公司第二十研究所 | Implementation method of high-speed parallel digital matched filter |
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