CN103559019A - Universal floating point full-pipeline FFT (Fast Fourier Transform) operation IP (Internet Protocol) core - Google Patents
Universal floating point full-pipeline FFT (Fast Fourier Transform) operation IP (Internet Protocol) core Download PDFInfo
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Abstract
The invention discloses a universal floating point full-pipeline FFT (Fast Fourier Transform) operation IP (Internet Protocol) core, which comprises an in-situ operation unit, a base-2 pipeline type butterfly operation unit and a result processing unit, wherein the in-situ operation unit is used for segmenting and sorting input digital signals, completing in-situ operation by means of address order reversal, sequentially caching the input digital signals in a way of keeping 256 points in each group by using a ping-pang cache method, and generating data which are convenient for butterfly operation input via screening of odd and even sequences; the base-2 pipeline type butterfly operation unit comprises multiple stages of butterfly pipeline operation units; a first-stage butterfly pipeline operation unit is used for receiving data generated by the in-situ operation unit, and then each stage of butterfly pipeline operation unit is connected with a previous stage butterfly pipeline operation unit respectively to calculate FFT operation output corresponding to the input of each point; the result processing unit is connected with the base-2 pipeline type butterfly operation unit, and is used for sorting the FFT operation output calculated by using the base-2 pipeline type butterfly operation unit.
Description
Technical field
The present invention relates to digital signal processing technique field, particularly the full flowing water FFT of a kind of general floating-point computing IP kernel.
Background technology
FFT(Fast Fourier Transform (FFT), Fast Fourier Transform) computing is digital signal conversion algorithm important in digital signal processing, and it is powerful, is widely used.Be confined to FPGA technique and integrated level, it is the mode of fixed point or block floating point mostly that the FPGA of FFT computing realizes, and adopts the Floating FFT computing IP kernel of these two kinds of modes except authorizing costliness, configures loaded down with trivial details problem of easily makeing mistakes, and also has following a few point defect:
1. precision is low, uses the method calculating process of fixed point or block floating point can produce serious accumulated error, and final FFT the possibility of result is caused to larger distortion;
2. signal indication is limited in scope, and with respect to the method for expressing of fixed-point number, floating number has larger expression scope, and corresponding floating point arithmetic also has larger dynamic range, and higher operational precision, is difficult for overflowing and accumulating arithmetic eror;
3. real-time is poor, and FFT processes framework and optimizes not, does not realize full water operation, and each FFT computing will wait until that last FFT computing finishes to start once again computing flow process, and real-time is poor;
4. there is defect in basic multiply-add operation device, and fixed point adder and multiplier is because fixed-point number computing lacks accuracy guarantee, and the IP kernel of floating dual MAC has long computing pipelining-stage, has greatly extended the computing time of FFT by synergistic effect.
Summary of the invention
The present invention is directed to prior art above shortcomings, the full flowing water FFT of a kind of general floating-point computing IP kernel is provided, its structure is bright and clear, configuration is simple, when guaranteeing operational precision, greatly improved the arithmetic speed of Floating FFT, simultaneously its be packaged into Floating FFT floating-point operation IP kernel can rapid deployment in different engineering application, easy to use, accelerate greatly the research and development progress of engineering, can in officely what is the need for and want in the engineering system of frequency-domain analysis calculating Fourier transform real-time.
The present invention is achieved through the following technical solutions:
The full flowing water FFT of a floating-point computing IP kernel, comprising:
Original position arithmetic element, in order to the digital signal piecemeal of input is arranged, first original position arithmetic element completes former bit arithmetic by address inverted order, then the method by ping-pong buffer by the digital signal of input the order buffer memory with 256 every group, then by sequence of parity, screen to produce and is convenient to the data that butterfly computation is inputted;
Base 2 flowing water type butterfly processing elements, comprise the butterfly flowing water arithmetic element of some grades, the butterfly flowing water arithmetic element of the first order receives the data that produce through original position arithmetic element, the butterfly flowing water arithmetic element of every one-level afterwards connects respectively the butterfly flowing water arithmetic element of upper level, to calculate corresponding every bit, inputs corresponding FFT computing output;
Result treatment unit, connects base 2 flowing water type butterfly processing elements, and the FFT computing that base 2 flowing water type butterfly processing elements are calculated output arranges;
Wherein, two result of calculations of the each output of base 2 flowing water type butterfly processing elements, every 256 result of calculations are once complete FFT computing flow process, result treatment unit completes the packing of parallel-serial conversion and 256 outputs and processes.
Preferably, original position arithmetic element adopts the fft algorithm of decimation in time to realize.
Preferably, the corresponding every bit of calculating in base 2 flowing water type butterfly processing elements is inputted corresponding FFT computing output and is comprised:
The data that produce through original position arithmetic element are carried out to multiply-add operation, and the twiddle factor of multiply-add operation is read by storer, and the result of calculation of the butterfly flowing water arithmetic element of every one-level is given respectively the memory buffer of the butterfly flowing water arithmetic element of next stage.
Preferably, butterfly flowing water arithmetic element comprises:
Butterfly computation subelement, in order to carry out butterfly computation;
Address generate subelement, the memory address in order to the result of calculation that produces butterfly computation subelement in next stage butterfly flowing water arithmetic element;
Sequential control subelement, connects butterfly computation subelement and address generate subelement, in order to produce sequential;
Some storeies, connect butterfly computation subelement and address generate subelement, in order to store the result of calculation of butterfly computation subelement and the twiddle factor of multiply-add operation.
Preferably, base 2 flowing water type butterfly processing elements comprise the butterfly flowing water arithmetic element of eight grades: the first butterfly flowing water arithmetic element to the eight butterfly flowing water arithmetic elements.
Preferably, the butterfly flowing water arithmetic element of every one-level completes butterfly computation 128 times by the mode of round-robin, with saving resource, takies.
Preferably, original position arithmetic element comprises:
Address inverted order subelement, in order to complete former bit arithmetic by address inverted order;
Some storeies, link address inverted order subelement, the digital signal in order to buffer memory after former bit arithmetic;
Odd even address screening subelement, connects some storeies, in order to screen by sequence of parity, produces the data that are convenient to butterfly computation input.
Accompanying drawing explanation
Shown in Fig. 1 is structural representation of the present invention;
Shown in Fig. 2 is the structural representation of original position arithmetic element of the present invention;
Shown in Fig. 3 is the structural representation of butterfly flowing water arithmetic element of the present invention.
Embodiment
Below with reference to accompanying drawing of the present invention; technical scheme in the embodiment of the present invention is carried out to clear, complete description and discussion; obviously; as described herein is only a part of example of the present invention; it is not whole examples; embodiment based in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work, belongs to protection scope of the present invention.
For the ease of the understanding to the embodiment of the present invention, below in conjunction with accompanying drawing, take specific embodiment and be further explained as example, and each embodiment does not form the restriction to the embodiment of the present invention.
Please refer to Fig. 1, the full flowing water FFT of a kind of general floating-point computing IP kernel that the present embodiment provides, comprising: original position arithmetic element, base 2 flowing water type butterfly processing elements, result treatment unit.
Original position arithmetic element, for the digital signal piecemeal of input is arranged, singularity due to FFT computing, the input data amount check that requires each FFT computing is corresponding to FFT count (the present invention is 256 points), and the inverted sequence that the true sequence number that requires the data of input is its corresponding scale-of-two sequence number is so-called former bit arithmetic, first original position arithmetic element completes former bit arithmetic by address inverted order module, then by the method for ping-pong buffer, will input the order buffer memory of data with 256 every group, then screen and produce the data that are convenient to butterfly computation input by sequence of parity.
Base 2 flowing water type butterfly processing elements, for the core calculations unit of FFT computing (adopts base 2FFT algorithm, this algorithm is prior art, the present invention does not repeat at this, technician can be with reference to data of literatures), comprise eight grades of similar butterfly flowing water arithmetic elements, to calculate corresponding every bit, input corresponding FFT computing output, first every one-level butterfly flowing water arithmetic element receives the butterfly computation result of upper level, after adjusting (former bit arithmetic), address enters base 2 flowing water type butterfly processing element and multiply-add operations, the twiddle factor of multiply-add operation is read by ROM, result of calculation is given respectively the input RAM buffer memory of next stage, RAM memory address is produced by special address generating module, whole calculating process completes under time-sequence control module instructs, to FFT computing each time, the mode of the butterfly flowing water arithmetic element of every one-level by round-robin completes 128 butterfly computations and greatly saved resource occupation, butterfly flowing water arithmetic element is used special-purpose multiplier and totalizer, and design is helped flowing water pattern, the expense that has reduced the multiplexing computing time bringing.The wherein multiplier of autonomous Custom Design, the thought that totalizer all adopts exponent mantissa parallel computation, reduced the computation delay of multiply-add operation; Totalizer has adopted Two-path thought, and leading zero computational algorithm and leading zero prediction algorithm have been realized by logical design, by reasonable interpolation register, make basic multiply-add operation unit and butterfly computing unit can input continuously continuous wave output, realized full pipeline computing pattern.
Result treatment unit, the FFT result that base 2 flowing water type butterfly processing elements are calculated arranges output, two result of calculations of the each output of base 2 flowing water type butterfly processing elements, every 256 result of calculations are once complete FFT computing flow process, and result treatment unit completes the packing of parallel-serial conversion and 256 outputs and processes.
In the present embodiment, base 2 flowing water type butterfly processing elements comprise the butterfly flowing water arithmetic element of eight grades: the first butterfly flowing water arithmetic element to the eight butterfly flowing water arithmetic elements, but the present invention does not limit at this, technician can design according to actual conditions.The butterfly flowing water arithmetic element of every one-level completes butterfly computation 128 times by the mode of round-robin, with saving resource, takies.
Please refer to Fig. 2, original position arithmetic element comprises: address inverted order subelement, in order to complete former bit arithmetic by address inverted order; Some storeies, link address inverted order subelement, the digital signal in order to buffer memory after former bit arithmetic; Odd even address screening subelement, connects some storeies, in order to screen by sequence of parity, produces the data that are convenient to butterfly computation input.In the present embodiment, original position arithmetic element adopts the fft algorithm of the decimation in time (DIT) of classical Cooley and Tukey proposition to realize, by address inverted order subelement, complete former bit arithmetic, by the input data of 256 every group of ping pong scheme buffer memorys, by sequence of parity, screen the data that produce butterfly computation input.
Please refer to Fig. 3, butterfly flowing water arithmetic element comprises: butterfly computation subelement, in order to carry out butterfly computation; Address generate subelement, the memory address in order to the result of calculation that produces butterfly computation subelement in next stage butterfly flowing water arithmetic element; Sequential control subelement, connects butterfly computation subelement and address generate subelement, in order to produce sequential; Some storeies, connect butterfly computation subelement and address generate subelement, in order to store the result of calculation of butterfly computation subelement and the twiddle factor of multiply-add operation.The twiddle factor of multiply-add operation is read by read only memory ROM, and result of calculation is given respectively the input random access memory ram buffer memory of next stage, and RAM memory address is produced by special address generate subelement, and module sequential is completed by sequential control subelement.
The full flowing water FFT of a kind of general floating-point provided by the invention computing IP kernel, can be used for the spectrum analysis in digital signal processing, and the pulse compression in Radar Signal Processing, moving-target detection etc., have great importance and purposes.The invention solves fixed point and block floating point FFT operational precision low, the problem such as signal indication is limited in scope, and computing real-time is poor.The digital information processing system that can be applied to easily to take FPGA be platform.
Example, moving-target detects in (MTD) application, radar echo signal can be directly inputted to signal input module of the present invention, and due to the existence of ping-pong buffer, user can independently select to intercept one piece of data and does FFT computing or directly the data of input continuously done to FFT computing; After signal input, every one-level is done former bit arithmetic to signal and is then entered butterfly operation module and take advantage of and add processing with twiddle factor, and multiply-add operation process is controlled by address generating module, calculates the frequency spectrum that each frequency is corresponding and exports.Result of calculation is sent into the output of result treatment unit, completes the fft analysis to radar echo signal.
The above; be only the present invention's embodiment preferably, but protection scope of the present invention is not limited to this, is anyly familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (7)
1. the full flowing water FFT of a general floating-point computing IP kernel, is characterized in that, comprising:
Original position arithmetic element, in order to the digital signal piecemeal of input is arranged, first described original position arithmetic element completes former bit arithmetic by address inverted order, then the method by ping-pong buffer by the digital signal of input the order buffer memory with 256 every group, then by sequence of parity, screen to produce and is convenient to the data that butterfly computation is inputted;
Base 2 flowing water type butterfly processing elements, comprise the butterfly flowing water arithmetic element of some grades, the described butterfly flowing water arithmetic element of the first order receives the data that produce through described original position arithmetic element, the described butterfly flowing water arithmetic element of every one-level afterwards connects respectively the described butterfly flowing water arithmetic element of upper level, to calculate corresponding every bit, inputs corresponding FFT computing output;
Result treatment unit, connects described base 2 flowing water type butterfly processing elements, and the FFT computing output that described base 2 flowing water type butterfly processing elements are calculated arranges;
Wherein, two result of calculations of the each output of described base 2 flowing water type butterfly processing elements, every 256 result of calculations are once complete FFT computing flow process, described result treatment unit completes the packing of parallel-serial conversion and 256 outputs and processes.
2. the full flowing water FFT of general floating-point according to claim 1 computing IP kernel, is characterized in that, described original position arithmetic element adopts the fft algorithm of decimation in time to realize.
3. the full flowing water FFT of general floating-point according to claim 1 computing IP kernel, is characterized in that, the corresponding every bit of calculating in described base 2 flowing water type butterfly processing elements is inputted corresponding FFT computing output and comprised:
The data that produce through described original position arithmetic element are carried out to multiply-add operation, the twiddle factor of multiply-add operation is read by storer, and the result of calculation of the described butterfly flowing water arithmetic element of every one-level is given respectively the memory buffer of the described butterfly flowing water arithmetic element of next stage.
4. the full flowing water FFT of general floating-point according to claim 3 computing IP kernel, is characterized in that, described butterfly flowing water arithmetic element comprises:
Butterfly computation subelement, in order to carry out butterfly computation;
Address generate subelement, the memory address in order to the result of calculation that produces described butterfly computation subelement in butterfly flowing water arithmetic element described in next stage;
Sequential control subelement, connects described butterfly computation subelement and described address generate subelement, in order to produce sequential;
Some storeies, connect described butterfly computation subelement and described address generate subelement, in order to store the result of calculation of described butterfly computation subelement and the twiddle factor of multiply-add operation.
5. the full flowing water FFT of general floating-point according to claim 1 computing IP kernel, is characterized in that, described base 2 flowing water type butterfly processing elements comprise the described butterfly flowing water arithmetic element of eight grades: the first butterfly flowing water arithmetic element to the eight butterfly flowing water arithmetic elements.
6. the full flowing water FFT of general floating-point according to claim 1 computing IP kernel, is characterized in that, the described butterfly flowing water arithmetic element of every one-level completes butterfly computation 128 times by the mode of round-robin, with saving resource, takies.
7. the full flowing water FFT of general floating-point according to claim 1 computing IP kernel, is characterized in that, described original position arithmetic element comprises:
Address inverted order subelement, in order to complete former bit arithmetic by address inverted order;
Some storeies, connect described address inverted order subelement, the digital signal in order to buffer memory after former bit arithmetic;
Odd even address screening subelement, connects described some storeies, in order to screen by sequence of parity, produces the data that are convenient to butterfly computation input.
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| CN105116380A (en) * | 2015-08-13 | 2015-12-02 | 电子科技大学 | Calculation method of sort type constant false alarm threshold |
| CN105446702A (en) * | 2015-11-05 | 2016-03-30 | 中国船舶重工集团公司第七二四研究所 | Broadband digital channelization parallel processing method based on serial FFT IP core |
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| CN109740749A (en) * | 2017-10-30 | 2019-05-10 | 北京深鉴智能科技有限公司 | The hardware realization apparatus and method that the full connection of high speed calculates |
| CN111429944A (en) * | 2020-04-17 | 2020-07-17 | 北京百瑞互联技术有限公司 | Codec development test optimization method and system |
| CN112163185A (en) * | 2020-09-30 | 2021-01-01 | 中国科学院计算技术研究所 | FFT/IFFT operation device and FFT/IFFT operation method based on the same |
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| CN105116380A (en) * | 2015-08-13 | 2015-12-02 | 电子科技大学 | Calculation method of sort type constant false alarm threshold |
| CN105446702A (en) * | 2015-11-05 | 2016-03-30 | 中国船舶重工集团公司第七二四研究所 | Broadband digital channelization parallel processing method based on serial FFT IP core |
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| CN108021781A (en) * | 2018-01-31 | 2018-05-11 | 中国电子科技集团公司第五十四研究所 | The FFT IP core designs and optimization method of a kind of parameterisable |
| CN111429944A (en) * | 2020-04-17 | 2020-07-17 | 北京百瑞互联技术有限公司 | Codec development test optimization method and system |
| CN112163185A (en) * | 2020-09-30 | 2021-01-01 | 中国科学院计算技术研究所 | FFT/IFFT operation device and FFT/IFFT operation method based on the same |
| CN112163185B (en) * | 2020-09-30 | 2023-11-28 | 中国科学院计算技术研究所 | FFT/IFFT operation device and FFT/IFFT operation method based on same |
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