CN105446702A - Broadband digital channelization parallel processing method based on serial FFT IP core - Google Patents
Broadband digital channelization parallel processing method based on serial FFT IP core Download PDFInfo
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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Abstract
The present invention discloses a broadband digital channelization parallel processing method based on a serial FFT IP core, and gives a method for designing a parallel FFT IP core based on the serial FFT core. According to the method disclosed by the present invention, after broadband signals intercepted by an electronic signal reconnaissance receiver are sampled by using a high-speed AD, data is grouped; parallel-serial conversion pipeline processing of the data is performed in groups; the parallel data is transformed into the serial data; and meanwhile, pipeline conversion processing can be guaranteed to be uninterruptedly carried out on the input parallel in a time sequence so as to achieve an effect of parallel data input and parallel data output. Moreover, due to a determined sequential relationship of the input data and output data, continuous input and continuous output of data flow are guaranteed. In a process of FPGA program verification, parameters, such as a bit width processed in each stage, a coefficient of a channel filter, a bit width of the channel filter, a bit width of an FFT twiddle factor and the like, are continuously modified, and under a situation of meeting design indexes, a resource occupation rate is reduced to the greatest extent.
Description
Technical field
The present invention is applied to digital signal processing technique field, particularly a kind of method of the design of the serial FFTIP core based on FPGA parallel FFT IP kernel.
Background technology
At present in electronic reconnaissance field, in order to improve the intercept probability to all kinds of broadband signal, needing electronic detection system to have larger momentary signal and covering bandwidth.Adopt broad-band channel receiver can obtain larger momentary signal bandwidth, but implement technical more complicated.Traditional channelized receiver adopts mimic channel to realize multi-channel filter, due to the restriction of analog device performance, this receiver volume is larger, interchannel consistance is poor, and the circuit of each passage needs designer to carry out constantly repeatedly debugging just reaching performance requirement, workload and cost price higher.Along with the development of digital processing technology, wideband digital channel signal processing technology is used widely.In order to realize wideband digital channel multi-channel digital filtering parallel processing capability, when carrying out the design of wideband digital channel multi-channel parallel processor, need directly to utilize hardware description language to design according to FFT structure, realize more complicated, design efficiency is lower, and design verification is more difficult.
The present invention adopts wideband digital receiver Parallel processing designs thought, SystemGenerator upgrade kit is utilized to carry out the design of wideband digital channel signal processor, so that the design of hardware and software of Processing Algorithm realizes and checking, and improve the reliability of wideband digital channel signal processor design.High-speed AD is utilized to carry out high-speed sampling to the broadband signal of detecing receipts, then the high speed multiphase filtering channelizing treatment technology designing realization in PFGA is utilized, realize the wideband digital channel signal processor of parameter configuration flexibility and changeability, the consistance of channel can be ensured, reduce volume and debugging difficulty, save manpower, financial resources cost.Simultaneously in order to realize wideband digital channel signal processor parameter configuration flexibly, to modify according to different demands, the FPGA serial FFT core that the present invention utilizes Xilinx to provide devises a kind of parallel FFTIP core, and based on this parallel FFT IP kernel, in FPGA, design achieves a kind of 8 channel wideband digital channelizing Parallel signal processing machines, can meet different signals and detect receipts demand.
Summary of the invention
The present invention is the method that the design of a kind of serial FFTIP core based on FPGA realizes wideband digital channel Parallel signal processing machine, comprises and utilizes SystemGenerator upgrade kit to carry out the emulation design method of wideband digital channel parallel processor and a kind of method utilizing the serial FFTIP core design parallel FFT process IP kernel of FPGA.
The wideband digital channel method for parallel processing based on serial FFTIP core that the present invention proposes, concrete technical scheme is: a kind of parallel FFTIP core of serial FFTIP core design utilizing Xilinx to provide; Based on parallel FFT Processing Algorithm, derive to the flow process of wideband digital channel Processing Algorithm according to parallel FFT process, what obtain wideband digital channel parallel processing algorithm realizes structure; Matlab is utilized to programme to the wideband digital channel parallel processing algorithm based on parallel FFT process, utilize the SystemGenerator specific purpose tool module that Xilinx company in Simulink provides, the design matched is re-started to wideband digital channel parallel processing algorithm realize with the parallel realization structure of FPGA; Utilize the CMOS macro cell pumping signal that Simulink environment provides, utilize its test module provided to verify design simultaneously; In proof procedure to comprising the bit wide of every coagulation, the coefficient of channel model, the bit wide of channel model, the bit wide of FFT twiddle factor constantly revise, and when meeting design objective, reduces resources occupation rate as far as possible.
The present invention design in FPGA achieve a kind of wideband digital channel method for parallel processing based on serial FFTIP core 8 channel wideband digital channelizing Parallel signal processing machines, mainly comprise broadband signal acquisition module and multiphase filtering channelizing processing module, wherein broadband signal acquisition module comprises low-jitter clock generation circuit, gain circuitry and automatic gaining controling algorithm, for the collection of broadband signal; Multiphase filtering channelizing processing module comprises extraction, index is multiplied, FIR filtering, complex multiplication and parallel FFT module, for the broadband signal filtering gathered; Parallel FFT module is made up of matrix transpose module and duplex flow IP kernel.The data of input are divided into group according to often organizing 8 data by 8 channel wideband digital channelizing Parallel signal processing machines, respectively parallel-serial conversion is carried out to 8 data often organized, incoming serial FFT core, often organize 8 circuit-switched data, a clock period of every road time delay, the time delay simultaneously guaranteeing every road FFT core Output rusults in sequential is fixing, makes eight road FFT export data every road Bi Shang mono-clock period of tunnel time delay; The process of continual flowing water parallel-serial conversion is carried out to Output rusults, realizes parallel data input and the effect of parallel data output; Due to input data and output data timing order relation really, ensure that the continuous input of data stream and export continuously.
The technical scheme that the present invention proposes can process in real time to number digital channelizing realizing 8 passage 125MHz bandwidth of collecting mail of detecing that bandwidth is 1GHz, the checking of its function and performance is shown, the 8 channel wideband digital channelizing Parallel signal processing facility designing realization based on parallel FFT IP kernel in FPGA have the real-time allocative abilities of parameter flexibly, according to different application demand option and installment parameters, different detection signal processing capacities can be realized.
Accompanying drawing explanation
Fig. 1 wideband digital channel realizes block diagram.
Fig. 2 non-blind area multiphase filtering channelization structure model.
The Parallel FFT Architecture model that Fig. 3 utilizes FFTIP to build.
Embodiment
The present invention is in the wideband digital channel recipient processor of design wideband electronic signal detection system, a kind of FPGA design of Simulation instrument SystemGenerator based on Matlab/Simulink environment utilizing Xilinx company to provide, carries out the wideband digital channel Processing Algorithm design of Simulation with the seamless connection of Matlab/Simulink environment.Specific design performing step is as follows:
The first step: derive to the flow process of wideband digital channel Processing Algorithm according to parallel FFT process, what obtain wideband digital channel parallel processing algorithm realizes structure.
Second step: utilize Matlab to programme to the wideband digital channel parallel processing algorithm based on parallel FFT process, the correctness of checking parallel processing algorithm.
3rd step: to the wideband digital channel parallel processing algorithm after Matlab checking, the structure utilizing Simulink to provide re-starts the design matched with the parallel realization structure of FPGA and realizes.
4th step: utilize the CMOS macro cell pumping signal that Simulink environment provides, utilizes its test module provided to verify design simultaneously.
5th step: utilize the SystemGenerator specific purpose tool module that Xilinx company in Simulink provides, carries out FPGA design to wideband digital channel parallel processing algorithm and realizes.The design utilizing this instrument to realize only has the module utilizing Xilinx to provide could realize in FPGA.In the realization that the core of FPGA middle width strip digital channelizing parallel processing algorithm realization is parallel FFT core, concrete grammar is, a kind of parallel FFT core of serial FFT core design utilizing Xilinx to provide, the data of input are divided in groups, the parallel-serial conversion stream treatment of data is carried out by group, convert parallel data to serial data, guarantee to carry out flowing water conversion process to the parallel data of input incessantly simultaneously in sequential.In the present invention, the data of 8 parallel FFT inputs are divided into group according to often organizing 8 data, respectively parallel-serial conversion is carried out, incoming serial FFT core to 8 data often organized, often organizes 8 circuit-switched data, a clock period of every road time delay, the time delay of every road FFT core Output rusults is certain simultaneously.So 8 road Output rusults are also every clock period of circuit-switched data Bi Shang mono-tunnel time delay.Parallel-serial conversion is carried out to Output rusults, realizes parallel data input and the effect of parallel data output.And due to input data and output data timing order relation really, ensure that the continuous input of data stream and export continuously.
6th step: the abundant FPGA program design of module to wideband digital channel parallel processing algorithm utilizing Simulink self to provide outside the border realized is verified, constantly the parameter that wideband digital channel parallel processing algorithm FPGA realizes is revised in proof procedure, mainly comprise the bit wide of every coagulation, the coefficient of channel model, the bit wide of channel model, the bit wide of FFT twiddle factor, when meeting design objective, reduce resources occupation rate as far as possible.
Claims (3)
1. based on a wideband digital channel method for parallel processing for serial FFTIP core, it is characterized in that: a kind of parallel FFTIP core of serial FFTIP core design utilizing Xilinx to provide; Based on parallel FFT Processing Algorithm, derive to the flow process of wideband digital channel Processing Algorithm according to parallel FFT process, what obtain wideband digital channel parallel processing algorithm realizes structure; Matlab is utilized to programme to the wideband digital channel parallel processing algorithm based on parallel FFT process, utilize the SystemGenerator specific purpose tool module that Xilinx company in Simulink provides, the design matched is re-started to wideband digital channel parallel processing algorithm realize with the parallel realization structure of FPGA; Utilize the CMOS macro cell pumping signal that Simulink environment provides, utilize its test module provided to verify design simultaneously; In proof procedure to comprising the bit wide of every coagulation, the coefficient of channel model, the bit wide of channel model, the bit wide of FFT twiddle factor constantly revise, and when meeting design objective, reduces resources occupation rate as far as possible.
2. method according to claim 1 designs the one 8 channel wideband digital channelizing Parallel signal processing machine of realization in FPGA, be primarily characterized in that and comprise broadband signal acquisition module and multiphase filtering channelizing processing module, wherein broadband signal acquisition module comprises low-jitter clock generation circuit, gain circuitry and automatic gaining controling algorithm, for the collection of broadband signal; Multiphase filtering channelizing processing module comprises extraction, index is multiplied, FIR filtering, complex multiplication and parallel FFT module, for the broadband signal filtering gathered; Parallel FFT module is made up of matrix transpose module and duplex flow IP kernel.
3. 8 channel wideband digital channelizing Parallel signal processing machines according to claim 2, be primarily characterized in that and the data of input are divided into group according to often organizing 8 data, respectively parallel-serial conversion is carried out to 8 data often organized, incoming serial FFT core, often organize 8 circuit-switched data, a clock period of every road time delay, in sequential, guarantee that the time delay of every road FFT core Output rusults is fixing simultaneously, make eight road FFT export data every road Bi Shang mono-clock period of tunnel time delay; The process of continual flowing water parallel-serial conversion is carried out to Output rusults, realizes parallel data input and the effect of parallel data output; Due to input data and output data timing order relation really, ensure that the continuous input of data stream and export continuously.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109001532A (en) * | 2018-05-08 | 2018-12-14 | 浙江万里学院 | Analog signal FFT implementation method and its circuit based on FPGA |
| CN109525256A (en) * | 2018-10-18 | 2019-03-26 | 哈尔滨工程大学 | A kind of channelizing emitting structural of the narrow transition band filter group based on FPGA |
| CN109617631A (en) * | 2018-12-28 | 2019-04-12 | 华航高科(北京)技术有限公司 | Reconnaissance system adaptive reception method based on the measurement of digital channelizing instantaneous parameters |
| CN111367256A (en) * | 2020-03-03 | 2020-07-03 | 中国船舶重工集团公司第七0七研究所九江分部 | RVDT steering hand wheel control device and automatic detection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070005830A1 (en) * | 2005-06-29 | 2007-01-04 | Yancey Jerry W | Systems and methods for weighted overlap and add processing |
| CN103559019A (en) * | 2013-11-08 | 2014-02-05 | 上海航天测控通信研究所 | Universal floating point full-pipeline FFT (Fast Fourier Transform) operation IP (Internet Protocol) core |
| CN104931968A (en) * | 2015-06-18 | 2015-09-23 | 西安电子科技大学 | FPGA-based InSAR channel amplitude and phase error estimation method |
-
2015
- 2015-11-05 CN CN201510747090.5A patent/CN105446702A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070005830A1 (en) * | 2005-06-29 | 2007-01-04 | Yancey Jerry W | Systems and methods for weighted overlap and add processing |
| CN103559019A (en) * | 2013-11-08 | 2014-02-05 | 上海航天测控通信研究所 | Universal floating point full-pipeline FFT (Fast Fourier Transform) operation IP (Internet Protocol) core |
| CN104931968A (en) * | 2015-06-18 | 2015-09-23 | 西安电子科技大学 | FPGA-based InSAR channel amplitude and phase error estimation method |
Non-Patent Citations (2)
| Title |
|---|
| 贾一凡: "基于System Generator的信道化发射模块设计", 《信息通信》 * |
| 顾何方: "基于XILINX IP核的并行信道化收发模块设计", 《信息通信》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109001532A (en) * | 2018-05-08 | 2018-12-14 | 浙江万里学院 | Analog signal FFT implementation method and its circuit based on FPGA |
| CN109525256A (en) * | 2018-10-18 | 2019-03-26 | 哈尔滨工程大学 | A kind of channelizing emitting structural of the narrow transition band filter group based on FPGA |
| CN109617631A (en) * | 2018-12-28 | 2019-04-12 | 华航高科(北京)技术有限公司 | Reconnaissance system adaptive reception method based on the measurement of digital channelizing instantaneous parameters |
| CN109617631B (en) * | 2018-12-28 | 2021-09-14 | 华航高科(北京)技术有限公司 | Adaptive receiving method of reconnaissance system based on digital channelized instantaneous parameter measurement |
| CN111367256A (en) * | 2020-03-03 | 2020-07-03 | 中国船舶重工集团公司第七0七研究所九江分部 | RVDT steering hand wheel control device and automatic detection method |
| CN111367256B (en) * | 2020-03-03 | 2022-03-29 | 中国船舶重工集团公司第七0七研究所九江分部 | RVDT steering hand wheel control device and automatic detection method |
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Application publication date: 20160330 |