CN106803750B

CN106803750B - Multichannel running water FIR filter

Info

Publication number: CN106803750B
Application number: CN201710022449.1A
Authority: CN
Inventors: 李世平; 陈铠; 周海斌; 何国强
Original assignee: CETC 14 Research Institute
Current assignee: CETC 14 Research Institute
Priority date: 2017-01-12
Filing date: 2017-01-12
Publication date: 2020-01-10
Anticipated expiration: 2037-01-12
Also published as: CN106803750A

Abstract

The invention discloses a multichannel running water FIR filter, which comprises a channel merging device, a zero-order filtering unit, a plurality of serial general filtering units and a channel splitting device, wherein M paths of input data are merged into one path of output after passing through the channel merging device; one path of output signal of the zero-level filter unit enters a buffer shifter, enters a second multiplier through buffer shift, performs multiplication operation with the output signal of the second coefficient storage unit, outputs the result to a multiplication output register group, adds the delayed signal and the other path of output signal of the zero-level filter unit through an adder, and outputs the result to an addition output register group; and the channel splitting device is used for extracting parallel M paths of data from the serial filtering signals and outputting the data. The invention has high operation efficiency, supports the interrupt transmission of input data, has simple cascade mode, easy expansion of order and strong universality.

Description

Multichannel running water FIR filter

Technical Field

The invention relates to the technical field of filters, in particular to a multichannel running water FIR filter.

Background

With the increasing demand of the fields of radar, communication and the like for broadband systems, the broadband digital array processing technology is widely applied. For a wideband digital array system, in order to compensate for the mismatch of frequency responses between channels, a digital FIR equalization filter needs to be connected in series in each channel, so that the frequency responses of all channels are consistent. To ensure system real-time, the digital FIR equalization filter is usually implemented by FPGA or dedicated ASIC.

In the traditional N-order FIR time domain, running water calculation is usually realized by N multipliers and adders connected in series, and the main frequency of the multipliers and the input effective data rate are kept consistent. However, as the actual data rate of the digital array varies from system to system, with the rapid development of the integrated circuit, the main frequency of the FPGA, especially the ASIC, is higher and higher, the working main frequency of the typical ASIC can be up to more than 1GHz, and the actual input data rate is only hundreds of M magnitude, typically 200M. Obviously, for the multiplier-adder working at 1GHz dominant frequency, 80% of the time is in an idle state when processing 200MHz input data, and the operation efficiency is extremely low. Therefore, it is necessary to design a multi-channel running water FIR filter based on the time-division multiplexing principle to implement time-division calculation of multi-channel FIR filtering, thereby fully exerting the advantage of high working dominant frequency and improving the operation efficiency.

Disclosure of Invention

The invention provides a Multi-Channel pipeline FIR (MCP-FIR) filter, and develops an MCP-FIR filter module which is simultaneously suitable for an FPGA and a special ASIC. The method aims to complete the pipelined FIR filtering of a plurality of channels through time-sharing calculation of a group of high-dominant-frequency multiplier-adders according to the relation between working dominant frequencies and actual input data rates, and the number of the channels can be dynamically configured.

A multi-channel running water FIR filter comprises a channel merging device, a zero-order filtering unit, a plurality of general filtering units connected in series and a channel splitting device in sequence, wherein M paths of input data are merged into one path of output after passing through the channel merging device, and M is an integer greater than or equal to 1; the zero-level filtering unit comprises a first multiplier, a zero-level coefficient storage unit, a first input register group, a first output register group and a first control register group, output signals of the zero-level coefficient storage unit and the input register group are used as the input of the multiplier to be multiplied, and the result enters the output register group; the general filter unit comprises a second multiplier, a first adder, a buffer shifter, a second coefficient storage unit, a multiplication output register, an addition output register group and a second control register group, wherein one path of output signal of the zero-level filter unit enters the buffer shifter, enters the second multiplier through buffer shift, is subjected to multiplication operation with the output signal of the second coefficient storage unit, the result is output to the multiplication output register group, and the delayed signal and the other path of output signal of the zero-level filter unit are added through the adder and then output to the addition output register group; the output signals of the addition output register group and the buffer shifter enter a next general filtering unit and are sequentially cascaded; and the channel splitting device is used for extracting parallel M paths of data from the serial filtering signals and outputting the data.

The coefficient storage unit is a register file or a RAM, but is not limited to the two storage structures;

the multiplier includes, but is not limited to, any one of a fixed-point real multiplier, a fixed-point complex multiplier, a floating-point real multiplier, and a floating-point complex multiplier.

The invention has the following beneficial effects:

1. under the application condition of high working dominant frequency and low data rate, the running water FIR filtering operation of a plurality of input channels is completed in a time-sharing manner by adopting the multiply-add resource of an FIR filter, and the operation efficiency is high;

2. the input/output interface conforms to a non-blocking standard AXI4-Stream interface and supports input data interrupt transmission;

3. the N-order FIR filtering calculation is realized through 1 zero-order filtering unit and the cascaded N-1 general filtering units, the cascade mode is simple, and the order is easy to expand;

4. the number of channels can be dynamically configured, the method is suitable for different application scenes, and the universality is high.

Drawings

FIG. 1 is a block diagram of the multi-channel pipelined FIR filter of the present invention;

FIG. 2 is a diagram of a zero-level filtering unit in an embodiment of a multi-channel running water FIR filter;

FIG. 3 is a block diagram of a general filtering unit in another embodiment of a multi-channel pipelined FIR filter;

FIG. 4 is a timing diagram of the operation of a 16 th order FIR filter of still another embodiment 3.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Firstly, M channel data input in parallel are merged into one channel in a time-sharing mode, then, 1 zero-order filter unit and N-1 cascaded general filter units are adopted to carry out multichannel running water N-order FIR filter operation on the channel data, N multipliers and N-1 adders are consumed in total, and finally, an operation result is split into M channels in a time-sharing mode and is output in a parallel mode, and a structural block diagram is shown in figure 1. Wherein, s _ AXI _ data _ i is ith input data, M _ AXI _ data _ i is ith output data after calculation is completed, i is 0,1, … M-1, input and output interfaces all conform to a non-blocking standard AXI4-Stream interface, and the number of channels M can be dynamically configured by the input interface s _ M _ value.

Let the coefficient of the ith N-order FIR filter be h_n(i, j), the input data is D (i, k), the output result is Q (i, k), and then after the MCP-FIR is adopted to complete N-order FIR filtering of M channels, the following can be obtained:

wherein j is 0,1, …, N-1, K is 0,1, …, K + N-1, and K is the total number of input points.

The function of each module in the MCP-FIR is described as follows:

(1) channel merging

The channel merging device is used for completing parallel-serial conversion, namely merging the data of M channels input in parallel into one path for output in a time-sharing manner. Setting the input data rate as fin and the work dominant frequency fwork, wherein the work dominant frequency meets the following requirements: fwork is greater than or equal to M x fin. The method comprises the steps of respectively setting a shift register for each path of data, shifting an ith path by i effective clock cycles (the clock cycle corresponding to the valid time of s _ axi _ valid is called as a valid clock cycle, and the same applies below, the shift is not carried out when the valid time of s _ axi _ valid is invalid), and polling and selecting output from M paths of shifted data, so that kth% M (% represents remainder and the same applies below) path data is output in the kth effective clock cycle, wherein i is 0,1, …, M-1, k is 0,1, ….

(2) Zero-order filtering unit

The zero-level filtering unit comprises a first multiplier, a zero-level coefficient storage unit, a first input register group, a first output register group and a first control register group. The structure block diagram is shown in fig. 2.

The coefficient storage unit comprises M data registers, the 1 st-order FIR coefficients corresponding to the M paths of input data are stored respectively, when the k-th effective data arrives, the FIR coefficients corresponding to the k% M paths are selected and output to the multiplier, and k is 0,1 and …. The first multiplier completes the multiplication operation of the data and the FIR coefficient.

The register group realizes the delay of input data in different stages through different numbers of registers, is mainly used for effective data alignment when a zero-order filter unit and a general filter unit are cascaded, and ensures that two paths of output meet the time sequence requirement of the general filter unit.

(3) Universal filter unit

The general filtering unit comprises a second multiplier, a first adder, a buffer shifter, a second coefficient storage unit, a multiplication output register, an addition output register group and a second control register group. The structure block diagram is shown in fig. 3.

The function of the coefficient memory unit, the multiplier and the register bank is the same as that in the zero-level filter unit.

The buffer shifter is mainly used for realizing an interrupt transmission function, and when the working main frequency and the actual data rate are not in integral multiple or the data rate is reduced for use, the data after channel combination is invalid, so that interrupt transmission is caused. The buffer shifter is controlled by the input s _ axi _ valid _1 to perform buffer shift, when the s _ axi _ valid _1 is valid, the buffer shifter has a function equivalent to an M + 1-stage shift register, when the s _ axi _ valid _1 is invalid, the current shift state is latched, and the current invalid data is immediately output in the next clock cycle until the s _ axi _ valid _1 is valid again and then is shifted continuously. The output of the buffer is sent to the multiplier and is output to the next stage as m _ axi _ data _ 1.

The adder is used for completing the addition operation of the output result of the multiplier and the previous stage input s _ axi _ data _2, and the addition result is output as the current stage m _ axi _ data _ 2. The output of the adder of the N-1 th-stage general filtering unit is the operation result after N-order FIR filtering of M channels.

(4) Channel splitting

The channel splitting device is used for completing serial-parallel conversion, namely extracting parallel M paths of data from serial M channel FIR filtering results and outputting the data. The method comprises the steps of firstly carrying out M paths of shifts on input data respectively, shifting an ith path by M-i-1 effective clock cycles, and simultaneously outputting M paths of shifted results when k% M is M-1 in a kth clock cycle, wherein i is 0,1, …, M-1, k is 0,1 and ….

The N-level FIR filtering of the M channels with the structure is realized by the following steps:

firstly, configuring the current channel number M, then inputting M channel data through a standard non-blocking AXI interface, carrying out parallel-serial conversion by a channel merging device, and merging the M channel data into one path for outputting in a time-sharing manner;

secondly, the combined data is sequentially subjected to a zero-level filtering unit and a cascaded N-1-level general filtering unit to complete the multiply-add operation of the input data of the M channel and the FIR coefficient of the corresponding channel to obtain an FIR operation result;

and finally, completing serial conversion through the channel splitting device, and separating M channel data according to a time sequence to output in parallel.

N-order running water FIR calculation of M channels under low data rate is realized by adopting N multiplier-adders with high main frequency, and the operation efficiency is high; FIR calculation is carried out in a mode of cascading 1 zero-level filter unit and N-1 general filter units, full flowing performance is achieved, the cascading mode is simple, and the order is easy to expand; the buffer shift mechanism ensures that the multiplier-adder can correctly identify and process valid data when the input data jumps between invalid and valid, thereby realizing the function of interruptable transmission; the number of the channels can be dynamically configured, the method is suitable for different application scenes, and the universality is high.

According to the technical scheme, under the application requirements of 500MHz working main frequency of an ASIC, 160M average data rate of input single channel and 16 orders, a 3-channel 16-order running-water FIR filter is designed, wherein a first input register group in a zero-order filtering unit is 1 level, and a first output register group and a first control register group are 3 levels; the multiplication output register set in the general filtering unit is 2 stages, the addition output register set and the second control register set are 1 stage, and the working timing diagram is shown in fig. 4.

For convenience of timing sequence description, it is assumed that all FIR coefficients corresponding to 3 channels are 1,4,7, and … in the input data are 1 st channel input data, 2,5,8, and … in the input data are 2 nd channel input data, 3,6,9, and … in the input data are 3 rd channel input data, ① represents an output of channel combination, ② represents an output of a zero-level filter unit, ③ and ⑤ represent 2 outputs of a 1 st-stage general filter unit, ④ represents an input of an adder inside the 1 st-stage general filter unit, ⑥ and ⑧ represent 2 outputs of a 2 nd-stage general filter unit, and ⑦ represents an input of an adder inside the 2 nd-stage general filter unit.

It can be seen that after the input data of the three channels pass through the channel merging module, the parallel 3-way data are arranged in series and output in a time-sharing manner, valid is invalid in the 7 th clock cycle, and is recovered to be valid in the 10 th clock cycle, the zero-level filtering unit finishes the output after the multiplication, and because the first output register group is 3 levels, ② is delayed by 3 clock cycles relative to ①, and the invalid data is also delayed by 3 clock cycles, meanwhile, ① is directly sent to the 1 st-level general filtering unit.

When multiplication operations are performed in the zero-order filtering unit and the general filtering unit, the coefficient storage unit in the unit can sequentially extract the FIR coefficients of the corresponding paths according to the number of the effective data and the remainder of 3 and send the FIR coefficients to the multiplier, so that the corresponding FIR coefficients are correctly used by the three paths of input data.

In the 1 st stage general filter unit, ① is buffered and shifted, when data is valid, 4 stages of shift are directly performed, when data is invalid, the current shift state is latched, invalid data is preferentially output in the next clock cycle until the data in the 10 th clock cycle is restored to be valid, the shift operation is continuously started in the next clock cycle, the buffered and shifted data ③ is simultaneously sent to an internal multiplier and a 2 nd stage general filter unit, the output of the multiplier is delayed by 2 stages to obtain ④ and sent to an internal adder, the adder completes the addition of ④ and ② and delays by 1 stage to obtain ⑤ and sends the ⑤ to the 2 nd stage general filter unit.

The working mechanism in the 2 nd stage general filter unit is the same as that in the 1 st stage, the ③ is buffered and shifted to output ⑥, the output of the internal multiplier is ⑦ after 2 stages of delay, and the internal adder adds ⑤ and ⑦ and delays 1 stage to obtain ⑧ and ⑧ which are continuously sent to the 3 rd stage filter unit.

By analogy, the 15 th stage filtering unit outputs a 16-order FIR filtering result which is 3 paths of input data, the channel splitting module completes serial-parallel conversion, and 3 paths of data are separated according to time sequence to obtain the required parallel result output of 3 channels.

The input s _ axi _ last signal represents the last data currently input, the signal carries out corresponding period shift according to the actual data delay value in each stage of filtering unit, and finally the m _ axi _ last signal is output to represent and output the last result of FIR operation.

The technical means disclosed in the invention scheme are not limited to the technical means disclosed in the above embodiments, but also include the technical scheme formed by any combination of the above technical features.

Claims

1. A multi-channel, in-line FIR filter, characterized by: the device sequentially comprises a channel merging device, a zero-level filtering unit, a plurality of general filtering units and a channel splitting device which are connected in series, wherein M paths of input data are merged into one path of output after passing through the channel merging device, and M is an integer greater than or equal to 1; the zero-level filtering unit comprises a first multiplier, a zero-level coefficient storage unit, a first input register group, a first output register group and a first control register group, output signals of the zero-level coefficient storage unit and the input register group are used as the input of the multiplier to be multiplied, and the result enters the output register group; the general filtering unit comprises a second multiplier, a first adder, a buffer shifter, a second coefficient storage unit, a multiplication output register, an addition output register group and a second control register group, wherein the state of the buffer shifter is controlled by an interrupt signal, when the interrupt signal is effective, the buffer shifter is equivalent to an M + 1-level shift register, when the interrupt signal is invalid, the buffer shifter latches the current shift state, and outputs an invalid interrupt signal in the next clock cycle until the interrupt signal is effective again and then continues to shift; one path of output signal of the zero-level filter unit enters the buffer shifter, enters the second multiplier through buffer shift, performs multiplication operation with the output signal of the second coefficient storage unit, outputs the result to a multiplication output register group, adds the delayed signal and the other path of output signal of the zero-level filter unit through the adder, and outputs the result to an addition output register group; the output signals of the addition output register group and the buffer shifter enter a next general filtering unit and are sequentially cascaded; and the channel splitting device is used for extracting parallel M paths of data from the serial filtering signals and outputting the data.

2. The multi-channel running water FIR filter according to claim 1, characterized in that: the coefficient storage unit is a register file or a RAM.

3. The multi-channel running water FIR filter according to claim 1, characterized in that: the multiplier is any one of a fixed-point real number multiplier, a fixed-point complex number multiplier, a floating-point real number multiplier and a floating-point complex number multiplier.